31:28

REL

Core Release. One digit, BCD-coded.

RO

0x3

27:24

STEP

Step of Core Release. One digit, BCD-coded.

RO

0x2

23:20

SUBSTEP

Sub-Step of Core Release. One digit, BCD-coded.

RO

0x3

19:16

YEAR

Time Stamp Year. One digit, BCD-coded.

RO

0x8

15:8

MON

Time Stamp Month. Two digits, BCD-coded.

RO

0x06

7:0

DAY

Time Stamp Day. Two digits, BCD-coded.

RO

0x08

31:0

ETV

Endianess Test Value. Reading the constant value maintained in this register allows software to determine the endianess of the host CPU.

RO

0x8765 4321

31:24

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

RO

0x00

23

TDC

Transmitter Delay Compensation
0 Transmitter Delay Compensation disabled
1 Transmitter Delay Compensation enabled

+I107

RW

0

22:21

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

RO

0x0

20:16

DBRP

Data Bit Rate Prescaler. The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Bit Rate Prescaler are 0 to 31. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used.

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.

RW

0x00

15:13

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

RO

0x0

12:8

DTSEG1

Data Time Segment Before Sample Point. Valid values are 0 to 31. The actual interpretation by the hardware of this value is such that one more than the programmed value is used.

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.

RW

0x0A

7:4

DTSEG2

Data Time Segment After Sample Point. Valid values are 0 to 15. The actual interpretation by the hardware of this value is such that one more than the programmed value is used.

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.

RW

0x3

3:0

DSJW

Data Resynchronization Jump Width. Valid values are 0 to 15. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used.

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.

RW

0x3

31:8

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

RO

0x00 0000

7

RX

Receive Pin. Monitors the actual value of the CAN receive pin.
0 The CAN bus is dominant (CAN RX pin = '0')
1 The CAN bus is recessive (CAN RX pin = '1')

RO

X

6:5

TX

Control of Transmit Pin
00 CAN TX pin controlled by the CAN Core, updated at the end of the CAN bit time
01 Sample Point can be monitored at CAN TX pin
10 Dominant ('0') level at CAN TX pin
11 Recessive ('1') at CAN TX pin

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.

RW

0x0

4

LBCK

Loop Back Mode
0 Reset value, Loop Back Mode is disabled
1 Loop Back Mode is enabled

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.

RW

0

3:0

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

RO

0x0

31:16

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

RO

0x0000

15:8

WDV

Watchdog Value. Actual Message RAM Watchdog Counter Value.

The RAM Watchdog monitors the READY output of the Message RAM. A Message RAM access via the MCAN's Generic Commander Interface starts the Message RAM Watchdog Counter with the value configured by the WDC field. The counter is reloaded with WDC when the Message RAM signals successful completion by activating its READY output. In case there is no response from the Message RAM until the counter has counted down to zero, the counter stops and interrupt flag IR.WDI is set. The RAM Watchdog Counter is clocked by the host (system) clock.

RO

0x00

7:0

WDC

Watchdog Configuration. Start value of the Message RAM Watchdog Counter. With the reset value of "00" the counter is disabled.

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.

RW

0x00

31:16

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

RO

0x0000

15

NISO

Non ISO Operation. If this bit is set, the MCAN uses the CAN FD frame format as specified by the Bosch CAN FD Specification V1.0.
0 CAN FD frame format according to ISO 11898-1:2015
1 CAN FD frame format according to Bosch CAN FD Specification V1.0

RW

0

14

TXP

Transmit Pause. If this bit is set, the MCAN pauses for two CAN bit times before starting the next transmission after itself has successfully transmitted a frame.
0 Transmit pause disabled
1 Transmit pause enabled

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.

RW

0

13

EFBI

Edge Filtering during Bus Integration
0 Edge filtering disabled
1 Two consecutive dominant tq required to detect an edge for hard synchronization

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.

RW

0

12

PXHD

Protocol Exception Handling Disable
0 Protocol exception handling enabled
1 Protocol exception handling disabled
Note: When protocol exception handling is disabled, the MCAN will transmit an error frame when it detects a protocol exception condition.

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.

RW

0

11:10

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

RO

0x0

9

BRSE

Bit Rate Switch Enable
0 Bit rate switching for transmissions disabled
1 Bit rate switching for transmissions enabled
Note: When CAN FD operation is disabled FDOE = '0', BRSE is not evaluated.

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.

RW

0

8

FDOE

Flexible Datarate Operation Enable
0 FD operation disabled
1 FD operation enabled

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.

RW

0

7

TEST

Test Mode Enable
0 Normal operation, register TEST holds reset values
1 Test Mode, write access to register TEST enabled

Qualified Write 1 to Set is possible only with CCCR.CCE='1' and CCCR.INIT='1'.

RW

0

6

DAR

Disable Automatic Retransmission
0 Automatic retransmission of messages not transmitted successfully enabled
1 Automatic retransmission disabled

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.

RW

0

5

MON

Bus Monitoring Mode. Bit MON can only be set by SW when both CCE and INIT are set to '1'. The bit can be reset by SW at any time.
0 Bus Monitoring Mode is disabled
1 Bus Monitoring Mode is enabled

Qualified Write 1 to Set is possible only with CCCR.CCE='1' and CCCR.INIT='1'.

RW

0

4

CSR

Clock Stop Request
0 No clock stop is requested
1 Clock stop requested. When clock stop is requested, first INIT and then CSA will be set after all pending transfer requests have been completed and the CAN bus reached idle.

RW

0

3

CSA

Clock Stop Acknowledge
0 No clock stop acknowledged
1 MCAN may be set in power down by stopping the Host and CAN clocks

RO

0

2

ASM

Restricted Operation Mode. Bit ASM can only be set by SW when both CCE and INIT are set to '1'. The bit can be reset by SW at any time.
0 Normal CAN operation
1 Restricted Operation Mode active

Qualified Write 1 to Set is possible only with CCCR.CCE='1' and CCCR.INIT='1'.

RW

0

1

CCE

Configuration Change Enable
0 The CPU has no write access to the protected configuration registers
1 The CPU has write access to the protected configuration registers (while CCCR.INIT = '1')

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.

RW

0

0

INIT

Initialization
0 Normal Operation
1 Initialization is started
Note: Due to the synchronization mechanism between the two clock domains, there may be a delay until the value written to INIT can be read back. Therefore the programmer has to assure that the previous value written to INIT has been accepted by reading INIT before setting INIT to a new value.

RW

1

31:25

NSJW

Nominal (Re)Synchronization Jump Width. Valid values are 0 to 127. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used.

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.

RW

0x03

24:16

NBRP

Nominal Bit Rate Prescaler. The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Bit Rate Prescaler are 0 to 511. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used.

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.

RW

0x000

15:8

NTSEG1

Nominal Time Segment Before Sample Point. Valid values are 1 to 255. The actual interpretation by the hardware of this value is such that one more than the programmed value is used.

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.

RW

0x0A

7

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

RO

0

6:0

NTSEG2

Nominal Time Segment After Sample Point. Valid values are 1 to 127. The actual interpretation by the hardware of this value is such that one more than the programmed value is used.

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.

RW

0x03

31:20

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

RO

0x000

19:16

TCP

Timestamp Counter Prescaler. Configures the timestamp and timeout counters time unit in multiples of CAN bit times. Valid values are 0 to 15. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used.

Note: With CAN FD an external counter is required for timestamp generation (TSS = "10").

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.

RW

0x0

15:2

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

RO

0x0000

1:0

TSS

Timestamp Select
00 Timestamp counter value always 0x0000
01 Timestamp counter value incremented according to TCP
10 External timestamp counter value used
11 Same as "00"

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.

RW

0x0

31:16

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

RO

0x0000

15:0

TSC

Timestamp Counter. The internal/external Timestamp Counter value is captured on start of frame (both Rx and Tx). When TSCC.TSS = "01", the Timestamp Counter is incremented in multiples of CAN bit times, (1...16), depending on the configuration of TSCC.TCP. A wrap around sets interrupt flag IR.TSW. Write access resets the counter to zero. When TSCC.TSS = "10", TSC reflects the External Timestamp Counter value, and a write access has no impact.

Note: A "wrap around" is a change of the Timestamp Counter value from non-zero to zero not
caused by write access to TSCV.

RW

0x0000

31:16

TOP

Timeout Period. Start value of the Timeout Counter (down-counter). Configures the Timeout Period.

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.

RW

0xFFFF

15:3

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

RO

0x0000

2:1

TOS

Timeout Select. When operating in Continuous mode, a write to TOCV presets the counter to the value configured by TOCC.TOP and continues down-counting. When the Timeout Counter is controlled by one of the FIFOs, an empty FIFO presets the counter to the value configured by TOCC.TOP. Down-counting is started when the first FIFO element is stored.
00 Continuous operation
01 Timeout controlled by Tx Event FIFO
10 Timeout controlled by Rx FIFO 0
11 Timeout controlled by Rx FIFO 1

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.

RW

0x0

0

ETOC

Enable Timeout Counter
0 Timeout Counter disabled
1 Timeout Counter enabled

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.

RW

0

31:16

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

RO

0x0000

15:0

TOC

Timeout Counter. The Timeout Counter is decremented in multiples of CAN bit times, (1...16), depending on the configuration of TSCC.TCP. When decremented to zero, interrupt flag IR.TOO is set and the Timeout Counter is stopped. Start and reset/restart conditions are configured via TOCC.TOS.

RW

0xFFFF

31:24

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

RO

0x00

23:16

CEL

CAN Error Logging. The counter is incremented each time when a CAN protocol error causes the Transmit Error Counter or the Receive Error Counter to be incremented. It is reset by read access to CEL. The counter stops at 0xFF; the next increment of TEC or REC sets interrupt flag IR.ELO.

Note: When CCCR.ASM is set, the CAN protocol controller does not increment TEC and REC when a CAN protocol error is detected, but CEL is still incremented.

RO

0x00

15

RP

Receive Error Passive
0 The Receive Error Counter is below the error passive level of 128
1 The Receive Error Counter has reached the error passive level of 128

RO

0

14:8

REC

Receive Error Counter. Actual state of the Receive Error Counter, values between 0 and 127.

Note: When CCCR.ASM is set, the CAN protocol controller does not increment TEC and REC when a CAN protocol error is detected, but CEL is still incremented.

RO

0x00

7:0

TEC

Transmit Error Counter. Actual state of the Transmit Error Counter, values between 0 and 255.

Note: When CCCR.ASM is set, the CAN protocol controller does not increment TEC and REC when a CAN protocol error is detected, but CEL is still incremented.

RO

0x00

31:23

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

RO

0x000

22:16

TDCV

Transmitter Delay Compensation Value. Position of the secondary sample point, defined by the sum of the measured delay from the internal CAN TX signal to the internal CAN RX signal and TDCR.TDCO. The SSP position is, in the data phase, the number of mtq between the start of the transmitted bit and the secondary sample point. Valid values are 0 to 127 mtq.

RO

0x00

15

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

RO

0

14

PXE

Protocol Exception Event
0 No protocol exception event occurred since last read access
1 Protocol exception event occurred

RO

0

13

RFDF

Received a CAN FD Message. This bit is set independent of acceptance filtering.
0 Since this bit was reset by the CPU, no CAN FD message has been received
1 Message in CAN FD format with FDF flag set has been received

RO

0

12

RBRS

BRS Flag of Last Received CAN FD Message. This bit is set together with RFDF, independent of acceptance filtering.
0 Last received CAN FD message did not have its BRS flag set
1 Last received CAN FD message had its BRS flag set

RO

0

11

RESI

ESI Flag of Last Received CAN FD Message. This bit is set together with RFDF, independent of acceptance filtering.
0 Last received CAN FD message did not have its ESI flag set
1 Last received CAN FD message had its ESI flag set

RO

0

10:8

DLEC

Data Phase Last Error Code. Type of last error that occurred in the data phase of a CAN FD format frame with its BRS flag set. Coding is the same as for LEC. This field will be cleared to zero when a CAN FD format frame with its BRS flag set has been transferred (reception or transmission) without error.

RO

0x7

7

BO

Bus_Off Status
0 The M_CAN is not Bus_Off
1 The M_CAN is in Bus_Off state

RO

0

6

EW

Warning Status
0 Both error counters are below the Error_Warning limit of 96
1 At least one of error counter has reached the Error_Warning limit of 96

RO

0

5

EP

Error Passive
0 The M_CAN is in the Error_Active state. It normally takes part in bus communication and sends an active error flag when an error has been detected
1 The M_CAN is in the Error_Passive state

RO

0

4:3

ACT

Node Activity. Monitors the module's CAN communication state.
00 Synchronizing - node is synchronizing on CAN communication
01 Idle - node is neither receiver nor transmitter
10 Receiver - node is operating as receiver
11 Transmitter - node is operating as transmitter

Note: ACT is set to "00" by a Protocol Exception Event.

RO

0x0

2:0

LEC

Last Error Code. The LEC indicates the type of the last error to occur on the CAN bus. This field will be cleared to '0' when a message has been transferred (reception or transmission) without error.
0 No Error: No error occurred since LEC has been reset by successful reception or transmission.
1 Stuff Error: More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed.
2 Form Error: A fixed format part of a received frame has the wrong format.
3 AckError: The message transmitted by the MCAN was not acknowledged by another node.
4 Bit1Error: During the transmission of a message (with the exception of the arbitration field), the device wanted to send a recessive level (bit of logical value '1'), but the monitored bus value was dominant.
5 Bit0Error: During the transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device wanted to send a dominant level (data or identifier bit logical value '0'), but the monitored bus value was recessive. During Bus_Off recovery this status is set each time a sequence of 11 recessive bits has been monitored. This enables the CPU to monitor the proceeding of the Bus_Off recovery sequence (indicating the bus is not stuck at dominant or continuously disturbed).
6 CRCError: The CRC check sum of a received message was incorrect. The CRC of an incoming message does not match with the CRC calculated from the received data.
7 NoChange: Any read access to the Protocol Status Register re-initializes the LEC to '7'. When the LEC shows the value '7', no CAN bus event was detected since the last CPU read access to the Protocol Status Register.

Note: When a frame in CAN FD format has reached the data phase with BRS flag set, the next CAN event (error or valid frame) will be shown in DLEC instead of LEC. An error in a fixed stuff bit of a CAN FD CRC sequence will be shown as a Form Error, not Stuff Error. Note: The Bus_Off recovery sequence (see ISO 11898-1:2015) cannot be shortened by setting or resetting CCCR.INIT. If the device goes Bus_Off, it will set CCCR.INIT of its own accord, stopping all bus activities. Once CCCR.INIT has been cleared by the CPU, the device will then wait for 129 occurrences of Bus Idle (129 * 11 consecutive recessive bits) before resuming normal operation. At the end of the Bus_Off recovery sequence, the Error Management Counters will be reset. During the waiting time after the resetting of CCCR.INIT, each time a sequence of 11 recessive bits has been monitored, a Bit0Error code is written to PSR.LEC, enabling the CPU to readily check up whether the CAN bus is stuck at dominant or continuously
disturbed and to monitor the Bus_Off recovery sequence. ECR.REC is used to count these sequences.

RO

0x7

31:15

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

RO

0x0 0000

14:8

TDCO

Transmitter Delay Compensation Offset. Offset value defining the distance between the measured delay from the internal CAN TX signal to the internal CAN RX signal and the secondary sample point. Valid values are 0 to 127 mtq.

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.

RW

0x00

7

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

RO

0

6:0

TDCF

Transmitter Delay Compensation Filter Window Length. Defines the minimum value for the SSP position, dominant edges on the internal CAN RX signal that would result in an earlier SSP position are ignored for transmitter delay measurement. The feature is enabled when TDCF is configured to a value greater than TDCO. Valid values are 0 to 127 mtq.

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.

RW

0x00

31:30

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

RO

0x0

29

ARA

Access to Reserved Address
0 No access to reserved address occurred
1 Access to reserved address occurred

RW

0

28

PED

Protocol Error in Data Phase (Data Bit Time is used)
0 No protocol error in data phase
1 Protocol error in data phase detected (PSR.DLEC ? 0,7)

RW

0

27

PEA

Protocol Error in Arbitration Phase (Nominal Bit Time is used)
0 No protocol error in arbitration phase
1 Protocol error in arbitration phase detected (PSR.LEC ? 0,7)

RW

0

26

WDI

Watchdog Interrupt
0 No Message RAM Watchdog event occurred
1 Message RAM Watchdog event due to missing READY

RW

0

25

BO

Bus_Off Status
0 Bus_Off status unchanged
1 Bus_Off status changed

RW

0

24

EW

Warning Status
0 Error_Warning status unchanged
1 Error_Warning status changed

RW

0

23

EP

Error Passive
0 Error_Passive status unchanged
1 Error_Passive status changed

RW

0

22

ELO

Error Logging Overflow
0 CAN Error Logging Counter did not overflow
1 Overflow of CAN Error Logging Counter occurred

RW

0

21

BEU

Bit Error Uncorrected. Message RAM bit error detected, uncorrected. This bit is set when a double bit error is detected by the ECC aggregator attached to the Message RAM. An uncorrected Message RAM bit error sets CCCR.INIT to '1'. This is done to avoid transmission of corrupted data.
0 No bit error detected when reading from Message RAM
1 Bit error detected, uncorrected (e.g. parity logic)

RW

0

20

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

RO

0

19

DRX

Message Stored to Dedicated Rx Buffer. The flag is set whenever a received message has been stored into a dedicated Rx Buffer.
0 No Rx Buffer updated
1 At least one received message stored into an Rx Buffer

RW

0

18

TOO

Timeout Occurred
0 No timeout
1 Timeout reached

RW

0

17

MRAF

Message RAM Access Failure. The flag is set, when the Rx Handler:
- has not completed acceptance filtering or storage of an accepted message until the arbitration field of the following message has been received. In this case acceptance filtering or message storage is aborted and the Rx Handler starts processing of the following message.
- was not able to write a message to the Message RAM. In this case message storage is aborted.

In both cases the FIFO put index is not updated resp. the New Data flag for a dedicated Rx Buffer is not set, a partly stored message is overwritten when the next message is stored to this location.

The flag is also set when the Tx Handler was not able to read a message from the Message RAM in time. In this case message transmission is aborted. In case of a Tx Handler access failure the MCAN is switched into Restricted Operation Mode. To leave Restricted Operation Mode, the Host CPU has to reset CCCR.ASM.
0 No Message RAM access failure occurred
1 Message RAM access failure occurred

RW

0

16

TSW

Timestamp Wraparound
0 No timestamp counter wrap-around
1 Timestamp counter wrapped around

RW

0

15

TEFL

Tx Event FIFO Element Lost
0 No Tx Event FIFO element lost
1 Tx Event FIFO element lost, also set after write attempt to Tx Event FIFO of size zero

RW

0

14

TEFF

Tx Event FIFO Full
0 Tx Event FIFO not full
1 Tx Event FIFO full

RW

0

13

TEFW

Tx Event FIFO Watermark Reached
0 Tx Event FIFO fill level below watermark
1 Tx Event FIFO fill level reached watermark

RW

0

12

TEFN

Tx Event FIFO New Entry
0 Tx Event FIFO unchanged
1 Tx Handler wrote Tx Event FIFO element

RW

0

11

TFE

Tx FIFO Empty
0 Tx FIFO non-empty
1 Tx FIFO empty

RW

0

10

TCF

Transmission Cancellation Finished
0 No transmission cancellation finished
1 Transmission cancellation finished

RW

0

9

TC

Transmission Completed
0 No transmission completed
1 Transmission completed

RW

0

8

HPM

High Priority Message
0 No high priority message received
1 High priority message received

RW

0

7

RF1L

Rx FIFO 1 Message Lost
0 No Rx FIFO 1 message lost
1 Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size zero

RW

0

6

RF1F

Rx FIFO 1 Full
0 Rx FIFO 1 not full
1 Rx FIFO 1 full

RW

0

5

RF1W

Rx FIFO 1 Watermark Reached
0 Rx FIFO 1 fill level below watermark
1 Rx FIFO 1 fill level reached watermark

RW

0

4

RF1N

Rx FIFO 1 New Message
0 No new message written to Rx FIFO 1
1 New message written to Rx FIFO 1

RW

0

3

RF0L

Rx FIFO 0 Message Lost
0 No Rx FIFO 0 message lost
1 Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size zero

RW

0

2

RF0F

Rx FIFO 0 Full
0 Rx FIFO 0 not full
1 Rx FIFO 0 full

RW

0

1

RF0W

Rx FIFO 0 Watermark Reached
0 Rx FIFO 0 fill level below watermark
1 Rx FIFO 0 fill level reached watermark

RW

0

0

RF0N

Rx FIFO 0 New Message
0 No new message written to Rx FIFO 0
1 New message written to Rx FIFO 0

RW

0

31:30

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

RO

0x0

29

ARAE

Access to Reserved Address Enable

RW

0

28

PEDE

Protocol Error in Data Phase Enable

RW

0

27

PEAE

Protocol Error in Arbitration Phase Enable

RW

0

26

WDIE

Watchdog Interrupt Enable

RW

0

25

BOE

Bus_Off Status Enable

RW

0

24

EWE

Warning Status Enable

RW

0

23

EPE

Error Passive Enable

RW

0

22

ELOE

Error Logging Overflow Enable

RW

0

21

BEUE

Bit Error Uncorrected Enable

RW

0

19

DRXE

Message Stored to Dedicated Rx Buffer Enable

RW

0

18

TOOE

Timeout Occurred Enable

RW

0

17

MRAFE

Message RAM Access Failure Enable

RW

0

16

TSWE

Timestamp Wraparound Enable

RW

0

15

TEFLE

Tx Event FIFO Element Lost Enable

RW

0

14

TEFFE

Tx Event FIFO Full Enable

RW

0

13

TEFWE

Tx Event FIFO Watermark Reached Enable

RW

0

12

TEFNE

Tx Event FIFO New Entry Enable

RW

0

11

TFEE

Tx FIFO Empty Enable

RW

0

10

TCFE

Transmission Cancellation Finished Enable

RW

0

9

TCE

Transmission Completed Enable

RW

0

8

HPME

High Priority Message Enable

RW

0

7

RF1LE

Rx FIFO 1 Message Lost Enable

RW

0

6

RF1FE

Rx FIFO 1 Full Enable

RW

0

5

RF1WE

Rx FIFO 1 Watermark Reached Enable

RW

0

4

RF1NE

Rx FIFO 1 New Message Enable

RW

0

3

RF0LE

Rx FIFO 0 Message Lost Enable

RW

0

2

RF0FE

Rx FIFO 0 Full Enable

RW

0

1

RF0WE

Rx FIFO 0 Watermark Reached Enable

RW

0

0

RF0NE

Rx FIFO 0 New Message Enable

RW

0

31:30

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

RO

0x0

29

ARAL

Access to Reserved Address Line
0 Interrupt source is assigned to Interrupt Line 0
1 Interrupt source is assigned to Interrupt Line 1

RW

0

28

PEDL

Protocol Error in Data Phase Line
0 Interrupt source is assigned to Interrupt Line 0
1 Interrupt source is assigned to Interrupt Line 1

RW

0

27

PEAL

Protocol Error in Arbitration Phase Line
0 Interrupt source is assigned to Interrupt Line 0
1 Interrupt source is assigned to Interrupt Line 1

RW

0

26

WDIL

Watchdog Interrupt Line
0 Interrupt source is assigned to Interrupt Line 0
1 Interrupt source is assigned to Interrupt Line 1

RW

0

25

BOL

Bus_Off Status Line
0 Interrupt source is assigned to Interrupt Line 0
1 Interrupt source is assigned to Interrupt Line 1

RW

0

24

EWL

Warning Status Line
0 Interrupt source is assigned to Interrupt Line 0
1 Interrupt source is assigned to Interrupt Line 1

RW

0

23

EPL

Error Passive Line
0 Interrupt source is assigned to Interrupt Line 0
1 Interrupt source is assigned to Interrupt Line 1

RW

0

22

ELOL

Error Logging Overflow Line
0 Interrupt source is assigned to Interrupt Line 0
1 Interrupt source is assigned to Interrupt Line 1

RW

0

21

BEUL

Bit Error Uncorrected Line
0 Interrupt source is assigned to Interrupt Line 0
1 Interrupt source is assigned to Interrupt Line 1

RW

0

20

BECL

Bit Error Corrected Line

A separate interrupt line reserved for corrected bit errors is provided via the MCAN_ERROR_REGS. It advised for the user to use these registers and leave the IE.BECE bit cleared to '0' (disabled), thereby relegating this bit to not applicable.

RW

0

19

DRXL

Message Stored to Dedicated Rx Buffer Line
0 Interrupt source is assigned to Interrupt Line 0
1 Interrupt source is assigned to Interrupt Line 1

RW

0

18

TOOL

Timeout Occurred Line
0 Interrupt source is assigned to Interrupt Line 0
1 Interrupt source is assigned to Interrupt Line 1

RW

0

17

MRAFL

Message RAM Access Failure Line
0 Interrupt source is assigned to Interrupt Line 0
1 Interrupt source is assigned to Interrupt Line 1

RW

0

16

TSWL

Timestamp Wraparound Line
0 Interrupt source is assigned to Interrupt Line 0
1 Interrupt source is assigned to Interrupt Line 1

RW

0

15

TEFLL

Tx Event FIFO Element Lost Line
0 Interrupt source is assigned to Interrupt Line 0
1 Interrupt source is assigned to Interrupt Line 1

RW

0

14

TEFFL

Tx Event FIFO Full Line
0 Interrupt source is assigned to Interrupt Line 0
1 Interrupt source is assigned to Interrupt Line 1

RW

0

13

TEFWL

Tx Event FIFO Watermark Reached Line
0 Interrupt source is assigned to Interrupt Line 0
1 Interrupt source is assigned to Interrupt Line 1

RW

0

12

TEFNL

Tx Event FIFO New Entry Line
0 Interrupt source is assigned to Interrupt Line 0
1 Interrupt source is assigned to Interrupt Line 1

RW

0

11

TFEL

Tx FIFO Empty Line
0 Interrupt source is assigned to Interrupt Line 0
1 Interrupt source is assigned to Interrupt Line 1

RW

0

10

TCFL

Transmission Cancellation Finished Line
0 Interrupt source is assigned to Interrupt Line 0
1 Interrupt source is assigned to Interrupt Line 1

RW

0

9

TCL

Transmission Completed Line
0 Interrupt source is assigned to Interrupt Line 0
1 Interrupt source is assigned to Interrupt Line 1

RW

0

8

HPML

High Priority Message Line
0 Interrupt source is assigned to Interrupt Line 0
1 Interrupt source is assigned to Interrupt Line 1

RW

0

7

RF1LL

Rx FIFO 1 Message Lost Line
0 Interrupt source is assigned to Interrupt Line 0
1 Interrupt source is assigned to Interrupt Line 1

RW

0

6

RF1FL

Rx FIFO 1 Full Line
0 Interrupt source is assigned to Interrupt Line 0
1 Interrupt source is assigned to Interrupt Line 1

RW

0

5

RF1WL

Rx FIFO 1 Watermark Reached Line
0 Interrupt source is assigned to Interrupt Line 0
1 Interrupt source is assigned to Interrupt Line 1

RW

0

4

RF1NL

Rx FIFO 1 New Message Line
0 Interrupt source is assigned to Interrupt Line 0
1 Interrupt source is assigned to Interrupt Line 1

RW

0

3

RF0LL

Rx FIFO 0 Message Lost Line
0 Interrupt source is assigned to Interrupt Line 0
1 Interrupt source is assigned to Interrupt Line 1

RW

0

2

RF0FL

Rx FIFO 0 Full Line
0 Interrupt source is assigned to Interrupt Line 0
1 Interrupt source is assigned to Interrupt Line 1

RW

0

1

RF0WL

Rx FIFO 0 Watermark Reached Line
0 Interrupt source is assigned to Interrupt Line 0
1 Interrupt source is assigned to Interrupt Line 1

RW

0

0

RF0NL

Rx FIFO 0 New Message Line
0 Interrupt source is assigned to Interrupt Line 0
1 Interrupt source is assigned to Interrupt Line 1

RW

0

31:2

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

RO

0x0000 0000

1

EINT1

Enable Interrupt Line 1
0 Interrupt Line 1 is disabled
1 Interrupt Line 1 is enabled

RW

0

0

EINT0

Enable Interrupt Line 0
0 Interrupt Line 0 is disabled
1 Interrupt Line 0 is enabled

RW

0

31:6

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

RO

0x000 0000

5:4

ANFS

Accept Non-matching Frames Standard. Defines how received messages with 11-bit IDs that do not match any element of the filter list are treated.
00 Accept in Rx FIFO 0
01 Accept in Rx FIFO 1
10 Reject
11 Reject

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.

RW

0x0

3:2

ANFE

Accept Non-matching Frames Extended. Defines how received messages with 29-bit IDs that do not match any element of the filter list are treated.
00 Accept in Rx FIFO 0
01 Accept in Rx FIFO 1
10 Reject
11 Reject

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.

RW

0x0

1

RRFS

Reject Remote Frames Standard
0 Filter remote frames with 11-bit standard IDs
1 Reject all remote frames with 11-bit standard IDs

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.

RW

0

0

RRFE

Reject Remote Frames Extended
0 Filter remote frames with 29-bit extended IDs
1 Reject all remote frames with 29-bit extended IDs

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.

RW

0

31:24

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

RO

0x00

23:16

LSS

List Size Standard
0 No standard Message ID filter
1-128 Number of standard Message ID filter elements
>128 Values greater than 128 are interpreted as 128

RW

0x00

15:2

FLSSA

Filter List Standard Start Address. Start address of standard Message ID filter list (32-bit word address).

RW

0x0000

1:0

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

RO

0x0

31:23

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

RO

0x000

22:16

LSE

List Size Extended
0 No extended Message ID filter
1-64 Number of extended Message ID filter elements
>64 Values greater than 64 are interpreted as 64

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.

RW

0x00

15:2

FLESA

Filter List Extended Start Address. Start address of extended Message ID filter list (32-bit word address).

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.

RW

0x0000

1:0

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

RO

0x0

31:29

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

RO

0x0

28:0

EIDM

Extended ID Mask. For acceptance filtering of extended frames the Extended ID AND Mask is ANDed with the Message ID of a received frame. Intended for masking of 29-bit IDs in SAE J1939. With the reset value of all bits set to one the mask is not active.

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.

RW

0x1FFF FFFF

31:16

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

RO

0x0000

15

FLST

Filter List. Indicates the filter list of the matching filter element.
0 Standard Filter List
1 Extended Filter List

RO

0

14:8

FIDX

Filter Index. Index of matching filter element. Range is 0 to SIDFC.LSS - 1 resp. XIDFC.LSE - 1.

RO

0x00

7:6

MSI

Message Storage Indicator
00 No FIFO selected
01 FIFO message lost
10 Message stored in FIFO 0
11 Message stored in FIFO 1

RO

0x0

5:0

BIDX

Buffer Index. Index of Rx FIFO element to which the message was stored. Only valid when MSI(1) = '1'.

RO

0x00

31

ND31

New Data RX Buffer 31
0 Rx Buffer not updated
1 Rx Buffer updated from new message

RW

0

30

ND30

New Data RX Buffer 30
0 Rx Buffer not updated
1 Rx Buffer updated from new message

RW

0

29

ND29

New Data RX Buffer 29
0 Rx Buffer not updated
1 Rx Buffer updated from new message

RW

0

28

ND28

New Data RX Buffer 28
0 Rx Buffer not updated
1 Rx Buffer updated from new message

RW

0

27

ND27

New Data RX Buffer 27
0 Rx Buffer not updated
1 Rx Buffer updated from new message

RW

0

26

ND26

New Data RX Buffer 26
0 Rx Buffer not updated
1 Rx Buffer updated from new message

RW

0

25

ND25

New Data RX Buffer 25
0 Rx Buffer not updated
1 Rx Buffer updated from new message

RW

0

24

ND24

New Data RX Buffer 24
0 Rx Buffer not updated
1 Rx Buffer updated from new message

RW

0

23

ND23

New Data RX Buffer 23
0 Rx Buffer not updated
1 Rx Buffer updated from new message

RW

0

22

ND22

New Data RX Buffer 22
0 Rx Buffer not updated
1 Rx Buffer updated from new message

RW

0

21

ND21

New Data RX Buffer 21
0 Rx Buffer not updated
1 Rx Buffer updated from new message

RW

0

20

ND20

New Data RX Buffer 20
0 Rx Buffer not updated
1 Rx Buffer updated from new message

RW

0

19

ND19

New Data RX Buffer 19
0 Rx Buffer not updated
1 Rx Buffer updated from new message

RW

0

18

ND18

New Data RX Buffer 18
0 Rx Buffer not updated
1 Rx Buffer updated from new message

RW

0

17

ND17

New Data RX Buffer 17
0 Rx Buffer not updated
1 Rx Buffer updated from new message

RW

0

16

ND16

New Data RX Buffer 16
0 Rx Buffer not updated
1 Rx Buffer updated from new message

RW

0

15

ND15

New Data RX Buffer 15
0 Rx Buffer not updated
1 Rx Buffer updated from new message

RW

0

14

ND14

New Data RX Buffer 14
0 Rx Buffer not updated
1 Rx Buffer updated from new message

RW

0

13

ND13

New Data RX Buffer 13
0 Rx Buffer not updated
1 Rx Buffer updated from new message

RW

0

12

ND12

New Data RX Buffer 12
0 Rx Buffer not updated
1 Rx Buffer updated from new message

RW

0

11

ND11

New Data RX Buffer 11
0 Rx Buffer not updated
1 Rx Buffer updated from new message

RW

0

10

ND10

New Data RX Buffer 10
0 Rx Buffer not updated
1 Rx Buffer updated from new message

RW

0

9

ND9

New Data RX Buffer 9
0 Rx Buffer not updated
1 Rx Buffer updated from new message

RW

0

8

ND8

New Data RX Buffer 8
0 Rx Buffer not updated
1 Rx Buffer updated from new message

RW

0

7

ND7

New Data RX Buffer 7
0 Rx Buffer not updated
1 Rx Buffer updated from new message

RW

0

6

ND6

New Data RX Buffer 6
0 Rx Buffer not updated
1 Rx Buffer updated from new message

RW

0

5

ND5

New Data RX Buffer 5
0 Rx Buffer not updated
1 Rx Buffer updated from new message

RW

0

4

ND4

New Data RX Buffer 4
0 Rx Buffer not updated
1 Rx Buffer updated from new message

RW

0

3

ND3

New Data RX Buffer 3
0 Rx Buffer not updated
1 Rx Buffer updated from new message

RW

0

2

ND2

New Data RX Buffer 2
0 Rx Buffer not updated
1 Rx Buffer updated from new message

RW

0

1

ND1

New Data RX Buffer 1
0 Rx Buffer not updated
1 Rx Buffer updated from new message

RW

0

0

ND0

New Data RX Buffer 0
0 Rx Buffer not updated
1 Rx Buffer updated from new message

RW

0

31

ND63

New Data RX Buffer 63
0 Rx Buffer not updated
1 Rx Buffer updated from new message

RW

0

30

ND62

New Data RX Buffer 62
0 Rx Buffer not updated
1 Rx Buffer updated from new message

RW

0

29

ND61

New Data RX Buffer 61
0 Rx Buffer not updated
1 Rx Buffer updated from new message

RW

0

28

ND60

New Data RX Buffer 60
0 Rx Buffer not updated
1 Rx Buffer updated from new message

RW

0

27

ND59

New Data RX Buffer 59
0 Rx Buffer not updated
1 Rx Buffer updated from new message

RW

0

26

ND58

New Data RX Buffer 58
0 Rx Buffer not updated
1 Rx Buffer updated from new message

RW

0

25

ND57

New Data RX Buffer 57
0 Rx Buffer not updated
1 Rx Buffer updated from new message

RW

0

24

ND56

New Data RX Buffer 56
0 Rx Buffer not updated
1 Rx Buffer updated from new message

RW

0

23

ND55

New Data RX Buffer 55
0 Rx Buffer not updated
1 Rx Buffer updated from new message

RW

0

22

ND54

New Data RX Buffer 54
0 Rx Buffer not updated
1 Rx Buffer updated from new message

RW

0

21

ND53

New Data RX Buffer 53
0 Rx Buffer not updated
1 Rx Buffer updated from new message

RW

0

20

ND52

New Data RX Buffer 52
0 Rx Buffer not updated
1 Rx Buffer updated from new message

RW

0

19

ND51

New Data RX Buffer 51
0 Rx Buffer not updated
1 Rx Buffer updated from new message

RW

0

18

ND50

New Data RX Buffer 50
0 Rx Buffer not updated
1 Rx Buffer updated from new message

RW

0

17

ND49

New Data RX Buffer 49
0 Rx Buffer not updated
1 Rx Buffer updated from new message

RW

0

16

ND48

New Data RX Buffer 48
0 Rx Buffer not updated
1 Rx Buffer updated from new message

RW

0

15

ND47

New Data RX Buffer 47
0 Rx Buffer not updated
1 Rx Buffer updated from new message

RW

0

14

ND46

New Data RX Buffer 46
0 Rx Buffer not updated
1 Rx Buffer updated from new message

RW

0

13

ND45

New Data RX Buffer 45
0 Rx Buffer not updated
1 Rx Buffer updated from new message

RW

0

12

ND44

New Data RX Buffer 44
0 Rx Buffer not updated
1 Rx Buffer updated from new message

RW

0

11

ND43

New Data RX Buffer 43
0 Rx Buffer not updated
1 Rx Buffer updated from new message

RW

0

10

ND42

New Data RX Buffer 42
0 Rx Buffer not updated
1 Rx Buffer updated from new message

RW

0

9

ND41

New Data RX Buffer 41
0 Rx Buffer not updated
1 Rx Buffer updated from new message

RW

0

8

ND40

New Data RX Buffer 40
0 Rx Buffer not updated
1 Rx Buffer updated from new message

RW

0

7

ND39

New Data RX Buffer 39
0 Rx Buffer not updated
1 Rx Buffer updated from new message

RW

0

6

ND38

New Data RX Buffer 38
0 Rx Buffer not updated
1 Rx Buffer updated from new message

RW

0

5

ND37

New Data RX Buffer 37
0 Rx Buffer not updated
1 Rx Buffer updated from new message

RW

0

4

ND36

New Data RX Buffer 36
0 Rx Buffer not updated
1 Rx Buffer updated from new message

RW

0

3

ND35

New Data RX Buffer 35
0 Rx Buffer not updated
1 Rx Buffer updated from new message

RW

0

2

ND34

New Data RX Buffer 34
0 Rx Buffer not updated
1 Rx Buffer updated from new message

RW

0

1

ND33

New Data RX Buffer 33
0 Rx Buffer not updated
1 Rx Buffer updated from new message

RW

0

0

ND32

New Data RX Buffer 32
0 Rx Buffer not updated
1 Rx Buffer updated from new message

RW

0

31

F0OM

FIFO 0 Operation Mode. FIFO 0 can be operated in blocking or in overwrite mode.
0 FIFO 0 blocking mode
1 FIFO 0 overwrite mode

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.

RW

0

30:24

F0WM

Rx FIFO 0 Watermark
0 Watermark interrupt disabled
1-64 Level for Rx FIFO 0 watermark interrupt (IR.RF0W)
>64 Watermark interrupt disabled

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.

RW

0x00

23

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

RO

0

22:16

F0S

Rx FIFO 0 Size. The Rx FIFO 0 elements are indexed from 0 to F0S-1.
0 No Rx FIFO 0
1-64 Number of Rx FIFO 0 elements
>64 Values greater than 64 are interpreted as 64

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.

RW

0x00

15:2

F0SA

Rx FIFO 0 Start Address. Start address of Rx FIFO 0 in Message RAM (32-bit word address).

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.

RW

0x0000

1:0

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

RO

0x0

31:26

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

RO

0x00

25

RF0L

Rx FIFO 0 Message Lost. This bit is a copy of interrupt flag IR.RF0L. When IR.RF0L is reset, this bit is also reset.
0 No Rx FIFO 0 message lost
1 Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size zero

Note: Overwriting the oldest message when RXF0C.F0OM = '1' will not set this flag.

RO

0

24

F0F

Rx FIFO 0 Full
0 Rx FIFO 0 not full
1 Rx FIFO 0 full

RO

0

23:22

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

RO

0x0

21:16

F0PI

Rx FIFO 0 Put Index. Rx FIFO 0 write index pointer, range 0 to 63.

RO

0x00

15:14

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

RO

0x0

13:8

F0GI

Rx FIFO 0 Get Index. Rx FIFO 0 read index pointer, range 0 to 63.

RO

0x00

7

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

RO

0

6:0

F0FL

Rx FIFO 0 Fill Level. Number of elements stored in Rx FIFO 0, range 0 to 64.

RO

0x00

31:6

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

RO

0x000 0000

5:0

F0AI

Rx FIFO 0 Acknowledge Index. After the Host has read a message or a sequence of messages from Rx FIFO 0 it has to write the buffer index of the last element read from Rx FIFO 0 to F0AI. This will set the Rx FIFO 0 Get Index RXF0S.F0GI to F0AI + 1 and update the FIFO 0 Fill Level RXF0S.F0FL.

RW

0x00

31:16

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

RO

0x0000

15:2

RBSA

Rx Buffer Start Address. Configures the start address of the Rx Buffers section in the Message RAM (32-bit word address).

+I466

RW

0x0000

1:0

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

RO

0x0

31

F1OM

FIFO 1 Operation Mode. FIFO 1 can be operated in blocking or in overwrite mode.
0 FIFO 1 blocking mode
1 FIFO 1 overwrite mode

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.

RW

0

30:24

F1WM

Rx FIFO 1 Watermark
0 Watermark interrupt disabled
1-64 Level for Rx FIFO 1 watermark interrupt (IR.RF1W)
>64 Watermark interrupt disabled

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.

RW

0x00

23

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

RO

0

22:16

F1S

Rx FIFO 1 Size. The Rx FIFO 1 elements are indexed from 0 to F1S - 1.
0 No Rx FIFO 1
1-64 Number of Rx FIFO 1 elements
>64 Values greater than 64 are interpreted as 64

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.

RW

0x00

15:2

F1SA

Rx FIFO 1 Start Address Start address of Rx FIFO 1 in Message RAM (32-bit word address).

RW

0x0000

1:0

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

RO

0x0

31:30

DMS

Debug Message Status
00 Idle state, wait for reception of debug messages, DMA request is cleared
01 Debug message A received
10 Debug messages A, B received
11 Debug messages A, B, C received, DMA request is set

RO

0x0

29:26

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

RO

0x0

25

RF1L

Rx FIFO 1 Message Lost. This bit is a copy of interrupt flag IR.RF1L. When IR.RF1L is reset, this bit is also reset.
0 No Rx FIFO 1 message lost
1 Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size zero

Note: Overwriting the oldest message when RXF1C.F1OM = '1' will not set this flag.

RO

0

24

F1F

Rx FIFO 1 Full
0 Rx FIFO 1 not full
1 Rx FIFO 1 full

RO

0

23:22

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

RO

0x0

21:16

F1PI

Rx FIFO 1 Put Index. Rx FIFO 1 write index pointer, range 0 to 63.

RO

0x00

15:14

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

RO

0x0

13:8

F1GI

Rx FIFO 1 Get Index. Rx FIFO 1 read index pointer, range 0 to 63.

RO

0x00

7

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

RO

0

6:0

F1FL

Rx FIFO 1 Fill Level. Number of elements stored in Rx FIFO 1, range 0 to 64.

RO

0x00

31:6

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

RO

0x000 0000

5:0

F1AI

Rx FIFO 1 Acknowledge Index. After the Host has read a message or a sequence of messages from Rx FIFO 1 it has to write the buffer index of the last element read from Rx FIFO 1 to F1AI. This will set the Rx FIFO 1 Get Index RXF1S.F1GI to F1AI + 1 and update the FIFO 1 Fill Level RXF1S.F1FL.

RW

0x00

31:11

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

RO

0x00 0000

10:8

RBDS

Rx Buffer Data Field Size
000 8 byte data field
001 12 byte data field
010 16 byte data field
011 20 byte data field
100 24 byte data field
101 32 byte data field
110 48 byte data field
111 64 byte data field

Note: In case the data field size of an accepted CAN frame exceeds the data field size configured for the matching Rx Buffer or Rx FIFO, only the number of bytes as configured by RXESC are stored to the Rx Buffer resp. Rx FIFO element. The rest of the frame's data field is ignored.

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.

RW

0x0

7

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

RO

0

6:4

F1DS

Rx FIFO 1 Data Field Size
000 8 byte data field
001 12 byte data field
010 16 byte data field
011 20 byte data field
100 24 byte data field
101 32 byte data field
110 48 byte data field
111 64 byte data field

Note: In case the data field size of an accepted CAN frame exceeds the data field size configured for the matching Rx Buffer or Rx FIFO, only the number of bytes as configured by RXESC are stored to the Rx Buffer resp. Rx FIFO element. The rest of the frame's data field is ignored.

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.

RW

0x0

3

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

RO

0

2:0

F0DS

Rx FIFO 0 Data Field Size
000 8 byte data field
001 12 byte data field
010 16 byte data field
011 20 byte data field
100 24 byte data field
101 32 byte data field
110 48 byte data field
111 64 byte data field

Note: In case the data field size of an accepted CAN frame exceeds the data field size configured for the matching Rx Buffer or Rx FIFO, only the number of bytes as configured by RXESC are stored to the Rx Buffer resp. Rx FIFO element. The rest of the frame's data field is ignored.

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.

RW

0x0

31

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

RO

0

30

TFQM

Tx FIFO/Queue Mode
0 Tx FIFO operation
1 Tx Queue operation

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.

RW

0

29:24

TFQS

Transmit FIFO/Queue Size
0 No Tx FIFO/Queue
1-32 Number of Tx Buffers used for Tx FIFO/Queue
>32 Values greater than 32 are interpreted as 32

Note: Be aware that the sum of TFQS and NDTB may be not greater than 32. There is no check
for erroneous configurations. The Tx Buffers section in the Message RAM starts with the
dedicated Tx Buffers.

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.

RW

0x00

23:22

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

RO

0x0

21:16

NDTB

Number of Dedicated Transmit Buffers
0 No Dedicated Tx Buffers
1-32 Number of Dedicated Tx Buffers
>32 Values greater than 32 are interpreted as 32

Note: Be aware that the sum of TFQS and NDTB may be not greater than 32. There is no check
for erroneous configurations. The Tx Buffers section in the Message RAM starts with the
dedicated Tx Buffers.

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.

RW

0x00

15:2

TBSA

Tx Buffers Start Address. Start address of Tx Buffers section in Message RAM (32-bit word address).

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.

RW

0x0000

1:0

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

RO

0x0

31:22

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

RO

0x000

21

TFQF

Tx FIFO/Queue Full
0 Tx FIFO/Queue not full
1 Tx FIFO/Queue full

RO

0

20:16

TFQP

Tx FIFO/Queue Put Index. Tx FIFO/Queue write index pointer, range 0 to 31.

Note: In case of mixed configurations where dedicated Tx Buffers are combined with a Tx FIFO or a Tx Queue, the Put and Get Indices indicate the number of the Tx Buffer starting with the first dedicated Tx Buffers. Example: For a configuration of 12 dedicated Tx Buffers and a Tx FIFO of 20 Buffers a Put Index of 15 points to the fourth buffer of the Tx FIFO.

RO

0x00

15:13

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

RO

0x0

12:8

TFGI

Tx FIFO Get Index. Tx FIFO read index pointer, range 0 to 31. Read as zero when Tx Queue operation is configured (TXBC.TFQM = '1').

Note: In case of mixed configurations where dedicated Tx Buffers are combined with a Tx FIFO or a Tx Queue, the Put and Get Indices indicate the number of the Tx Buffer starting with the first dedicated Tx Buffers. Example: For a configuration of 12 dedicated Tx Buffers and a Tx FIFO of 20 Buffers a Put Index of 15 points to the fourth buffer of the Tx FIFO.

RO

0x00

7:6

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

RO

0x0

5:0

TFFL

Tx FIFO Free Level. Number of consecutive free Tx FIFO elements starting from TFGI, range 0 to 32. Read as zero when Tx Queue operation is configured (TXBC.TFQM = '1').

RO

0x00

31:3

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

RO

0x0000 0000

2:0

TBDS

Tx Buffer Data Field Size
000 8 byte data field
001 12 byte data field
010 16 byte data field
011 20 byte data field
100 24 byte data field
101 32 byte data field
110 48 byte data field
111 64 byte data field

Note: In case the data length code DLC of a Tx Buffer element is configured to a value higher than the Tx Buffer data field size TXESC.TBDS, the bytes not defined by the Tx Buffer are transmitted as "0xCC" (padding bytes).

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.

RW

0x0

31

TRP31

Transmission Request Pending 31. See description for bit 0.

RO

0

30

TRP30

Transmission Request Pending 30. See description for bit 0.

RO

0

29

TRP29

Transmission Request Pending 29. See description for bit 0.

RO

0

28

TRP28

Transmission Request Pending 28. See description for bit 0.

RO

0

27

TRP27

Transmission Request Pending 27. See description for bit 0.

RO

0

26

TRP26

Transmission Request Pending 26. See description for bit 0.

RO

0

25

TRP25

Transmission Request Pending 25. See description for bit 0.

RO

0

24

TRP24

Transmission Request Pending 24. See description for bit 0.

RO

0

23

TRP23

Transmission Request Pending 23. See description for bit 0.

RO

0

22

TRP22

Transmission Request Pending 22. See description for bit 0.

RO

0

21

TRP21

Transmission Request Pending 21. See description for bit 0.

RO

0

20

TRP20

Transmission Request Pending 20. See description for bit 0.

RO

0

19

TRP19

Transmission Request Pending 19. See description for bit 0.

RO

0

18

TRP18

Transmission Request Pending 18. See description for bit 0.

RO

0

17

TRP17

Transmission Request Pending 17. See description for bit 0.

RO

0

16

TRP16

Transmission Request Pending 16. See description for bit 0.

RO

0

15

TRP15

Transmission Request Pending 15. See description for bit 0.

RO

0

14

TRP14

Transmission Request Pending 14. See description for bit 0.

RO

0

13

TRP13

Transmission Request Pending 13. See description for bit 0.

RO

0

12

TRP12

Transmission Request Pending 12. See description for bit 0.

RO

0

11

TRP11

Transmission Request Pending 11. See description for bit 0.

RO

0

10

TRP10

Transmission Request Pending 10. See description for bit 0.

RO

0

9

TRP9

Transmission Request Pending 9. See description for bit 0.

RO

0

8

TRP8

Transmission Request Pending 8. See description for bit 0.

RO

0

7

TRP7

Transmission Request Pending 7. See description for bit 0.

RO

0

6

TRP6

Transmission Request Pending 6. See description for bit 0.

RO

0

5

TRP5

Transmission Request Pending 5. See description for bit 0.

RO

0

4

TRP4

Transmission Request Pending 4. See description for bit 0.

RO

0

3

TRP3

Transmission Request Pending 3. See description for bit 0.

RO

0

2

TRP2

Transmission Request Pending 2. See description for bit 0.

RO

0

1

TRP1

Transmission Request Pending 1. See description for bit 0.

RO

0

0

TRP0

Transmission Request Pending 0.

Each Tx Buffer has its own Transmission Request Pending bit. The bits are set via register TXBAR. The bits are reset after a requested transmission has completed or has been cancelled via register TXBCR.

TXBRP bits are set only for those Tx Buffers configured via TXBC. After a TXBRP bit has been set, a Tx scan is started to check for the pending Tx request with the highest priority (Tx Buffer with lowest Message ID).

A cancellation request resets the corresponding transmission request pending bit of register TXBRP. In case a transmission has already been started when a cancellation is requested, this is done at the end of the transmission, regardless whether the transmission was successful or not. The cancellation request bits are reset directly after the corresponding TXBRP bit has been reset.

After a cancellation has been requested, a finished cancellation is signalled via TXBCF
- after successful transmission together with the corresponding TXBTO bit
- when the transmission has not yet been started at the point of cancellation
- when the transmission has been aborted due to lost arbitration
- when an error occurred during frame transmission

In DAR mode all transmissions are automatically cancelled if they are not successful. The corresponding TXBCF bit is set for all unsuccessful transmissions.
0 No transmission request pending
1 Transmission request pending

Note: TXBRP bits which are set while a Tx scan is in progress are not considered during this particular Tx scan. In case a cancellation is requested for such a Tx Buffer, this Add Request is cancelled immediately, the corresponding TXBRP bit is reset.

RO

0

31

AR31

Add Request 31. See description for bit 0.

RW

0

30

AR30

Add Request 30. See description for bit 0.

RW

0

29

AR29

Add Request 29. See description for bit 0.

RW

0

28

AR28

Add Request 28. See description for bit 0.

RW

0

27

AR27

Add Request 27. See description for bit 0.

RW

0

26

AR26

Add Request 26. See description for bit 0.

RW

0

25

AR25

Add Request 25. See description for bit 0.

RW

0

24

AR24

Add Request 24. See description for bit 0.

RW

0

23

AR23

Add Request 23. See description for bit 0.

RW

0

22

AR22

Add Request 22. See description for bit 0.

RW

0

21

AR21

Add Request 21. See description for bit 0.

RW

0

20

AR20

Add Request 20. See description for bit 0.

RW

0

19

AR19

Add Request 19. See description for bit 0.

RW

0

18

AR18

Add Request 18. See description for bit 0.

RW

0

17

AR17

Add Request 17. See description for bit 0.

RW

0

16

AR16

Add Request 16. See description for bit 0.

RW

0

15

AR15

Add Request 15. See description for bit 0.

RW

0

14

AR14

Add Request 14. See description for bit 0.

RW

0

13

AR13

Add Request 13. See description for bit 0.

RW

0

12

AR12

Add Request 12. See description for bit 0.

RW

0

11

AR11

Add Request 11. See description for bit 0.

RW

0

10

AR10

Add Request 10. See description for bit 0.

RW

0

9

AR9

Add Request 9. See description for bit 0.

RW

0

8

AR8

Add Request 8. See description for bit 0.

RW

0

7

AR7

Add Request 7. See description for bit 0.

RW

0

6

AR6

Add Request 6. See description for bit 0.

RW

0

5

AR5

Add Request 5. See description for bit 0.

RW

0

4

AR4

Add Request 4. See description for bit 0.

RW

0

3

AR3

Add Request 3. See description for bit 0.

RW

0

2

AR2

Add Request 2. See description for bit 0.

RW

0

1

AR1

Add Request 1. See description for bit 0.

RW

0

0

AR0

Add Request 0.

Each Tx Buffer has its own Add Request bit. Writing a '1' will set the corresponding Add Request bit; writing a '0' has no impact. This enables the Host to set transmission requests for multiple Tx Buffers with one write to TXBAR. TXBAR bits are set only for those Tx Buffers configured via TXBC. When no Tx scan is running, the bits are reset immediately, else the bits remain set until the Tx scan process has completed.
0 No transmission request added
1 Transmission requested added

Note: If an add request is applied for a Tx Buffer with pending transmission request (corresponding TXBRP bit already set), this add request is ignored.

Qualified Write is possible only with CCCR.CCE='0'

RW

0

31

CR31

Cancellation Request 31. See description for bit 0.

RW

0

30

CR30

Cancellation Request 30. See description for bit 0.

RW

0

29

CR29

Cancellation Request 29. See description for bit 0.

RW

0

28

CR28

Cancellation Request 28. See description for bit 0.

RW

0

27

CR27

Cancellation Request 27. See description for bit 0.

RW

0

26

CR26

Cancellation Request 26. See description for bit 0.

RW

0

25

CR25

Cancellation Request 25. See description for bit 0.

RW

0

24

CR24

Cancellation Request 24. See description for bit 0.

RW

0

23

CR23

Cancellation Request 23. See description for bit 0.

RW

0

22

CR22

Cancellation Request 22. See description for bit 0.

RW

0

21

CR21

Cancellation Request 21. See description for bit 0.

RW

0

20

CR20

Cancellation Request 20. See description for bit 0.

RW

0

19

CR19

Cancellation Request 19. See description for bit 0.

RW

0

18

CR18

Cancellation Request 18. See description for bit 0.

RW

0

17

CR17

Cancellation Request 17. See description for bit 0.

RW

0

16

CR16

Cancellation Request 16. See description for bit 0.

RW

0

15

CR15

Cancellation Request 15. See description for bit 0.

RW

0

14

CR14

Cancellation Request 14. See description for bit 0.

RW

0

13

CR13

Cancellation Request 13. See description for bit 0.

RW

0

12

CR12

Cancellation Request 12. See description for bit 0.

RW

0

11

CR11

Cancellation Request 11. See description for bit 0.

RW

0

10

CR10

Cancellation Request 10. See description for bit 0.

RW

0

9

CR9

Cancellation Request 9. See description for bit 0.

RW

0

8

CR8

Cancellation Request 8. See description for bit 0.

RW

0

7

CR7

Cancellation Request 7. See description for bit 0.

RW

0

6

CR6

Cancellation Request 6. See description for bit 0.

RW

0

5

CR5

Cancellation Request 5. See description for bit 0.

RW

0

4

CR4

Cancellation Request 4. See description for bit 0.

RW

0

3

CR3

Cancellation Request 3. See description for bit 0.

RW

0

2

CR2

Cancellation Request 2. See description for bit 0.

RW

0

1

CR1

Cancellation Request 1. See description for bit 0.

RW

0

0

CR0

Cancellation Request 0.

Each Tx Buffer has its own Cancellation Request bit. Writing a '1' will set the corresponding Cancellation Request bit; writing a '0' has no impact. This enables the Host to set cancellation requests for multiple Tx Buffers with one write to TXBCR. TXBCR bits are set only for those Tx Buffers configured via TXBC. The bits remain set until the corresponding bit of TXBRP is reset.
0 No cancellation pending
1 Cancellation pending

Qualified Write is possible only with CCCR.CCE='0'

RW

0

31

TO31

Transmission Occurred 31. See description for bit 0.

RO

0

30

TO30

Transmission Occurred 30. See description for bit 0.

RO

0

29

TO29

Transmission Occurred 29. See description for bit 0.

RO

0

28

TO28

Transmission Occurred 28. See description for bit 0.

RO

0

27

TO27

Transmission Occurred 27. See description for bit 0.

RO

0

26

TO26

Transmission Occurred 26. See description for bit 0.

RO

0

25

TO25

Transmission Occurred 25. See description for bit 0.

RO

0

24

TO24

Transmission Occurred 24. See description for bit 0.

RO

0

23

TO23

Transmission Occurred 23. See description for bit 0.

RO

0

22

TO22

Transmission Occurred 22. See description for bit 0.

RO

0

21

TO21

Transmission Occurred 21. See description for bit 0.

RO

0

20

TO20

Transmission Occurred 20. See description for bit 0.

RO

0

19

TO19