DCACHE

DCACHE

This section provides information on the DCACHE Module Instance within this product. Each of the registers within the Module Instance is described separately below.

DCACHE Registers Mapping Summary

:DCACHE Common Register Mapping Summary

Register Name	Type	Register Width (Bits)	Register Reset	Address Offset
MOD_VER	RO	32	0x6880 0800	0x0000 0000
CTRL	RW	32	0b01xx xxxx xxxx xxxx xxxx xxxx xxxx xxxx	0x0000 0004
STS	RO	32	0b0xxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx	0x0000 0008
CAL	RW	32	0x0000 0XXX	0x0000 0010
CAH	RW	32	0x0000 0XXX	0x0000 0018
READ_COUNTER	RW	32	0x0000 0000	0x0000 0040
WRITE_COUNTER	RW	32	0x0000 0000	0x0000 0044
ADDRESS_LATCH	RW	32	0x0000 0000	0x0000 0048
CACHE_FSM_STATE	RO	32	0x0000 0000	0x0000 004C
IRQSTATUS_RAW	RW	32	0bxxxx xxxx xxxx xxxx xxxx xxxx xxxx xxx0	0x0000 0080
IRQSTATUS_MSK	RW	32	0bxxxx xxxx xxxx xxxx xxxx xxxx xxxx xxx0	0x0000 0084
IRQENABLE_SET	RW	32	0bxxxx xxxx xxxx xxxx xxxx xxxx xxxx xxx0	0x0000 0088
IRQENABLE_CLR	RW	32	0bxxxx xxxx xxxx xxxx xxxx xxxx xxxx xxx0	0x0000 008C
CTRL1	RW	32	0b00xx xxxx xxxx xxxx xxxx xxxx xxxx xxxx	0x0000 00C0
STATUS1	RO	32	0b000x xxxx xxxx xxxx xxxx xxxx xxxx xxxx	0x0000 00C4

DCACHE Instances Register Mapping Summary

DCACHE Register Descriptions

:DCACHE Common Register Descriptions

:DCACHE:MOD_VER

Address offset	0x0000 0000
Description	The Module and Version Register identifies the module identifier and revision of the L1 module.
Type	RO

Bits	Field Name	Description			Type	Reset
31:30	SCHEME	Module Scheme			RO	0x1
29:28	BU	Module Business Unit			RO	0x2
27:16	MODULE_ID	L1 module ID.			RO	0x880
15:11	RTL_VERSION	RTL Version.			RO	0x01
10:8	MAJOR_REVISION	Major Revision.			RO	0x0
7:6	CUSTOM_REVISION	Custom Revision.			RO	0x0
5:0	MINOR_REVISION	Minor Revision.			RO	0x00

:DCACHE:CTRL

Address offset	0x0000 0004
Description	The control register defines the size of the remote cache data storage memory to use and whether the L1 is enabled.
Type	RW

Bits	Field Name	Description			Type	Reset
31	CENABLE	The ~icenable field determines whether the L1 configuration is enabled or not.#br# 0: Disabled#br# 1: Enabled #br# This field is write protected when the t_cfg_lock_ipcfg input is high.			RW	0
30	RENABLE	The ~irenable field determines if half the cache space is RAM or cache. #br# 0: No RAM 64K of cache#br# 1: RAM 32K of cache, 32K of RAM. This field is write protected when ~icenable is set or the t_cfg_lock_ipcfg input is high.			RW	1
29:0	RESERVED				RO	0bxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx

:DCACHE:STS

Address offset	0x0000 0008
Description	The Status register displays the state of the L1 module
Type	RO

Bits	Field Name	Description			Type	Reset
31	OK_TO_GO	The ~iok_to_go status bit indicates the Tag/LRU Ram has been initialized and the cache is in an operable state.			RO	0
30:0	RESERVED				RO	0bxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx

:DCACHE:CAL

Address offset	0x0000 0010
Description	The L1 Cache Address Low Register defines start of the L1 cacheable space. The L1 cache can cache up to a range of 8MB of of the target Flash as defined by CAL>=CachedRange<=CAH. This register is write protected when ~icenable is set or the t_cfg_lock_ipcfg input is high.
Type	RW

Bits	Field Name	Description			Type	Reset
31:12	ADDR_LO	The ~iaddr_lo defines the L1 low address[31:12] for the L1 to cache. The remaining bits 10:0 are assumed to be zero.			RW	0x0 0000
11:0	RESERVED				RO	0xXXX

:DCACHE:CAH

Address offset	0x0000 0018
Description	The L1 Cache Address High Register defines end of the L1 cacheable space. The L1 cache can cache up to a range of 8MB of of the target Flash as defined by CAL>=CachedRange<=CAH. This register is write protected when ~icenable is set or the t_cfg_lock_ipcfg input is high.
Type	RW

Bits	Field Name	Description			Type	Reset
31:12	ADDR_HI	The ~iaddr_hi defines the L1 high address[31:12] for the L1 to cache. The remaining bits 10:0 are assumed to be ones.			RW	0x0 0000
11:0	RESERVED				RO	0xXXX

:DCACHE:READ_COUNTER

Address offset	0x0000 0040
Description	The L1 HIT Counter register holds the number of L1 Hits to the internal cache.
Type	RW

Bits	Field Name	Description			Type	Reset
31:12	READ_HIT_COUNTER	The hit Counts the number of hits to the L1 cache. Writing zero to this register will clear its contents When one reach the max, the rest of the counters are halted too.			RW	0x0 0000
11:0	READ_MISS_COUNTER	The miss Counts the number of misses to the L1 cache. Writing zero to this register will clear its contents. When one reach the max, the rest of the counters are halted too.			RW	0x000

:DCACHE:WRITE_COUNTER

Address offset	0x0000 0044
Description	The L1 MISS Counter register holds the number of L1 Misses to the internal cache.
Type	RW

Bits	Field Name	Description			Type	Reset
31:12	WRITE_HIT_COUNTER	The hit Counts the number of hits to the L1 cache. Writing zero to this register will clear its contents. When one reach the max, the rest of the counters are halted too.			RW	0x0 0000
11:0	WRITE_MISS_COUNTER	The miss Counts the number of misses to the L1 cache. Writing zero to this register will clear its contents. When one reach the max, the rest of the counters are halted too			RW	0x000

:DCACHE:ADDRESS_LATCH

Address offset	0x0000 0048
Description	When having OTFDE AHB error, Latch the address accessed by D-cache
Type	RW

Bits	Field Name	Description			Type	Reset
31:0	ADDRESS_LATCH	When D-cache receive AHB error from the OTFDE it should latch the address accessed by D-cache. (OTFDE generates an error for write only) Writing zero to this register will clear its contents.			RW	0x0000 0000

:DCACHE:CACHE_FSM_STATE

Address offset	0x0000 004C
Description
Type	RO

Bits	Field Name	Description			Type	Reset
31:5	RESERVED5	Dcache current FSM state			RO	0x000 0000
4:0	FSM_STATE	Dcache current FSM state WIDLE = 5'd0; - No access to D-cache WRAMWR = 5'd1; - Data RAM Write WRAMRD = 5'd2; - Data RAM Read WCREADT = 5'd4; - Read Hit WCREADC = 5'd5; - Read Miss WCWRITET = 5'd6; - Write Hit EVICT = 5'd7; -Write back to PSRAM WR_ALLOC = 5'd8; - Write Allocate in write miss RD_WA = 5'd9; - Word aligned read for a byte aligned read WD = 5'd10; - Writing data to PSRAM RDATA_CACHE = 5'd3; Reading data RAM for eviction DEC_DIR = 5'd11; - Deciding direction RDATA_CACHE_FLUSH = 5'd12; Reading data from data RAM for flush RD_SET = 5'd13; Reading TAG & MRU DET_GRANT = 5'd14; Detecting the granted way to evict EVICT_FLUSH = 5'd15; Eviction during Flush WD_DEBUG = 5'd16; Writing data to PSRAM during a debugger access			RO	0x00

:DCACHE:IRQSTATUS_RAW

Address offset	0x0000 0080
Description	The Interrupt Raw Status Register holds the raw status of the L1 error interrupts. Note: Read to the field of this register gives raw status of corresponding interrupt. S/W can set corresponding interrupt field for diagnostic purposes.
Type	RW

Bits	Field Name	Description			Type	Reset
1	LOCK_CFG_WR	The ~ilock_cfg_wr bit indicates a write to a locked configuration register has occured. Write 1 to set the ~ilock_cfg_wr status for diagnostic purposes. Writing a 0 has no effect.			RW	X
0	RESERVED0	reserved			RO	0

:DCACHE:IRQSTATUS_MSK

Address offset	0x0000 0084
Description	The Interrupt Masked Status Register holds the masked status for the L1 error interrupts. Writing to this register will EOI the interrupt, that is if another interrupt is pending, a new pulse interrupt will be generated. Note: Read to the field of this register gives masked status of corresponding interrupt. Writing 1 to the field of this register clears corresponding interrupt.
Type	RW

Bits	Field Name	Description			Type	Reset
1	LOCK_CFG_WR	The ~ilock_cfg_wr bit indicates a write to a locked configuration register has occured. Write 1 to clear the ~ilock_cfg_wr status after interrupt has been serviced (raw status gets cleared, i.e. even if not enabled). Writing a 0 has no effect to this field.			RW	X
0	RESERVED0	reserved			RO	0

:DCACHE:IRQENABLE_SET

Address offset	0x0000 0088
Description	The Interrupt Enable Set Register holds the interrupt enable status of the L1 error interrupts. Note:Writing 1 to field of this register will not mask the corresponding interrupt. IRQSTATUS_RAW and IRQSTATUS_MSK status field gives the same status.
Type	RW

Bits	Field Name	Description			Type	Reset
1	EN_LOCK_CFG_WR	Interrupt Enable Set for ~ilock_cfg_wr error bit. Writing a 1 will enable the interrupt, and set this bit as well as the corresponding Interrupt Enable Clear Register. Writing a 0 has no effect.			RW	X
0	RESERVED0	reserved			RO	0

:DCACHE:IRQENABLE_CLR

Address offset	0x0000 008C
Description	The Interrupt Enable Clear Register holds the interrupt enable status of the L1 error interrupts. Note:Writing 1 to field of this register masks the corresponding interrupt. IRQSTATUS_RAW and IRQSTATUS_MSK status field gives the raw status and masked status respectively
Type	RW

Bits	Field Name	Description			Type	Reset
1	EN_LOCK_CFG_WR	Interrupt Enable Clear for ~ilock_cfg_wr error bit. Writing a 1 will disable the interrupt, and clear this bit as well as the corresponding Interrupt Enable Set Register. Writing a 0 has no effect.			RW	X
0	RESERVED0	reserved			RO	0

:DCACHE:CTRL1

Address offset	0x0000 00C0
Description	Flush and invalidates requests
Type	RW

Bits	Field Name	Description			Type	Reset
31	FLUSH	0x0 - Do nothing 0x1 - Flush The bit is self cleared when flush completed			RW	0
30	INVALIDATE	0x0 - Do nothing 0x1 - Invalidate This bit is self cleared when invalidate completed			RW	0
29:0	RESERVED				RO	0bxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx

:DCACHE:STATUS1

Address offset	0x0000 00C4
Description	Flush and invalidates status
Type	RO

Bits	Field Name	Description			Type	Reset
31	FLUSH_STATUS	This bit indicates that Flush as been completed ( Bit is cleared when Flush request bit is asserted )			RO	0
30	INVALIDATE_STATUS	This bit indicates that invalidate has been completed ( Bit is cleared when flush request bit is asserted )			RO	0
29	FLUSH_FAIL	This bit indicates that Flush has failed ( Bit is cleared when Flush request bit is asserted )			RO	0
28:0	RESERVED				RO	0bx xxxx xxxx xxxx xxxx xxxx xxxx xxxx