ADC

This section provides information on the ADC Module Instance within this product. Each of the registers within the Module Instance is described separately below.

ADC Registers Mapping Summary

:ADC Common Register Mapping Summary

Register Name	Type	Register Width (Bits)	Register Reset	Address Offset
FSCTL0	RW	32	0x0044 554A	0x0000 0000
FSCTL1	RW	32	0x18F0 6630	0x0000 0004
FSCTL2	RW	32	0x0010 208A	0x0000 0008
FSCTL3	RW	32	0x0000 0000	0x0000 000C
REFBUF	RW	32	0x000A 6E09	0x0000 0010
ATB	RW	32	0x0000 0000	0x0000 0014
INTEVT0IDX	RO	32	0x0000 0000	0x0000 1020
INTEVT0BM	RW	32	0x0000 0000	0x0000 1028
INTEVT0RIS	RO	32	0x0000 0000	0x0000 1030
INTEVT0MIS	RO	32	0x0000 0000	0x0000 1038
INTEVT0SET	RW	32	0x0000 0000	0x0000 1040
INTEVT0CLR	RW	32	0x0000 0000	0x0000 1048
INTEVT1IDX	RO	32	0x0000 0000	0x0000 1050
INTEVT1BM	RW	32	0x0000 0000	0x0000 1058
INTEVT1RIS	RO	32	0x0000 0000	0x0000 1060
INTEVT1MIS	RO	32	0x0000 0000	0x0000 1068
INTEVT1SET	RW	32	0x0000 0000	0x0000 1070
INTEVT1CLR	RW	32	0x0000 0000	0x0000 1078
INTEVT2IDX	RO	32	0x0000 0000	0x0000 1080
INTEVT2BM	RW	32	0x0000 0000	0x0000 1088
INTEVT2RIS	RO	32	0x0000 0000	0x0000 1090
INTEVT2MIS	RO	32	0x0000 0000	0x0000 1098
INTEVT2SET	RW	32	0x0000 0000	0x0000 10A0
INTEVT2CLR	RW	32	0x0000 0000	0x0000 10A8
EVTMOD	RW	32	0x0000 0009	0x0000 10E0
DESC	RO	32	0x2611 0010	0x0000 10FC
CTL0	RW	32	0x0000 0000	0x0000 1100
CTL1	RW	32	0x0000 0000	0x0000 1104
CTL2	RW	32	0x0000 0000	0x0000 1108
CTL3	RW	32	0x0000 0000	0x0000 110C
CLKFREQ	RW	32	0x0000 0000	0x0000 1110
SCOMP0	RW	32	0x0000 0000	0x0000 1114
SCOMP1	RW	32	0x0000 0000	0x0000 1118
REFCFG	RW	32	0x0000 0000	0x0000 111C
WCLOW	RW	32	0x0000 0000	0x0000 1148
WCHI	RW	32	0x0000 0000	0x0000 1150
FIFODATA	RO	32	0x0000 0000	0x0000 1160
ASCRES	RO	32	0x0000 0000	0x0000 1170
MEMCTL__0 - MEMCTL__5	RW	32	0x0000 0100	0x0000 1180-0x0000 1194
MEMRES__0 - MEMRES__15	RO	32	0x0000 0000	0x0000 1280-0x0000 12BC
STA	RO	32	0x0000 0000	0x0000 1340
TEST0	RW	32	0x0000 0000	0x0000 1E00
TEST1	RW	32	0x0000 0000	0x0000 1E04
TEST2	RW	32	0x0000 0000	0x0000 1E08
TEST3	RW	32	0x0000 0000	0x0000 1E0C
TEST4	RW	32	0x0000 0000	0x0000 1E10
TEST5	RW	32	0x0000 0000	0x0000 1E14
TEST6	RW	32	0x0000 0000	0x0000 1E18
DBG1	RW	32	0x0080 1000	0x0000 1E20
DBG2	RW	32	0x0000 0000	0x0000 1E24
DBG3	RW	32	0x0000 0000	0x0000 1E28
DBG4	RW	32	0x0000 0000	0x0000 1E2C
CONVCTL	RW	32	0x0000 0000	0x0000 1F14
CTRL	RW	32	0x0000 4000	0x0000 1F18
ADC_MOD_CTRL	RW	32	0x0000 0000	0x0000 1F1C
INTCHCTL	RW	32	0x0000 0000	0x0000 1F20
STLTIM	RW	32	0x0167 0027	0x0000 1F24
CLKCFG	RW	32	0x0000 0000	0x0000 2000

ADC Instances Register Mapping Summary

ADC Register Descriptions

:ADC Common Register Descriptions

:ADC:FSCTL0

Address offset	0x0000 0000
Description	FUSE CONTROL 0 Primarily for lab testing, needs to be written by TI boot code All may not be used now, few spare are kept intentionally
Type	RW

Bits	Field Name	Description			Type	Reset
31:0	TRIM0	TRIM VALUE 0			RW	0x0044 554A

:ADC:FSCTL1

Address offset	0x0000 0004
Description	FUSE CONTROL 1 Primarily for lab testing, needs to be written by TI boot code All may not be used now, few spare are kept intentionally
Type	RW

Bits	Field Name	Description			Type	Reset
31:0	TRIM1	TRIM VALUE 1			RW	0x18F0 6630

:ADC:FSCTL2

Address offset	0x0000 0008
Description	FUSE CONTROL 2 Primarily for lab testing, needs to be written by TI boot code All may not be used now, few spare are kept intentionally
Type	RW

Bits	Field Name	Description			Type	Reset
31:0	TRIM2	TRIM VALUE 2			RW	0x0010 208A

:ADC:FSCTL3

Address offset	0x0000 000C
Description	FUSE CONTROL 3 Primarily for lab testing, needs to be written by TI boot code All may not be used now, few spare are kept intentionally
Type	RW

Bits	Field Name	Description	Type	Reset
31:16	Reserved		RO	0x0000
15:0	TRIM3	TRIM VALUE 3	RW	0x0000

:ADC:REFBUF

Address offset	0x0000 0010
Description	REFERENCE BUFFER
Type	RW

Bits	Field Name	Description			Type	Reset
31:0	CFG	CONFIG bit[0] - Enable Internal Reference Mode bits[3:1] - Vsel for 3.3V mode Internal Reference Mode. Vrefbuf = 1.3V bits[6:4] - Vsel bits for higher tap points - For debug purpose <6:4> --> 001 (0.9V) <6:4> --> 010 (1.45V) <6:4> --> 100 (1.4V) bits[8:7] - Enable Test mux to check ground and reference thought test pins 01--> Vref Internal available to measure 10 --> vss Internal Reference available to measure bits[10:9] - Trim bits to change the bias current in Ref buf 1st stage bits[12:11] - Trim bits to change the bias current in Ref buf bits[14:13] - Trim bits to change the bias current in Ref buf output stage bits[16:15] - NU bits[19:17] - Vsel for 1.8V mode Internal Reference Mode .Vrefbuf = 1.35V bits[31:20] - NU			RW	0x000A 6E09

:ADC:ATB

Address offset	0x0000 0014
Description	ATB
Type	RW

Bits	Field Name	Description		Type	Reset
31:8	Reserved			RO	0x00 0000
7:0	CTRL	CONTROL bit0- master enable of test mux for AIP bit1- refbuf test enable bit2- 20uA current (scaled from PMCIO) test enable bit3- vbat_div test enable bit4- Tsense test enable bit5- Bandgap 0p9v test enable bit6- No connect bit7- No connect		RW	0x00
		0x00	NO_INTR No bit is set means there is no pending interrupt request
		0x01	OVIFG MEMRESx overflow interrupt
		0x02	TOVIFG Sequence Conversion time overflow interrupt
		0x03	HIFG High threshold compare interrupt
		0x04	LOFG Low threshold compare interrupt
		0x05	INIFG Primary Sequence In range comparator interrupt
		0x06	DMADONE DMA done interrupt, generated on DMA transfer completion,
		0x07	UVIFG MEMRESx underflow interrupt
		0x09	MEMRESIFG0 MEMRES0 data loaded interrupt
		0x0A	MEMRESIFG1 MEMRES1 data loaded interrupt
		0x0B	MEMRESIFG2 MEMRES2 data loaded interrupt
		0x0C	MEMRESIFG3 MEMRES3 data loaded interrupt
		0x0D	MEMRESIFG4 MEMRES4 data loaded interrupt
		0x0E	MEMRESIFG5 MEMRES5 data loaded interrupt
		0x0F	MEMRESIFG6 MEMRES6 data loaded interrupt
		0x10	MEMRESIFG7 MEMRES7 data loaded interrupt
		0x11	MEMRESIFG8 MEMRES8 data loaded interrupt
		0x12	MEMRESIFG9 MEMRES9 data loaded interrupt
		0x13	MEMRESIFG10 MEMRES10 data loaded interrupt
		0x14	MEMRESIFG11 MEMRES11 data loaded interrupt
		0x15	MEMRESIFG12 MEMRES12 data loaded interrupt
		0x16	MEMRESIFG13 MEMRES13 data loaded interrupt
		0x17	MEMRESIFG14 MEMRES14 data loaded interrupt
		0x18	MEMRESIFG15 MEMRES15 data loaded interrupt
		0x19	MEMRESIFG16 MEMRES16 data loaded interrupt
		0x1A	MEMRESIFG17 MEMRES17 data loaded interrupt
		0x1B	MEMRESIFG18 MEMRES18 data loaded interrupt
		0x1C	MEMRESIFG19 MEMRES19 data loaded interrupt
		0x1D	MEMRESIFG20 MEMRES20 data loaded interrupt
		0x1E	MEMRESIFG21 MEMRES21 data loaded interrupt
		0x1F	MEMRESIFG22 MEMRES22 data loaded interrupt
		0x20	MEMRESIFG23 MEMRES23 data loaded interrupt

:ADC:INTEVT0IDX

Address offset	0x0000 1020
Description	INTERNAL EVENT 0 IRQ IDX This register provides the highest priority enabled interrupt index. 0x0 means no event pending. Interrupt 1 is the highest priority, 2 next highest, 4, 8, ... 2^31 is the least priority. That is, the least bit position that is set to 1 denotes the highest priority pending interrupt. The priority order is fixed. However, users can implement their own prioritization schemes using other registers that expose the full set of interrupts that have occurred. On each read, only one interrupt is indicated. On a read, the current interrupt (highest priority) is automatically cleared by the hardware and the corresponding interrupt flag in the RIS and MIS are cleared as well. After a read from the CPU (not from the debug interface), the register must be updated with the next highest priority interrupt, if none are pending, then it should display 0x0.
Type	RO

Bits	Field Name	Description		Type	Reset
31:10	Reserved			RO	0x00 0000
9:0	STAT	Interrupt index status		RO	0x000
		Read 0x000	NO_INTR No bit is set means there is no pending interrupt request
		Read 0x001	OVIFG MEMRESx overflow interrupt
		Read 0x002	TOVIFG Sequence Conversion time overflow interrupt
		Read 0x003	HIFG High threshold compare interrupt
		Read 0x004	LOFG Low threshold compare interrupt
		Read 0x005	INIFG Primary Sequence In range comparator interrupt
		Read 0x006	DMADONE DMA done interrupt, generated on DMA transfer completion,
		Read 0x007	UVIFG MEMRESx underflow interrupt
		Read 0x009	MEMRESIFG0 MEMRES0 data loaded interrupt
		Read 0x00A	MEMRESIFG1 MEMRES1 data loaded interrupt
		Read 0x00B	MEMRESIFG2 MEMRES2 data loaded interrupt
		Read 0x00C	MEMRESIFG3 MEMRES3 data loaded interrupt
		Read 0x00D	MEMRESIFG4 MEMRES4 data loaded interrupt
		Read 0x00E	MEMRESIFG5 MEMRES5 data loaded interrupt
		Read 0x00F	MEMRESIFG6 MEMRES6 data loaded interrupt
		Read 0x010	MEMRESIFG7 MEMRES7 data loaded interrupt
		Read 0x011	MEMRESIFG8 MEMRES8 data loaded interrupt
		Read 0x012	MEMRESIFG9 MEMRES9 data loaded interrupt
		Read 0x013	MEMRESIFG10 MEMRES10 data loaded interrupt
		Read 0x014	MEMRESIFG11 MEMRES11 data loaded interrupt
		Read 0x015	MEMRESIFG12 MEMRES12 data loaded interrupt
		Read 0x016	MEMRESIFG13 MEMRES13 data loaded interrupt
		Read 0x017	MEMRESIFG14 MEMRES14 data loaded interrupt
		Read 0x018	MEMRESIFG15 MEMRES15 data loaded interrupt
		Read 0x019	MEMRESIFG16 MEMRES16 data loaded interrupt
		Read 0x01A	MEMRESIFG17 MEMRES17 data loaded interrupt
		Read 0x01B	MEMRESIFG18 MEMRES18 data loaded interrupt
		Read 0x01C	MEMRESIFG19 MEMRES19 data loaded interrupt
		Read 0x01D	MEMRESIFG20 MEMRES20 data loaded interrupt
		Read 0x01E	MEMRESIFG21 MEMRES21 data loaded interrupt
		Read 0x01F	MEMRESIFG22 MEMRES22 data loaded interrupt
		Read 0x020	MEMRESIFG23 MEMRES23 data loaded interrupt

:ADC:INTEVT0BM

Address offset	0x0000 1028
Description	INTERNAL EVENT 0 IRQ MASK Interrupt Mask. If a bit is set, then corresponding interrupt is un-masked. Un-masking the interrupt causes the raw interrupt to be visible in IIDX, as well as MIS.
Type	RW

Bits	Field Name	Description		Type	Reset
31:24	Reserved			RO	0x00
23	MEMRESIFG15	Raw interrupt status for MEMRES15. This bit is set to 1 when MEMRES15 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		RW	0
		0	CLR No new data ready.
		1	SET A new data is ready to be read.
22	MEMRESIFG14	Raw interrupt status for MEMRES14. This bit is set to 1 when MEMRES14 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		RW	0
		0	CLR No new data ready.
		1	SET A new data is ready to be read.
21	MEMRESIFG13	Raw interrupt status for MEMRES13. This bit is set to 1 when MEMRES13 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		RW	0
		0	CLR No new data ready.
		1	SET A new data is ready to be read.
20	MEMRESIFG12	Raw interrupt status for MEMRES12. This bit is set to 1 when MEMRES12 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		RW	0
		0	CLR No new data ready.
		1	SET A new data is ready to be read.
19	MEMRESIFG11	Raw interrupt status for MEMRES11. This bit is set to 1 when MEMRES11 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		RW	0
		0	CLR No new data ready.
		1	SET A new data is ready to be read.
18	MEMRESIFG10	Raw interrupt status for MEMRES10. This bit is set to 1 when MEMRES10 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		RW	0
		0	CLR No new data ready.
		1	SET A new data is ready to be read.
17	MEMRESIFG9	Raw interrupt status for MEMRES9. This bit is set to 1 when MEMRES9 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		RW	0
		0	CLR No new data ready.
		1	SET A new data is ready to be read.
16	MEMRESIFG8	Raw interrupt status for MEMRES8. This bit is set to 1 when MEMRES8 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		RW	0
		0	CLR No new data ready.
		1	SET A new data is ready to be read.
15	MEMRESIFG7	Raw interrupt status for MEMRES7. This bit is set to 1 when MEMRES7 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		RW	0
		0	CLR No new data ready.
		1	SET A new data is ready to be read.
14	MEMRESIFG6	Raw interrupt status for MEMRES6. This bit is set to 1 when MEMRES6 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		RW	0
		0	CLR No new data ready.
		1	SET A new data is ready to be read.
13	MEMRESIFG5	Raw interrupt status for MEMRES5. This bit is set to 1 when MEMRES5 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		RW	0
		0	CLR No new data ready.
		1	SET A new data is ready to be read.
12	MEMRESIFG4	Raw interrupt status for MEMRES4. This bit is set to 1 when MEMRES4 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		RW	0
		0	CLR No new data ready.
		1	SET A new data is ready to be read.
11	MEMRESIFG3	Raw interrupt status for MEMRES3. This bit is set to 1 when MEMRES3 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		RW	0
		0	CLR No new data ready.
		1	SET A new data is ready to be read.
10	MEMRESIFG2	Raw interrupt status for MEMRES2. This bit is set to 1 when MEMRES2 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		RW	0
		0	CLR No new data ready.
		1	SET A new data is ready to be read.
9	MEMRESIFG1	Raw interrupt status for MEMRES1. This bit is set to 1 when MEMRES1 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		RW	0
		0	CLR No new data ready.
		1	SET A new data is ready to be read.
8	MEMRESIFG0	Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		RW	0
		0	CLR No new data ready.
		1	SET A new data is ready to be read.
7	Reserved			RO	0
6	UVIFG	Raw interrupt flag for MEMRESx underflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR is set to 1.		RW	0
		0	CLR Interrupt is not pending.
		1	SET Interrupt is pending.
5	DMADONE	Raw interrupt flag for DMADONE. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.		RW	0
		0	CLR Interrupt is not pending.
		1	SET Interrupt is pending.
4	INIFG	Mask INIFG in MIS_EX register.		RW	0
		0	CLR Interrupt is not pending.
		1	SET Interrupt is pending.
3	LOFG	LOW FG Raw interrupt flag for the MEMRESx result register being below than the WCLOWx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.		RW	0
		0	CLR Interrupt is not pending.
		1	SET Interrupt is pending.
2	HIFG	Raw interrupt flag for the MEMRESx result register being higher than the WCHIx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.		RW	0
		0	CLR Interrupt is not pending.
		1	SET Interrupt is pending.
1	TOVIFG	Raw interrupt flag for sequence conversion timeout overflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.		RW	0
		0	CLR Interrupt is not pending.
		1	SET Interrupt is pending.
0	OVIFG	Raw interrupt flag for MEMRESx overflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.		RW	0
		0	CLR Interrupt is not pending.
		1	SET Interrupt is pending.

:ADC:INTEVT0RIS

Address offset	0x0000 1030
Description	INTERNAL EVENT 0 RAW IRQ STA Raw interrupt status. Reflects all pending interrupts, regardless of masking. The INTEVT0RIS register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the ICLR register bit even if the corresponding IMASK bit is not enabled.
Type	RO

Bits	Field Name	Description		Type	Reset
31:24	Reserved			RO	0x00
23	MEMRESIFG15	Raw interrupt status for MEMRES15. This bit is set to 1 when MEMRES15 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		RO	0
		Read 0	CLR No new data ready.
		Read 1	SET A new data is ready to be read.
22	MEMRESIFG14	Raw interrupt status for MEMRES14. This bit is set to 1 when MEMRES14 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		RO	0
		Read 0	CLR No new data ready.
		Read 1	SET A new data is ready to be read.
21	MEMRESIFG13	Raw interrupt status for MEMRES13. This bit is set to 1 when MEMRES13 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		RO	0
		Read 0	CLR No new data ready.
		Read 1	SET A new data is ready to be read.
20	MEMRESIFG12	Raw interrupt status for MEMRES12. This bit is set to 1 when MEMRES12 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		RO	0
		Read 0	CLR No new data ready.
		Read 1	SET A new data is ready to be read.
19	MEMRESIFG11	Raw interrupt status for MEMRES11. This bit is set to 1 when MEMRES11 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		RO	0
		Read 0	CLR No new data ready.
		Read 1	SET A new data is ready to be read.
18	MEMRESIFG10	Raw interrupt status for MEMRES10. This bit is set to 1 when MEMRES10 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		RO	0
		Read 0	CLR No new data ready.
		Read 1	SET A new data is ready to be read.
17	MEMRESIFG9	Raw interrupt status for MEMRES9. This bit is set to 1 when MEMRES9 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		RO	0
		Read 0	CLR No new data ready.
		Read 1	SET A new data is ready to be read.
16	MEMRESIFG8	Raw interrupt status for MEMRES8. This bit is set to 1 when MEMRES8 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		RO	0
		Read 0	CLR No new data ready.
		Read 1	SET A new data is ready to be read.
15	MEMRESIFG7	Raw interrupt status for MEMRES7. This bit is set to 1 when MEMRES7 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		RO	0
		Read 0	CLR No new data ready.
		Read 1	SET A new data is ready to be read.
14	MEMRESIFG6	Raw interrupt status for MEMRES6. This bit is set to 1 when MEMRES6 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		RO	0
		Read 0	CLR No new data ready.
		Read 1	SET A new data is ready to be read.
13	MEMRESIFG5	Raw interrupt status for MEMRES5. This bit is set to 1 when MEMRES5 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		RO	0
		Read 0	CLR No new data ready.
		Read 1	SET A new data is ready to be read.
12	MEMRESIFG4	Raw interrupt status for MEMRES4. This bit is set to 1 when MEMRES4 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		RO	0
		Read 0	CLR No new data ready.
		Read 1	SET A new data is ready to be read.
11	MEMRESIFG3	Raw interrupt status for MEMRES3. This bit is set to 1 when MEMRES3 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		RO	0
		Read 0	CLR No new data ready.
		Read 1	SET A new data is ready to be read.
10	MEMRESIFG2	Raw interrupt status for MEMRES2. This bit is set to 1 when MEMRES2 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		RO	0
		Read 0	CLR No new data ready.
		Read 1	SET A new data is ready to be read.
9	MEMRESIFG1	Raw interrupt status for MEMRES1. This bit is set to 1 when MEMRES1 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		RO	0
		Read 0	CLR No new data ready.
		Read 1	SET A new data is ready to be read.
8	MEMRESIFG0	Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		RO	0
		Read 0	CLR No new data ready.
		Read 1	SET A new data is ready to be read.
7	Reserved			RO	0
6	UVIFG	Raw interrupt flag for MEMRESx underflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR is set to 1.		RO	0
		Read 0	CLR Interrupt is not pending.
		Read 1	SET Interrupt is pending.
5	DMADONE	Raw interrupt flag for DMADONE. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.		RO	0
		Read 0	CLR Interrupt is not pending.
		Read 1	SET Interrupt is pending.
4	INIFG	Mask INIFG in MIS_EX register.		RO	0
		Read 0	CLR Interrupt is not pending.
		Read 1	SET Interrupt is pending.
3	LOFG	LOW FG Raw interrupt flag for the MEMRESx result register being below than the WCLOWx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.		RO	0
		Read 0	CLR Interrupt is not pending.
		Read 1	SET Interrupt is pending.
2	HIFG	HIGH FG Raw interrupt flag for the MEMRESx result register being higher than the WCHIx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.		RO	0
		Read 0	CLR Interrupt is not pending.
		Read 1	SET Interrupt is pending.
1	TOVIFG	Raw interrupt flag for sequence conversion timeout overflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.		RO	0
		Read 0	CLR Interrupt is not pending.
		Read 1	SET Interrupt is pending.
0	OVIFG	Raw interrupt flag for MEMRESx overflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.		RO	0
		Read 0	CLR Interrupt is not pending.
		Read 1	SET Interrupt is pending.

:ADC:INTEVT0MIS

Address offset	0x0000 1038
Description	INTERNAL EVENT 0 MASKED IRQ STA Masked interrupt status. This is an AND of the IMASK and RIS registers.
Type	RO

Bits	Field Name	Description		Type	Reset
31:24	Reserved			RO	0x00
23	MEMRESIFG15	Raw interrupt status for MEMRES15. This bit is set to 1 when MEMRES15 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		RO	0
		Read 0	CLR No new data ready.
		Read 1	SET A new data is ready to be read.
22	MEMRESIFG14	Raw interrupt status for MEMRES14. This bit is set to 1 when MEMRES14 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		RO	0
		Read 0	CLR No new data ready.
		Read 1	SET A new data is ready to be read.
21	MEMRESIFG13	Raw interrupt status for MEMRES13. This bit is set to 1 when MEMRES13 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		RO	0
		Read 0	CLR No new data ready.
		Read 1	SET A new data is ready to be read.
20	MEMRESIFG12	Raw interrupt status for MEMRES12. This bit is set to 1 when MEMRES12 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		RO	0
		Read 0	CLR No new data ready.
		Read 1	SET A new data is ready to be read.
19	MEMRESIFG11	Raw interrupt status for MEMRES11. This bit is set to 1 when MEMRES11 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		RO	0
		Read 0	CLR No new data ready.
		Read 1	SET A new data is ready to be read.
18	MEMRESIFG10	Raw interrupt status for MEMRES10. This bit is set to 1 when MEMRES10 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		RO	0
		Read 0	CLR No new data ready.
		Read 1	SET A new data is ready to be read.
17	MEMRESIFG9	Raw interrupt status for MEMRES9. This bit is set to 1 when MEMRES9 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		RO	0
		Read 0	CLR No new data ready.
		Read 1	SET A new data is ready to be read.
16	MEMRESIFG8	Raw interrupt status for MEMRES8. This bit is set to 1 when MEMRES8 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		RO	0
		Read 0	CLR No new data ready.
		Read 1	SET A new data is ready to be read.
15	MEMRESIFG7	Raw interrupt status for MEMRES7. This bit is set to 1 when MEMRES7 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		RO	0
		Read 0	CLR No new data ready.
		Read 1	SET A new data is ready to be read.
14	MEMRESIFG6	Raw interrupt status for MEMRES6. This bit is set to 1 when MEMRES6 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		RO	0
		Read 0	CLR No new data ready.
		Read 1	SET A new data is ready to be read.
13	MEMRESIFG5	Raw interrupt status for MEMRES5. This bit is set to 1 when MEMRES5 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		RO	0
		Read 0	CLR No new data ready.
		Read 1	SET A new data is ready to be read.
12	MEMRESIFG4	Raw interrupt status for MEMRES4. This bit is set to 1 when MEMRES4 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		RO	0
		Read 0	CLR No new data ready.
		Read 1	SET A new data is ready to be read.
11	MEMRESIFG3	Raw interrupt status for MEMRES3. This bit is set to 1 when MEMRES3 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		RO	0
		Read 0	CLR No new data ready.
		Read 1	SET A new data is ready to be read.
10	MEMRESIFG2	Raw interrupt status for MEMRES2. This bit is set to 1 when MEMRES2 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		RO	0
		Read 0	CLR No new data ready.
		Read 1	SET A new data is ready to be read.
9	MEMRESIFG1	Raw interrupt status for MEMRES1. This bit is set to 1 when MEMRES1 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		RO	0
		Read 0	CLR No new data ready.
		Read 1	SET A new data is ready to be read.
8	MEMRESIFG0	Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 11		RO	0
		Read 0	CLR No new data ready.
		Read 1	SET A new data is ready to be read.
7	Reserved			RO	0
6	UVIFG	Raw interrupt flag for MEMRESx underflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR is set to 1.		RO	0
		Read 0	CLR Interrupt is not pending.
		Read 1	SET Interrupt is pending.
5	DMADONE	Raw interrupt flag for DMADONE. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.		RO	0
		Read 0	CLR Interrupt is not pending.
		Read 1	SET Interrupt is pending.
4	INIFG	Mask INIFG in MIS_EX register.		RO	0
		Read 0	CLR Interrupt is not pending.
		Read 1	SET Interrupt is pending.
3	LOFG	LOW FG Raw interrupt flag for the MEMRESx result register being below than the WCLOWx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.		RO	0
		Read 0	CLR Interrupt is not pending.
		Read 1	SET Interrupt is pending.
2	HIFG	HIGH FG Raw interrupt flag for the MEMRESx result register being higher than the WCHIx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.		RO	0
		Read 0	CLR Interrupt is not pending.
		Read 1	SET Interrupt is pending.
1	TOVIFG	Raw interrupt flag for sequence conversion timeout overflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.		RO	0
		Read 0	CLR Interrupt is not pending.
		Read 1	SET Interrupt is pending.
0	OVIFG	Raw interrupt flag for MEMRESx overflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.		RO	0
		Read 0	CLR Interrupt is not pending.
		Read 1	SET Interrupt is pending.

:ADC:INTEVT0SET

Address offset	0x0000 1040
Description	INTERNAL EVENT 0 IRQ SET Interrupt set. Allows interrupts to be set by software (useful in diagnostics and safety checks). Writing a 1 to a bit in INTEVT0SET will set the event and therefore the related RIS bit also gets set. If the interrupt is enabled through the mask, then the corresponding MIS bit is also set.
Type	RW

Bits	Field Name	Description		Type	Reset
31:24	Reserved			RO	0x00
23	MEMRESIFG15	Raw interrupt status for MEMRES15. This bit is set to 1 when MEMRES15 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		WO	0
		Write 0	NO_EFFECT No new data ready.
		Write 1	SET A new data is ready to be read.
22	MEMRESIFG14	Raw interrupt status for MEMRES14. This bit is set to 1 when MEMRES14 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		WO	0
		Write 0	NO_EFFECT No new data ready.
		Write 1	SET A new data is ready to be read.
21	MEMRESIFG13	Raw interrupt status for MEMRES13. This bit is set to 1 when MEMRES13 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		WO	0
		Write 0	NO_EFFECT No new data ready.
		Write 1	SET A new data is ready to be read.
20	MEMRESIFG12	Raw interrupt status for MEMRES12. This bit is set to 1 when MEMRES12 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		WO	0
		Write 0	NO_EFFECT No new data ready.
		Write 1	SET A new data is ready to be read.
19	MEMRESIFG11	Raw interrupt status for MEMRES11. This bit is set to 1 when MEMRES11 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		WO	0
		Write 0	NO_EFFECT No new data ready.
		Write 1	SET A new data is ready to be read.
18	MEMRESIFG10	Raw interrupt status for MEMRES10. This bit is set to 1 when MEMRES10 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		WO	0
		Write 0	NO_EFFECT No new data ready.
		Write 1	SET A new data is ready to be read.
17	MEMRESIFG9	Raw interrupt status for MEMRES9. This bit is set to 1 when MEMRES9 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		WO	0
		Write 0	NO_EFFECT No new data ready.
		Write 1	SET A new data is ready to be read.
16	MEMRESIFG8	Raw interrupt status for MEMRES8. This bit is set to 1 when MEMRES8 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		WO	0
		Write 0	NO_EFFECT No new data ready.
		Write 1	SET A new data is ready to be read.
15	MEMRESIFG7	Raw interrupt status for MEMRES7. This bit is set to 1 when MEMRES7 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		WO	0
		Write 0	NO_EFFECT No new data ready.
		Write 1	SET A new data is ready to be read.
14	MEMRESIFG6	Raw interrupt status for MEMRES6. This bit is set to 1 when MEMRES6 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		WO	0
		Write 0	NO_EFFECT No new data ready.
		Write 1	SET A new data is ready to be read.
13	MEMRESIFG5	Raw interrupt status for MEMRES5. This bit is set to 1 when MEMRES5 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		WO	0
		Write 0	NO_EFFECT No new data ready.
		Write 1	SET A new data is ready to be read.
12	MEMRESIFG4	Raw interrupt status for MEMRES4. This bit is set to 1 when MEMRES4 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		WO	0
		Write 0	NO_EFFECT No new data ready.
		Write 1	SET A new data is ready to be read.
11	MEMRESIFG3	Raw interrupt status for MEMRES3. This bit is set to 1 when MEMRES3 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		WO	0
		Write 0	NO_EFFECT No new data ready.
		Write 1	SET A new data is ready to be read.
10	MEMRESIFG2	Raw interrupt status for MEMRES2. This bit is set to 1 when MEMRES2 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		WO	0
		Write 0	NO_EFFECT No new data ready.
		Write 1	SET A new data is ready to be read.
9	MEMRESIFG1	Raw interrupt status for MEMRES1. This bit is set to 1 when MEMRES1 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		WO	0
		Write 0	NO_EFFECT No new data ready.
		Write 1	SET A new data is ready to be read.
8	MEMRESIFG0	Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		WO	0
		Write 0	NO_EFFECT No new data ready.
		Write 1	SET A new data is ready to be read.
7	Reserved			RO	0
6	UVIFG	Raw interrupt flag for MEMRESx underflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.		WO	0
		Write 0	NO_EFFECT Interrupt is not pending.
		Write 1	SET Interrupt is pending.
5	DMADONE	Raw interrupt flag for DMADONE. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.		WO	0
		Write 0	NO_EFFECT Interrupt is not pending.
		Write 1	SET Interrupt is pending.
4	INIFG	Mask INIFG in MIS_EX register.		WO	0
		Write 0	NO_EFFECT Interrupt is not pending.
		Write 1	SET Interrupt is pending.
3	LOFG	LOW FG Raw interrupt flag for the MEMRESx result register being below than the WCLOWx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.		WO	0
		Write 0	NO_EFFECT Interrupt is not pending.
		Write 1	SET Interrupt is pending.
2	HIFG	HIGH FG Raw interrupt flag for the MEMRESx result register being higher than the WCHIx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.		WO	0
		Write 0	NO_EFFECT Interrupt is not pending.
		Write 1	SET Interrupt is pending.
1	TOVIFG	Raw interrupt flag for sequence conversion timeout overflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.		WO	0
		Write 0	NO_EFFECT Interrupt is not pending.
		Write 1	SET Interrupt is pending.
0	OVIFG	Raw interrupt flag for MEMRESx overflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.		WO	0
		Write 0	NO_EFFECT Interrupt is not pending.
		Write 1	SET Interrupt is pending.

:ADC:INTEVT0CLR

Address offset	0x0000 1048
Description	INTERNAL EVENT 0 IRQ CLEAR Interrupt clear. Write a 1 to clear corresponding Interrupt.
Type	RW

Bits	Field Name	Description		Type	Reset
31:24	Reserved			RO	0x00
23	MEMRESIFG15	Raw interrupt status for MEMRES15. This bit is set to 1 when MEMRES15 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		WO	0
		Write 0	NO_EFFECT No new data ready.
		Write 1	CLR A new data is ready to be read.
22	MEMRESIFG14	Raw interrupt status for MEMRES14. This bit is set to 1 when MEMRES14 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		WO	0
		Write 0	NO_EFFECT No new data ready.
		Write 1	CLR A new data is ready to be read.
21	MEMRESIFG13	Raw interrupt status for MEMRES13. This bit is set to 1 when MEMRES13 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		WO	0
		Write 0	NO_EFFECT No new data ready.
		Write 1	CLR A new data is ready to be read.
20	MEMRESIFG12	Raw interrupt status for MEMRES12. This bit is set to 1 when MEMRES12 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		WO	0
		Write 0	NO_EFFECT No new data ready.
		Write 1	CLR A new data is ready to be read.
19	MEMRESIFG11	Raw interrupt status for MEMRES11. This bit is set to 1 when MEMRES11 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		WO	0
		Write 0	NO_EFFECT No new data ready.
		Write 1	CLR A new data is ready to be read.
18	MEMRESIFG10	Raw interrupt status for MEMRES10. This bit is set to 1 when MEMRES10 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		WO	0
		Write 0	NO_EFFECT No new data ready.
		Write 1	CLR A new data is ready to be read.
17	MEMRESIFG9	Raw interrupt status for MEMRES9. This bit is set to 1 when MEMRES9 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		WO	0
		Write 0	NO_EFFECT No new data ready.
		Write 1	CLR A new data is ready to be read.
16	MEMRESIFG8	Raw interrupt status for MEMRES8. This bit is set to 1 when MEMRES8 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		WO	0
		Write 0	NO_EFFECT No new data ready.
		Write 1	CLR A new data is ready to be read.
15	MEMRESIFG7	Raw interrupt status for MEMRES7. This bit is set to 1 when MEMRES7 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		WO	0
		Write 0	NO_EFFECT No new data ready.
		Write 1	CLR A new data is ready to be read.
14	MEMRESIFG6	Raw interrupt status for MEMRES6. This bit is set to 1 when MEMRES6 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		WO	0
		Write 0	NO_EFFECT No new data ready.
		Write 1	CLR A new data is ready to be read.
13	MEMRESIFG5	Raw interrupt status for MEMRES5. This bit is set to 1 when MEMRES5 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		WO	0
		Write 0	NO_EFFECT No new data ready.
		Write 1	CLR A new data is ready to be read.
12	MEMRESIFG4	Raw interrupt status for MEMRES4. This bit is set to 1 when MEMRES4 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		WO	0
		Write 0	NO_EFFECT No new data ready.
		Write 1	CLR A new data is ready to be read.
11	MEMRESIFG3	Raw interrupt status for MEMRES3. This bit is set to 1 when MEMRES3 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		WO	0
		Write 0	NO_EFFECT No new data ready.
		Write 1	CLR A new data is ready to be read.
10	MEMRESIFG2	Raw interrupt status for MEMRES2. This bit is set to 1 when MEMRES2 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		WO	0
		Write 0	NO_EFFECT No new data ready.
		Write 1	CLR A new data is ready to be read.
9	MEMRESIFG1	Raw interrupt status for MEMRES1. This bit is set to 1 when MEMRES1 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		WO	0
		Write 0	NO_EFFECT No new data ready.
		Write 1	CLR A new data is ready to be read.
8	MEMRESIFG0	Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		WO	0
		Write 0	NO_EFFECT No new data ready.
		Write 1	CLR A new data is ready to be read.
7	Reserved			RO	0
6	UVIFG	Raw interrupt flag for MEMRESx underflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.		WO	0
		Write 0	NO_EFFECT Interrupt is not pending.
		Write 1	CLR Interrupt is pending.
5	DMADONE	Raw interrupt flag for DMADONE. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.		WO	0
		Write 0	NO_EFFECT Interrupt is not pending.
		Write 1	CLR Interrupt is pending.
4	INIFG	Mask INIFG in MIS_EX register.		WO	0
		Write 0	NO_EFFECT Interrupt is not pending.
		Write 1	CLR Interrupt is pending.
3	LOFG	LOW FG Raw interrupt flag for the MEMRESx result register being below than the WCLOWx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.		WO	0
		Write 0	NO_EFFECT Interrupt is not pending.
		Write 1	CLR Interrupt is pending.
2	HIFG	HIGH FG Raw interrupt flag for the MEMRESx result register being higher than the WCHIx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.		WO	0
		Write 0	NO_EFFECT Interrupt is not pending.
		Write 1	CLR Interrupt is pending.
1	TOVIFG	Raw interrupt flag for sequence conversion timeout overflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.		WO	0
		Write 0	NO_EFFECT Interrupt is not pending.
		Write 1	CLR Interrupt is pending.
0	OVIFG	Raw interrupt flag for MEMRESx overflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.		WO	0
		Write 0	NO_EFFECT Interrupt is not pending.
		Write 1	CLR Interrupt is pending.

:ADC:INTEVT1IDX

Address offset	0x0000 1050
Description	INTERNAL EVENT 1 IRQ IDX This register provides the highest priority enabled interrupt index. 0x0 means no event pending. Interrupt 1 is the highest priority, 2 next highest, 4, 8, ... 2^31 is the least priority. That is, the least bit position that is set to 1 denotes the highest priority pending interrupt. The priority order is fixed. However, users can implement their own prioritization schemes using other registers that expose the full set of interrupts that have occurred. On each read, only one interrupt is indicated. On a read, the current interrupt (highest priority) is automatically cleared by the hardware and the corresponding interrupt flag in the RIS and MIS are cleared as well. After a read from the CPU (not from the debug interface), the register must be updated with the next highest priority interrupt, if none are pending, then it should display 0x0.
Type	RO

Bits	Field Name	Description		Type	Reset
31:10	Reserved			RO	0x00 0000
9:0	STAT	Interrupt index status		RO	0x000
		Read 0x000	NO_INTR No bit is set means there is no pending interrupt request
		Read 0x003	HIFG High threshold compare interrupt
		Read 0x004	LOFG Low threshold compare interrupt
		Read 0x005	INIFG Primary Sequence In range comparator interrupt
		Read 0x009	MEMRESIFG0 MEMRES0 data loaded interrupt

:ADC:INTEVT1BM

Address offset	0x0000 1058
Description	INTERNAL EVENT 1 IRQ MASK Interrupt Mask. If a bit is set, then corresponding interrupt is un-masked. Un-masking the interrupt causes the raw interrupt to be visible in IIDX, as well as MIS.
Type	RW

Bits	Field Name	Description		Type	Reset
31:9	Reserved			RO	0x00 0000
8	MEMRESIFG0	Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		RW	0
		0	CLR No new data ready.
		1	SET A new data is ready to be read.
7:5	Reserved			RO	0x0
4	INIFG	Mask INIFG in MIS_EX register.		RW	0
		0	CLR Interrupt is not pending.
		1	SET Interrupt is pending.
3	LOFG	LOW FG Raw interrupt flag for the MEMRESx result register being below than the WCLOWx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.		RW	0
		0	CLR Interrupt is not pending.
		1	SET Interrupt is pending.
2	HIFG	HIGH FG Raw interrupt flag for the MEMRESx result register being higher than the WCHIx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.		RW	0
		0	CLR Interrupt is not pending.
		1	SET Interrupt is pending.
1:0	Reserved			RO	0x0

:ADC:INTEVT1RIS

Address offset	0x0000 1060
Description	INTERNAL EVENT 1 RAW IRQ STA Raw interrupt status. Reflects all pending interrupts, regardless of masking. The INTEVT1RIS register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the ICLR register bit even if the corresponding IMASK bit is not enabled.
Type	RO

Bits	Field Name	Description		Type	Reset
31:9	Reserved			RO	0x00 0000
8	MEMRESIFG0	Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		RO	0
		Read 0	CLR No new data ready.
		Read 1	SET A new data is ready to be read.
7:5	Reserved			RO	0x0
4	INIFG	Mask INIFG in MIS_EX register.		RO	0
		Read 0	CLR Interrupt is not pending.
		Read 1	SET Interrupt is pending.
3	LOFG	LOW FG Raw interrupt flag for the MEMRESx result register being below than the WCLOWx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.		RO	0
		Read 0	CLR Interrupt is not pending.
		Read 1	SET Interrupt is pending.
2	HIFG	HIGH FG Raw interrupt flag for the MEMRESx result register being higher than the WCHIx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.		RO	0
		Read 0	CLR Interrupt is not pending.
		Read 1	SET Interrupt is pending.
1:0	Reserved			RO	0x0

:ADC:INTEVT1MIS

Address offset	0x0000 1068
Description	INTERNAL EVENT 1 MASKED IRQ STA Masked interrupt status. This is an AND of the IMASK and RIS registers.
Type	RO

Bits	Field Name	Description		Type	Reset
31:9	Reserved			RO	0x00 0000
8	MEMRESIFG0	Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		RO	0
		Read 0	CLR No new data ready.
		Read 1	SET A new data is ready to be read.
7:5	Reserved			RO	0x0
4	INIFG	Mask INIFG in MIS_EX register.		RO	0
		Read 0	CLR Interrupt is not pending.
		Read 1	SET Interrupt is pending.
3	LOFG	LOW FG Raw interrupt flag for the MEMRESx result register being below than the WCLOWx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.		RO	0
		Read 0	CLR Interrupt is not pending.
		Read 1	SET Interrupt is pending.
2	HIFG	HIGH FG Raw interrupt flag for the MEMRESx result register being higher than the WCHIx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.		RO	0
		Read 0	CLR Interrupt is not pending.
		Read 1	SET Interrupt is pending.
1:0	Reserved			RO	0x0

:ADC:INTEVT1SET

Address offset	0x0000 1070
Description	INTERNAL EVENT 1 IRQ SET Interrupt set. Allows interrupts to be set by software (useful in diagnostics and safety checks). Writing a 1 to a bit in INTEVT1SET will set the event and therefore the related RIS bit also gets set. If the interrupt is enabled through the mask, then the corresponding MIS bit is also set.
Type	RW

Bits	Field Name	Description		Type	Reset
31:9	Reserved			RO	0x00 0000
8	MEMRESIFG0	Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		WO	0
		Write 0	NO_EFFECT No new data ready.
		Write 1	SET A new data is ready to be read.
7:5	Reserved			RO	0x0
4	INIFG	Mask INIFG in MIS_EX register.		WO	0
		Write 0	NO_EFFECT Interrupt is not pending.
		Write 1	SET Interrupt is pending.
3	LOFG	LOW FG Raw interrupt flag for the MEMRESx result register being below than the WCLOWx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.		WO	0
		Write 0	NO_EFFECT Interrupt is not pending.
		Write 1	SET Interrupt is pending.
2	HIFG	HIGH FG Raw interrupt flag for the MEMRESx result register being higher than the WCHIx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.		WO	0
		Write 0	NO_EFFECT Interrupt is not pending.
		Write 1	SET Interrupt is pending.
1:0	Reserved			RO	0x0

:ADC:INTEVT1CLR

Address offset	0x0000 1078
Description	INTERNAL EVENT 1 IRQ CLEAR Interrupt clear. Write a 1 to clear corresponding Interrupt.
Type	RW

Bits	Field Name	Description		Type	Reset
31:9	Reserved			RO	0x00 0000
8	MEMRESIFG0	Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		WO	0
		Write 0	NO_EFFECT No new data ready.
		Write 1	CLR A new data is ready to be read.
7:5	Reserved			RO	0x0
4	INIFG	Mask INIFG in MIS_EX register.		WO	0
		Write 0	NO_EFFECT Interrupt is not pending.
		Write 1	CLR Interrupt is pending.
3	LOFG	LOW FG Raw interrupt flag for the MEMRESx result register being below than the WCLOWx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.		WO	0
		Write 0	NO_EFFECT Interrupt is not pending.
		Write 1	CLR Interrupt is pending.
2	HIFG	HIGH FG Raw interrupt flag for the MEMRESx result register being higher than the WCHIx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.		WO	0
		Write 0	NO_EFFECT Interrupt is not pending.
		Write 1	CLR Interrupt is pending.
1:0	Reserved			RO	0x0

:ADC:INTEVT2IDX

Address offset	0x0000 1080
Description	INTERNAL EVENT 2 IRQ IDX This register provides the highest priority enabled interrupt index. 0x0 means no event pending. Interrupt 1 is the highest priority, 2 next highest, 4, 8, ... 2^31 is the least priority. That is, the least bit position that is set to 1 denotes the highest priority pending interrupt. The priority order is fixed. However, users can implement their own prioritization schemes using other registers that expose the full set of interrupts that have occurred. On each read, only one interrupt is indicated. On a read, the current interrupt (highest priority) is automatically cleared by the hardware and the corresponding interrupt flag in the RIS and MIS are cleared as well. After a read from the CPU (not from the debug interface), the register must be updated with the next highest priority interrupt, if none are pending, then it should display 0x0.
Type	RO

Bits	Field Name	Description		Type	Reset
31:10	Reserved			RO	0x00 0000
9:0	STAT	Interrupt index status		RO	0x000
		Read 0x000	NO_INTR No bit is set means there is no pending interrupt request
		Read 0x009	MEMRESIFG0 MEMRES0 data loaded interrupt
		Read 0x00A	MEMRESIFG1 MEMRES1 data loaded interrupt
		Read 0x00B	MEMRESIFG2 MEMRES2 data loaded interrupt
		Read 0x00C	MEMRESIFG3 MEMRES3 data loaded interrupt
		Read 0x00D	MEMRESIFG4 MEMRES4 data loaded interrupt
		Read 0x00E	MEMRESIFG5 MEMRES5 data loaded interrupt
		Read 0x00F	MEMRESIFG6 MEMRES6 data loaded interrupt
		Read 0x010	MEMRESIFG7 MEMRES7 data loaded interrupt
		Read 0x011	MEMRESIFG8 MEMRES8 data loaded interrupt
		Read 0x012	MEMRESIFG9 MEMRES9 data loaded interrupt
		Read 0x013	MEMRESIFG10 MEMRES10 data loaded interrupt
		Read 0x014	MEMRESIFG11 MEMRES11 data loaded interrupt
		Read 0x015	MEMRESIFG12 MEMRES12 data loaded interrupt
		Read 0x016	MEMRESIFG13 MEMRES13 data loaded interrupt
		Read 0x017	MEMRESIFG14 MEMRES14 data loaded interrupt
		Read 0x018	MEMRESIFG15 MEMRES15 data loaded interrupt
		Read 0x019	MEMRESIFG16 MEMRES16 data loaded interrupt
		Read 0x01A	MEMRESIFG17 MEMRES17 data loaded interrupt
		Read 0x01B	MEMRESIFG18 MEMRES18 data loaded interrupt
		Read 0x01C	MEMRESIFG19 MEMRES19 data loaded interrupt
		Read 0x01D	MEMRESIFG20 MEMRES20 data loaded interrupt
		Read 0x01E	MEMRESIFG21 MEMRES21 data loaded interrupt
		Read 0x01F	MEMRESIFG22 MEMRES22 data loaded interrupt
		Read 0x020	MEMRESIFG23 MEMRES23 data loaded interrupt

:ADC:INTEVT2BM

Address offset	0x0000 1088
Description	INTERNAL EVENT 2 IRQ MASK Interrupt Mask. If a bit is set, then corresponding interrupt is un-masked. Un-masking the interrupt causes the raw interrupt to be visible in IIDX, as well as MIS.
Type	RW

Bits	Field Name	Description		Type	Reset
31:24	Reserved			RO	0x00
23	MEMRESIFG15	Raw interrupt status for MEMRES15. This bit is set to 1 when MEMRES15 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		RW	0
		0	CLR No new data ready.
		1	SET A new data is ready to be read.
22	MEMRESIFG14	Raw interrupt status for MEMRES14. This bit is set to 1 when MEMRES14 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		RW	0
		0	CLR No new data ready.
		1	SET A new data is ready to be read.
21	MEMRESIFG13	Raw interrupt status for MEMRES13. This bit is set to 1 when MEMRES13 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		RW	0
		0	CLR No new data ready.
		1	SET A new data is ready to be read.
20	MEMRESIFG12	Raw interrupt status for MEMRES12. This bit is set to 1 when MEMRES12 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		RW	0
		0	CLR No new data ready.
		1	SET A new data is ready to be read.
19	MEMRESIFG11	Raw interrupt status for MEMRES11. This bit is set to 1 when MEMRES11 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		RW	0
		0	CLR No new data ready.
		1	SET A new data is ready to be read.
18	MEMRESIFG10	Raw interrupt status for MEMRES10. This bit is set to 1 when MEMRES10 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		RW	0
		0	CLR No new data ready.
		1	SET A new data is ready to be read.
17	MEMRESIFG9	Raw interrupt status for MEMRES9. This bit is set to 1 when MEMRES9 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		RW	0
		0	CLR No new data ready.
		1	SET A new data is ready to be read.
16	MEMRESIFG8	Raw interrupt status for MEMRES8. This bit is set to 1 when MEMRES8 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		RW	0
		0	CLR No new data ready.
		1	SET A new data is ready to be read.
15	MEMRESIFG7	Raw interrupt status for MEMRES7. This bit is set to 1 when MEMRES7 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		RW	0
		0	CLR No new data ready.
		1	SET A new data is ready to be read.
14	MEMRESIFG6	Raw interrupt status for MEMRES6. This bit is set to 1 when MEMRES6 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		RW	0
		0	CLR No new data ready.
		1	SET A new data is ready to be read.
13	MEMRESIFG5	Raw interrupt status for MEMRES5. This bit is set to 1 when MEMRES5 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		RW	0
		0	CLR No new data ready.
		1	SET A new data is ready to be read.
12	MEMRESIFG4	Raw interrupt status for MEMRES4. This bit is set to 1 when MEMRES4 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		RW	0
		0	CLR No new data ready.
		1	SET A new data is ready to be read.
11	MEMRESIFG3	Raw interrupt status for MEMRES3. This bit is set to 1 when MEMRES3 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		RW	0
		0	CLR No new data ready.
		1	SET A new data is ready to be read.
10	MEMRESIFG2	Raw interrupt status for MEMRES2. This bit is set to 1 when MEMRES2 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		RW	0
		0	CLR No new data ready.
		1	SET A new data is ready to be read.
9	MEMRESIFG1	Raw interrupt status for MEMRES1. This bit is set to 1 when MEMRES1 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		RW	0
		0	CLR No new data ready.
		1	SET A new data is ready to be read.
8	MEMRESIFG0	Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		RW	0
		0	CLR No new data ready.
		1	SET A new data is ready to be read.
7:0	Reserved			RO	0x00

:ADC:INTEVT2RIS

Address offset	0x0000 1090
Description	INTERNAL EVENT 2 RAW IRQ STA Raw interrupt status. Reflects all pending interrupts, regardless of masking. The INTEVT2RIS register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the ICLR register bit even if the corresponding IMASK bit is not enabled.
Type	RO

Bits	Field Name	Description		Type	Reset
31:24	Reserved			RO	0x00
23	MEMRESIFG15	Raw interrupt status for MEMRES15. This bit is set to 1 when MEMRES15 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		RO	0
		Read 0	CLR No new data ready.
		Read 1	SET A new data is ready to be read.
22	MEMRESIFG14	Raw interrupt status for MEMRES14. This bit is set to 1 when MEMRES14 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		RO	0
		Read 0	CLR No new data ready.
		Read 1	SET A new data is ready to be read.
21	MEMRESIFG13	Raw interrupt status for MEMRES13. This bit is set to 1 when MEMRES13 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		RO	0
		Read 0	CLR No new data ready.
		Read 1	SET A new data is ready to be read.
20	MEMRESIFG12	Raw interrupt status for MEMRES12. This bit is set to 1 when MEMRES12 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		RO	0
		Read 0	CLR No new data ready.
		Read 1	SET A new data is ready to be read.
19	MEMRESIFG11	Raw interrupt status for MEMRES11. This bit is set to 1 when MEMRES11 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		RO	0
		Read 0	CLR No new data ready.
		Read 1	SET A new data is ready to be read.
18	MEMRESIFG10	Raw interrupt status for MEMRES10. This bit is set to 1 when MEMRES10 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		RO	0
		Read 0	CLR No new data ready.
		Read 1	SET A new data is ready to be read.
17	MEMRESIFG9	Raw interrupt status for MEMRES9. This bit is set to 1 when MEMRES9 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		RO	0
		Read 0	CLR No new data ready.
		Read 1	SET A new data is ready to be read.
16	MEMRESIFG8	Raw interrupt status for MEMRES8. This bit is set to 1 when MEMRES8 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		RO	0
		Read 0	CLR No new data ready.
		Read 1	SET A new data is ready to be read.
15	MEMRESIFG7	Raw interrupt status for MEMRES7. This bit is set to 1 when MEMRES7 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		RO	0
		Read 0	CLR No new data ready.
		Read 1	SET A new data is ready to be read.
14	MEMRESIFG6	Raw interrupt status for MEMRES6. This bit is set to 1 when MEMRES6 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		RO	0
		Read 0	CLR No new data ready.
		Read 1	SET A new data is ready to be read.
13	MEMRESIFG5	Raw interrupt status for MEMRES5. This bit is set to 1 when MEMRES5 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		RO	0
		Read 0	CLR No new data ready.
		Read 1	SET A new data is ready to be read.
12	MEMRESIFG4	Raw interrupt status for MEMRES4. This bit is set to 1 when MEMRES4 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		RO	0
		Read 0	CLR No new data ready.
		Read 1	SET A new data is ready to be read.
11	MEMRESIFG3	Raw interrupt status for MEMRES3. This bit is set to 1 when MEMRES3 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		RO	0
		Read 0	CLR No new data ready.
		Read 1	SET A new data is ready to be read.
10	MEMRESIFG2	Raw interrupt status for MEMRES2. This bit is set to 1 when MEMRES2 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		RO	0
		Read 0	CLR No new data ready.
		Read 1	SET A new data is ready to be read.
9	MEMRESIFG1	Raw interrupt status for MEMRES1. This bit is set to 1 when MEMRES1 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		RO	0
		Read 0	CLR No new data ready.
		Read 1	SET A new data is ready to be read.
8	MEMRESIFG0	Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		RO	0
		Read 0	CLR No new data ready.
		Read 1	SET A new data is ready to be read.
7:0	Reserved			RO	0x00

:ADC:INTEVT2MIS

Address offset	0x0000 1098
Description	INTERNAL EVENT 2 MASKED IRQ STA Extension of Masked interrupt status. This is an AND of the IMASK and RIS registers.
Type	RO

Bits	Field Name	Description		Type	Reset
31:24	Reserved			RO	0x00
23	MEMRESIFG15	Raw interrupt status for MEMRES15. This bit is set to 1 when MEMRES15 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		RO	0
		Read 0	CLR No new data ready.
		Read 1	SET A new data is ready to be read.
22	MEMRESIFG14	Raw interrupt status for MEMRES14. This bit is set to 1 when MEMRES14 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		RO	0
		Read 0	CLR No new data ready.
		Read 1	SET A new data is ready to be read.
21	MEMRESIFG13	Raw interrupt status for MEMRES13. This bit is set to 1 when MEMRES13 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		RO	0
		Read 0	CLR No new data ready.
		Read 1	SET A new data is ready to be read.
20	MEMRESIFG12	Raw interrupt status for MEMRES12. This bit is set to 1 when MEMRES12 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		RO	0
		Read 0	CLR No new data ready.
		Read 1	SET A new data is ready to be read.
19	MEMRESIFG11	Raw interrupt status for MEMRES11. This bit is set to 1 when MEMRES11 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		RO	0
		Read 0	CLR No new data ready.
		Read 1	SET A new data is ready to be read.
18	MEMRESIFG10	Raw interrupt status for MEMRES10. This bit is set to 1 when MEMRES10 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		RO	0
		Read 0	CLR No new data ready.
		Read 1	SET A new data is ready to be read.
17	MEMRESIFG9	Raw interrupt status for MEMRES9. This bit is set to 1 when MEMRES9 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		RO	0
		Read 0	CLR No new data ready.
		Read 1	SET A new data is ready to be read.
16	MEMRESIFG8	Raw interrupt status for MEMRES8. This bit is set to 1 when MEMRES8 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		RO	0
		Read 0	CLR No new data ready.
		Read 1	SET A new data is ready to be read.
15	MEMRESIFG7	Raw interrupt status for MEMRES7. This bit is set to 1 when MEMRES7 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		RO	0
		Read 0	CLR No new data ready.
		Read 1	SET A new data is ready to be read.
14	MEMRESIFG6	Raw interrupt status for MEMRES6. This bit is set to 1 when MEMRES6 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		RO	0
		Read 0	CLR No new data ready.
		Read 1	SET A new data is ready to be read.
13	MEMRESIFG5	Raw interrupt status for MEMRES5. This bit is set to 1 when MEMRES5 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		RO	0
		Read 0	CLR No new data ready.
		Read 1	SET A new data is ready to be read.
12	MEMRESIFG4	Raw interrupt status for MEMRES4. This bit is set to 1 when MEMRES4 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		RO	0
		Read 0	CLR No new data ready.
		Read 1	SET A new data is ready to be read.
11	MEMRESIFG3	Raw interrupt status for MEMRES3. This bit is set to 1 when MEMRES3 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		RO	0
		Read 0	CLR No new data ready.
		Read 1	SET A new data is ready to be read.
10	MEMRESIFG2	Raw interrupt status for MEMRES2. This bit is set to 1 when MEMRES2 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		RO	0
		Read 0	CLR No new data ready.
		Read 1	SET A new data is ready to be read.
9	MEMRESIFG1	Raw interrupt status for MEMRES1. This bit is set to 1 when MEMRES1 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		RO	0
		Read 0	CLR No new data ready.
		Read 1	SET A new data is ready to be read.
8	MEMRESIFG0	Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		RO	0
		Read 0	CLR No new data ready.
		Read 1	SET A new data is ready to be read.
7:0	Reserved			RO	0x00

:ADC:INTEVT2SET

Address offset	0x0000 10A0
Description	INTERNAL EVENT 2 IRQ SET Interrupt set. Allows interrupts to be set by software (useful in diagnostics and safety checks). Writing a 1 to a bit in INTEVT2SET will set the event and therefore the related RIS bit also gets set. If the interrupt is enabled through the mask, then the corresponding MIS bit is also set.
Type	RW

Bits	Field Name	Description		Type	Reset
31:24	Reserved			RO	0x00
23	MEMRESIFG15	Raw interrupt status for MEMRES15. This bit is set to 1 when MEMRES15 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		WO	0
		Write 0	NO_EFFECT No new data ready.
		Write 1	SET A new data is ready to be read.
22	MEMRESIFG14	Raw interrupt status for MEMRES14. This bit is set to 1 when MEMRES14 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		WO	0
		Write 0	NO_EFFECT No new data ready.
		Write 1	SET A new data is ready to be read.
21	MEMRESIFG13	Raw interrupt status for MEMRES13. This bit is set to 1 when MEMRES13 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		WO	0
		Write 0	NO_EFFECT No new data ready.
		Write 1	SET A new data is ready to be read.
20	MEMRESIFG12	Raw interrupt status for MEMRES12. This bit is set to 1 when MEMRES12 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		WO	0
		Write 0	NO_EFFECT No new data ready.
		Write 1	SET A new data is ready to be read.
19	MEMRESIFG11	Raw interrupt status for MEMRES11. This bit is set to 1 when MEMRES11 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		WO	0
		Write 0	NO_EFFECT No new data ready.
		Write 1	SET A new data is ready to be read.
18	MEMRESIFG10	Raw interrupt status for MEMRES10. This bit is set to 1 when MEMRES10 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		WO	0
		Write 0	NO_EFFECT No new data ready.
		Write 1	SET A new data is ready to be read.
17	MEMRESIFG9	Raw interrupt status for MEMRES9. This bit is set to 1 when MEMRES9 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		WO	0
		Write 0	NO_EFFECT No new data ready.
		Write 1	SET A new data is ready to be read.
16	MEMRESIFG8	Raw interrupt status for MEMRES8. This bit is set to 1 when MEMRES8 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		WO	0
		Write 0	NO_EFFECT No new data ready.
		Write 1	SET A new data is ready to be read.
15	MEMRESIFG7	Raw interrupt status for MEMRES7. This bit is set to 1 when MEMRES7 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		WO	0
		Write 0	NO_EFFECT No new data ready.
		Write 1	SET A new data is ready to be read.
14	MEMRESIFG6	Raw interrupt status for MEMRES6. This bit is set to 1 when MEMRES6 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		WO	0
		Write 0	NO_EFFECT No new data ready.
		Write 1	SET A new data is ready to be read.
13	MEMRESIFG5	Raw interrupt status for MEMRES5. This bit is set to 1 when MEMRES5 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		WO	0
		Write 0	NO_EFFECT No new data ready.
		Write 1	SET A new data is ready to be read.
12	MEMRESIFG4	Raw interrupt status for MEMRES4. This bit is set to 1 when MEMRES4 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		WO	0
		Write 0	NO_EFFECT No new data ready.
		Write 1	SET A new data is ready to be read.
11	MEMRESIFG3	Raw interrupt status for MEMRES3. This bit is set to 1 when MEMRES3 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		WO	0
		Write 0	NO_EFFECT No new data ready.
		Write 1	SET A new data is ready to be read.
10	MEMRESIFG2	Raw interrupt status for MEMRES2. This bit is set to 1 when MEMRES2 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		WO	0
		Write 0	NO_EFFECT No new data ready.
		Write 1	SET A new data is ready to be read.
9	MEMRESIFG1	Raw interrupt status for MEMRES1. This bit is set to 1 when MEMRES1 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		WO	0
		Write 0	NO_EFFECT No new data ready.
		Write 1	SET A new data is ready to be read.
8	MEMRESIFG0	Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		WO	0
		Write 0	NO_EFFECT No new data ready.
		Write 1	SET A new data is ready to be read.
7:0	Reserved			RO	0x00

:ADC:INTEVT2CLR

Address offset	0x0000 10A8
Description	INTERNAL EVENT 2 IRQ CLEAR Interrupt clear. Write a 1 to clear corresponding Interrupt.
Type	RW

Bits	Field Name	Description		Type	Reset
31:24	Reserved			RO	0x00
23	MEMRESIFG15	Raw interrupt status for MEMRES15. This bit is set to 1 when MEMRES15 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		WO	0
		Write 0	NO_EFFECT No new data ready.
		Write 1	CLR A new data is ready to be read.
22	MEMRESIFG14	Raw interrupt status for MEMRES14. This bit is set to 1 when MEMRES14 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		WO	0
		Write 0	NO_EFFECT No new data ready.
		Write 1	CLR A new data is ready to be read.
21	MEMRESIFG13	Raw interrupt status for MEMRES13. This bit is set to 1 when MEMRES13 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		WO	0
		Write 0	NO_EFFECT No new data ready.
		Write 1	CLR A new data is ready to be read.
20	MEMRESIFG12	Raw interrupt status for MEMRES12. This bit is set to 1 when MEMRES12 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		WO	0
		Write 0	NO_EFFECT No new data ready.
		Write 1	CLR A new data is ready to be read.
19	MEMRESIFG11	Raw interrupt status for MEMRES11. This bit is set to 1 when MEMRES11 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		WO	0
		Write 0	NO_EFFECT No new data ready.
		Write 1	CLR A new data is ready to be read.
18	MEMRESIFG10	Raw interrupt status for MEMRES10. This bit is set to 1 when MEMRES10 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		WO	0
		Write 0	NO_EFFECT No new data ready.
		Write 1	CLR A new data is ready to be read.
17	MEMRESIFG9	Raw interrupt status for MEMRES9. This bit is set to 1 when MEMRES9 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		WO	0
		Write 0	NO_EFFECT No new data ready.
		Write 1	CLR A new data is ready to be read.
16	MEMRESIFG8	Raw interrupt status for MEMRES8. This bit is set to 1 when MEMRES8 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		WO	0
		Write 0	NO_EFFECT No new data ready.
		Write 1	CLR A new data is ready to be read.
15	MEMRESIFG7	Raw interrupt status for MEMRES7. This bit is set to 1 when MEMRES7 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		WO	0
		Write 0	NO_EFFECT No new data ready.
		Write 1	CLR A new data is ready to be read.
14	MEMRESIFG6	Raw interrupt status for MEMRES6. This bit is set to 1 when MEMRES6 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		WO	0
		Write 0	NO_EFFECT No new data ready.
		Write 1	CLR A new data is ready to be read.
13	MEMRESIFG5	Raw interrupt status for MEMRES5. This bit is set to 1 when MEMRES5 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		WO	0
		Write 0	NO_EFFECT No new data ready.
		Write 1	CLR A new data is ready to be read.
12	MEMRESIFG4	Raw interrupt status for MEMRES4. This bit is set to 1 when MEMRES4 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		WO	0
		Write 0	NO_EFFECT No new data ready.
		Write 1	CLR A new data is ready to be read.
11	MEMRESIFG3	Raw interrupt status for MEMRES3. This bit is set to 1 when MEMRES3 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		WO	0
		Write 0	NO_EFFECT No new data ready.
		Write 1	CLR A new data is ready to be read.
10	MEMRESIFG2	Raw interrupt status for MEMRES2. This bit is set to 1 when MEMRES2 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		WO	0
		Write 0	NO_EFFECT No new data ready.
		Write 1	CLR A new data is ready to be read.
9	MEMRESIFG1	Raw interrupt status for MEMRES1. This bit is set to 1 when MEMRES1 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		WO	0
		Write 0	NO_EFFECT No new data ready.
		Write 1	CLR A new data is ready to be read.
8	MEMRESIFG0	Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1		WO	0
		Write 0	NO_EFFECT No new data ready.
		Write 1	CLR A new data is ready to be read.
7:0	Reserved			RO	0x00

:ADC:EVTMOD

Address offset	0x0000 10E0
Description	EVENT MOD Event mode register. It is used to select whether each line is disabled, in software mode (software clears the RIS) or in hardware mode (hardware clears the RIS)
Type	RW

Bits	Field Name	Description		Type	Reset
31:4	Reserved			RO	0x000 0000
3:2	EVT1CFG	EVENT 1 CONFIG Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT1]		RW	0x2
		0x0	DISABLE The interrupt or event line is disabled.
		0x1	SOFTWARE The interrupt or event line is in software mode. Software must clear the RIS.
		0x2	HARDWARE The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag.
1:0	INT0CFG	INTERNAL 0 CONFIG Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT0]		RW	0x1
		0x0	DISABLE The interrupt or event line is disabled.
		0x1	SOFTWARE The interrupt or event line is in software mode. Software must clear the RIS.
		0x2	HARDWARE The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag.

:ADC:DESC

Address offset	0x0000 10FC
Description	This register identifies the peripheral and its exact version.
Type	RO

Bits	Field Name	Description		Type	Reset
31:16	MODULEID	Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness.		RO	0x2611
		Read 0x0000	MINIMUM Smallest value
		Read 0xFFFF	MAXIMUM Highest possible value
15:12	FEATUREVER	Feature Set for the module instance		RO	0x0
		Read 0x0	MINIMUM Smallest value
		Read 0xF	MAXIMUM Highest possible value
11:8	INSTNUM	Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances		RO	0x0
7:4	MAJREV	Major rev of the IP		RO	0x1
		Read 0x0	MINIMUM Smallest value
		Read 0xF	MAXIMUM Highest possible value
3:0	MINREV	Minor rev of the IP		RO	0x0
		Read 0x0	MINIMUM Smallest value
		Read 0xF	MAXIMUM Highest possible value

:ADC:CTL0

Address offset	0x0000 1100
Description	ULP_ADCHP Control Register 0
Type	RW

Bits	Field Name	Description		Type	Reset
31:27	Reserved			RO	0x00
26:24	SCLKDIV	NU - should keep as '0'. Selects divide ratio of of sample clock.		RW	0x0
		0x0	DIV_BY_1 Do not divide clock source
		0x1	DIV_BY_2 Divide clock source by 2
		0x2	DIV_BY_4 Divide clock source by 3
		0x3	DIV_BY_8 Divide clock source by 4
		0x4	DIV_BY_16 Divide clock source by 5
		0x5	DIV_BY_24 Divide clock source by 6
		0x6	DIV_BY_32 Divide clock source by 7
		0x7	DIV_BY_48 Divide clock source by 8
23:17	Reserved			RO	0x00
16	PWRDN	Auto or manual power down mode.		RW	0
		0	AUTO ADC is powered down on completion of a conversion, if there isn't a pending trigger.
		1	MANUAL ADC is kept powered up as long as ADCEN bit is set.
15:1	Reserved			RO	0x0000
0	ENC	ULP_ADCHP Enable Conversions.		RW	0
		0	OFF ULP_ADCHP primary sequencer is off Transition from ON to OFF will abort the primary single or repeat sequence on a MEMCTLx boundary. (The current conversion will finish and result stored in corresponding MEMRESx)
		1	ON ULP_ADCHP primary sequencer is ON. Waiting for valid trigger (Software or Hardware)

:ADC:CTL1

Address offset	0x0000 1104
Description	Primary Sequence Control Register
Type	RW

Bits	Field Name	Description		Type	Reset
31	Reserved			RO	0
30:28	AVGD	Hardware average denominator. The number to divide the accumulated value by (this is a shift). Note results register is maximum of 16-bits long so if not shifted appropriately result will be truncated.		RW	0x0
		0x0	SHIFT0 0 bit shift
		0x1	SHIFT1 1 bit shift
		0x2	SHIFT2 2 bit shift
		0x3	SHIFT3 3 bit shift
		0x4	SHIFT4 4 bit shift
		0x5	SHIFT5 5 bit shift
		0x6	SHIFT6 6 bit shift
		0x7	SHIFT7 7 bit shift
27	Reserved			RO	0
26:24	AVGN	Hardware averager numerator. Selects number of conversions to accumulate for current MEMCTLx and then is get divided by AVGD. Result will be stored in MEMRESx.		RW	0x0
		0x0	DISABLE Disables averager.
		0x1	AVG_2 Averages 2 conversions before storing in MEMRES register.
		0x2	AVG_4 Averages 4 conversions before storing in MEMRES register.
		0x3	AVG_8 Averages 8 conversions before storing in MEMRES register.
		0x4	AVG_16 Averages 16 conversions before storing in MEMRES register.
		0x5	AVG_32 Averages 32 conversions before storing in MEMRES register.
		0x6	AVG_64 Averages 64 conversions before storing in MEMRES register.
		0x7	AVG_128 Averages 128 conversions before storing in MEMRES register.
23:21	Reserved			RO	0x0
20	SAMPMOD	ULP_ADCHP Primary Sequencer Sample Mode. This bit select the source of the sampling signal.		RW	0
		0	AUTO The sample timer high phase is used as sample signal.
		1	MANUAL The external or software trigger is used as sample signal.
19:18	Reserved			RO	0x0
17:16	CONSEQ	ULP_ADCHP Primary Sequencer Conversion Sequence Mode Select.		RW	0x0
		0x0	SINGLE The MEMCTLx pointed by PSTARTADD will be converted once.
		0x1	SEQUENCE The primary sequence pointed by PSTARTADD will be converted once.
		0x2	REPEATSINGLE The MEMCTLx pointed by PSTARTADD will be converted in repeat mode.
		0x3	REPEATSEQUENCE Primary sequence pointed by PSTARTADD will be converted in repeat mode.
15:9	Reserved			RO	0x00
8	SC	ULP_ADCHP Sequencer Start Of Conversion. If ULP_ADCHP is configured as FOLLOWER, this bit has no effect.		RW	0
		0	STOP When PSAMPMOD is set to MANUAL (1) mode, clearing this bit will end the sampling phase and the conversion phase will start. When PSAMPMOD is set to AUTO mode (0), writing 0 has no effect. This bit is automatically cleared at the end of the current conversion.
		1	START When PSAMPMOD is set to MANUAL (1), setting this bit, will start the sampling phase. Sample phase will last as long as this bit is set. When PSAMPMOD is set to AUTO mode (0), setting this bit will trigger the timer based sample time.
7:1	Reserved			RO	0x00
0	TRIGSRC	ULP_ADCHP Primary Sequence Trigger Source.		RW	0
		0	SOFTWARE Primary sequence or single conversion is triggered by software.
		1	EVENT Primary sequence or single conversion is triggered by hardware event_0. (See device specific data-sheet for source for availability of this trigger)

:ADC:CTL2

Address offset	0x0000 1108
Description	Primary Sequence Control Register
Type	RW

Bits	Field Name	Description		Type	Reset
31:29	Reserved			RO	0x0
28:24	ENDADD	ULP_ADCHP Primary Sequence End Address. These bits select which MEMCTLx is the last MEMCTL for primary sequence mode. The value of PSTARTADD is 0x00 to 0x1F, corresponding to MEMRES0 to MEMRES31.		RW	0x00
		0x00	ADDR_00 MEMCTL0 is selected as end address of primary sequence.
		0x01	ADDR_01 MEMCTL1 is selected as end address of primary sequence.
		0x02	ADDR_02 MEMCTL2 is selected as end address of primary sequence.
		0x03	ADDR_03 MEMCTL3 is selected as end address of primary sequence.
		0x04	ADDR_04 MEMCTL4 is selected as end address of primary sequence.
		0x05	ADDR_05 MEMCTL5 is selected as end address of primary sequence.
		0x06	ADDR_06 MEMCTL6 is selected as end address of primary sequence.
		0x07	ADDR_07 MEMCTL7 is selected as end address of primary sequence.
		0x08	ADDR_08 MEMCTL8 is selected as end address of primary sequence.
		0x09	ADDR_09 MEMCTL9 is selected as end address of primary sequence.
		0x0A	ADDR_10 MEMCTL10 is selected as end address of primary sequence.
		0x0B	ADDR_11 MEMCTL11 is selected as end address of primary sequence.
		0x0C	ADDR_12 MEMCTL12 is selected as end address of primary sequence.
		0x0D	ADDR_13 MEMCTL13 is selected as end address of primary sequence.
		0x0E	ADDR_14 MEMCTL14 is selected as end address of primary sequence.
		0x0F	ADDR_15 MEMCTL15 is selected as end address of primary sequence.
		0x10	ADDR_16 MEMCTL16 is selected as end address of primary sequence.
		0x11	ADDR_17 MEMCTL17 is selected as end address of primary sequence.
		0x12	ADDR_18 MEMCTL18 is selected as end address of primary sequence.
		0x13	ADDR_19 MEMCTL19 is selected as end address of primary sequence.
		0x14	ADDR_20 MEMCTL20 is selected as end address of primary sequence.
		0x15	ADDR_21 MEMCTL21 is selected as end address of primary sequence.
		0x16	ADDR_22 MEMCTL22 is selected as end address of primary sequence.
		0x17	ADDR_23 MEMCTL23 is selected as end address of primary sequence.
		0x18	ADDR_24 MEMCTL24 is selected as end address of primary sequence.
		0x19	ADDR_25 MEMCTL25 is selected as end address of primary sequence.
		0x1A	ADDR_26 MEMCTL26 is selected as end address of primary sequence.
		0x1B	ADDR_27 MEMCTL27 is selected as end address of primary sequence.
		0x1C	ADDR_28 MEMCTL28 is selected as end address of primary sequence.
		0x1D	ADDR_29 MEMCTL29 is selected as end address of primary sequence.
		0x1E	ADDR_30 MEMCTL30 is selected as end address of primary sequence.
		0x1F	ADDR_31 MEMCTL31 is selected as end address of primary sequence.
23:21	Reserved			RO	0x0
20:16	STARTADD	ULP_ADCHP Primary Sequence Start Address. These bits select which MEMCTLx is used for single conversion or as first MEMCTL for primary sequence mode. The value of PSTARTADD is 0x00 to 0x1F, corresponding to MEMRES0 to MEMRES31.		RW	0x00
		0x00	ADDR_00 MEMCTL0 is selected as start address of a primary sequence or as a single conversion.
		0x01	ADDR_01 MEMCTL1 is selected as start address of a primary sequence or as a single conversion.
		0x02	ADDR_02 MEMCTL2 is selected as start address of a primary sequence or as a single conversion.
		0x03	ADDR_03 MEMCTL3 is selected as start address of a primary sequence or as a single conversion.
		0x04	ADDR_04 MEMCTL4 is selected as start address of a primary sequence or as a single conversion.
		0x05	ADDR_05 MEMCTL5 is selected as start address of a primary sequence or as a single conversion.
		0x06	ADDR_06 MEMCTL6 is selected as start address of a primary sequence or as a single conversion.
		0x07	ADDR_07 MEMCTL7 is selected as start address of a primary sequence or as a single conversion.
		0x08	ADDR_08 MEMCTL8 is selected as start address of a primary sequence or as a single conversion.
		0x09	ADDR_09 MEMCTL9 is selected as start address of a primary sequence or as a single conversion.
		0x0A	ADDR_10 MEMCTL10 is selected as start address of a primary sequence or as a single conversion.
		0x0B	ADDR_11 MEMCTL11 is selected as start address of a primary sequence or as a single conversion.
		0x0C	ADDR_12 MEMCTL12 is selected as start address of a primary sequence or as a single conversion.
		0x0D	ADDR_13 MEMCTL13 is selected as start address of a primary sequence or as a single conversion.
		0x0E	ADDR_14 MEMCTL14 is selected as start address of a primary sequence or as a single conversion.
		0x0F	ADDR_15 MEMCTL15 is selected as start address of a primary sequence or as a single conversion.
		0x10	ADDR_16 MEMCTL16 is selected as start address of a primary sequence or as a single conversion.
		0x11	ADDR_17 MEMCTL17 is selected as start address of a primary sequence or as a single conversion.
		0x12	ADDR_18 MEMCTL18 is selected as start address of a primary sequence or as a single conversion.
		0x13	ADDR_19 MEMCTL19 is selected as start address of a primary sequence or as a single conversion.
		0x14	ADDR_20 MEMCTL20 is selected as start address of a primary sequence or as a single conversion.
		0x15	ADDR_21 MEMCTL21 is selected as start address of a primary sequence or as a single conversion.
		0x16	ADDR_22 MEMCTL22 is selected as start address of a primary sequence or as a single conversion.
		0x17	ADDR_23 MEMCTL23 is selected as start address of a primary sequence or as a single conversion.
		0x18	ADDR_24 MEMCTL24 is selected as start address of a primary sequence or as a single conversion.
		0x19	ADDR_25 MEMCTL25 is selected as start address of a primary sequence or as a single conversion.
		0x1A	ADDR_26 MEMCTL26 is selected as start address of a primary sequence or as a single conversion.
		0x1B	ADDR_27 MEMCTL27 is selected as start address of a primary sequence or as a single conversion.
		0x1C	ADDR_28 MEMCTL28 is selected as start address of a primary sequence or as a single conversion.
		0x1D	ADDR_29 MEMCTL29 is selected as start address of a primary sequence or as a single conversion.
		0x1E	ADDR_30 MEMCTL30 is selected as start address of a primary sequence or as a single conversion.
		0x1F	ADDR_31 MEMCTL31 is selected as start address of a primary sequence or as a single conversion.
15:11	Reserved			RO	0x00
10	FIFOEN	Enables configuring of MEMRES register in FIFO mode.		RW	0
		0	DISABLE Disabled FIFO mode of operation,
		1	ENABLE Enables FIFO mode of operation.
9	Reserved			RO	0
8	DMAEN	Enable DMA for data transfer.		RW	0
		0	DISABLE DMA triggers are not enabled.
		1	ENABLE Enable DMA.
7:3	Reserved			RO	0x00
2:1	RES	ULP_ADCHP resolution. This bits define the conversion result resolution. Note : A value of 3 defaults to 12 bit resolution.		RW	0x0
		0x0	BIT_12 16-bits resolution
0	DF	ULP_ADCHP data read-back format. Data is always stored in binary unsigned format.		RW	0
		0	UNSIGNED Digital result reads as Binary Unsigned.
		1	SIGNED Digital result reads Signed Binary. (2s complement), left aligned.

:ADC:CTL3

Address offset	0x0000 110C
Description	Control Register 3. This register is used to configure ADC for ad-hoc single conversion.
Type	RW

Bits	Field Name	Description		Type	Reset
31:16	Reserved			RO	0x0000
15	ASCMOD	Single vs Differential		RW	0
14	ASCFSR	Full scale range of ADC limited to 1.8V or 3.3V *Exact range may be limited below the above mentioned voltages based on the design constraints		RW	0
13:12	ASCVRSEL	Selects the voltage reference for ASC operation. VEREFM must be connected to on-board ground when external reference option is selected. Note: Writing value 0x3 defaults to INTREF.		RW	0x0
		0x1	EXTREF EXTREF pin reference.
		0x2	INTREF Internal reference.
11:9	Reserved			RO	0x0
8	ASCSTIME	ASC sample time compare value select. This is used to select between SCOMP0 and SCOMP1 registers for ASC operation.		RW	0
		0	SEL_SCOMP0 Select SCOMP0
		1	SEL_SCOMP1 Select SCOMP1
7:5	Reserved			RO	0x0
4:0	ASCCHSEL	ASC channel select		RW	0x00
		0x00	CHAN_0 Selects channel 0
		0x01	CHAN_1 Selects channel 1
		0x02	CHAN_2 Selects channel 2
		0x03	CHAN_3 Selects channel 3
		0x04	CHAN_4 Selects channel 4
		0x05	CHAN_5 Selects channel 5
		0x06	CHAN_6 Selects channel 6
		0x07	CHAN_7 Selects channel 7
		0x08	CHAN_8 Selects channel 8
		0x09	CHAN_9 Selects channel 9
		0x0A	CHAN_10 Selects channel 10
		0x0B	CHAN_11 Selects channel 11
		0x0C	CHAN_12 Selects channel 12
		0x0D	CHAN_13 Selects channel 13
		0x0E	CHAN_14 Selects channel 14
		0x0F	CHAN_15 Selects channel 15
		0x10	CHAN_16 Selects channel 16
		0x11	CHAN_17 Selects channel 17
		0x12	CHAN_18 Selects channel 18
		0x13	CHAN_19 Selects channel 19
		0x14	CHAN_20 Selects channel 20
		0x15	CHAN_21 Selects channel 21
		0x16	CHAN_22 Selects channel 22
		0x17	CHAN_23 Selects channel 23
		0x18	CHAN_24 Selects channel 24
		0x19	CHAN_25 Selects channel 25
		0x1A	CHAN_26 Selects channel 26
		0x1B	CHAN_27 Selects channel 27
		0x1C	CHAN_28 Selects channel 28
		0x1D	CHAN_29 Selects channel 29
		0x1E	CHAN_30 Selects channel 30
		0x1F	CHAN_31 Selects channel 31

:ADC:CLKFREQ

Address offset	0x0000 1110
Description	ADC sampling clock frequency range register.
Type	RW

Bits	Field Name	Description		Type	Reset
31:3	Reserved			RO	0x0000 0000
2:0	FRANGE	Frequency Range. NU		RW	0x0
		0x0	RANGE1TO4 1 to 4 MHz
		0x1	RANGE4TO8 4 to 8 MHz
		0x2	RANGE8TO16 8 to 16 MHz
		0x3	RANGE16TO20 16 to 20 MHz
		0x4	RANGE20TO24 20 to 24 MHz
		0x5	RANGE24TO32 24 to 32 MHz
		0x6	RANGE32TO40 32 to 40 MHz
		0x7	RANGE40TO48 40 to 48 MHz

:ADC:SCOMP0

Address offset	0x0000 1114
Description	ULP_ADCHP sample time register x Specifies the sample time, in number of ADCCLK cycles, when PSSM = 0 (AUTO) or SSSM = 0 (AUTO). CTL0.ENC must be set to 0 to write to this register.
Type	RW

Bits	Field Name	Description	Type	Reset
31:14	Reserved		RO	0x0 0000
13:0	SMP	SMP This bit-field specify the number of sample time clocks (SCOMPx +1) for a conversion when SMP_TIME in MEMCTLx is set to SCOMPx.	RW	0x0000

:ADC:SCOMP1

Address offset	0x0000 1118
Description	ULP_ADCHP sample time register x Specifies the sample time, in number of ADCCLK cycles, when PSSM = 0 (AUTO) or SSSM = 0 (AUTO). CTL0.ENC must be set to 0 to write to this register.
Type	RW

Bits	Field Name	Description	Type	Reset
31:14	Reserved		RO	0x0 0000
13:0	SMP	SMP This bitfield specify the number of sample time clocks (SCOMPx +1) for a conversion when SMP_TIME in MEMCTLx is set to SCOMPx.	RW	0x0000

:ADC:REFCFG

Address offset	0x0000 111C
Description	REFBUF configuration register
Type	RW

Bits	Field Name	Description		Type	Reset
31:8	Reserved			RO	0x00 0000
7:6	SPAR	SPAR		RW	0x0
5	OSPRPWRDN	OSPREY POWER DOWN Similar to ADC PWRDN control to save power in duty cycled mode of operation. 0 - AUTO, 1 - MANUAL In case of ADC, Sample time MMR needs to take into account time required to power on ADC. Since REF BUF may take time in us, recommendation is to use REFOKf th output oe buffer instead to start ADC conversion		RW	0
4:3	IBPROG	Configures REFBUF IBIAS current output value		RW	0x0
		0x0	VAL0 1uA
		0x1	VAL1 0.5uA
		0x2	VAL2 2uA
		0x3	VAL3 0.67uA
2	IBEN	REFBUF IBIAS enable		RW	0
		0	DISABLE Disable
		1	ENABLE Enable
1	REFVSEL	Configures REFBUF output voltage		RW	0
		0	V1P4 REFBUF generates 1.4V output
0	REFEN	REFBUF enable		RW	0
		0	DISABLE Disable
		1	ENABLE Enable

:ADC:WCLOW

Address offset	0x0000 1148
Description	ULP_ADCHP Window Comparator Low Threshold 0 Register. The data format that is used to write and read WCLOW0 depends on the value of the DATAFORMAT bit in the CTL1 register. If DATAFORMAT = 0, the data is binary unsigned and right aligned. If DATAFORMAT = 1, the data is 2s complement and left aligned. Refer to the WCLOW0 bit-field description for details. CTL0.ENC must be set to 0 to write to this register. Design Note: To minimize cycles transforming data, the data written to WCLOW0 should be transformed into DATAFORMAT = 0 to match the MEMRESx register so a direct comparison can be done. Thus, there are extra cycles to write to this register but no penalty when a comparison is done.
Type	RW

Bits	Field Name	Description	Type	Reset
31:16	Reserved		RO	0x0000
15:0	DATA	Low threshold register 0. If DATAFORMAT = 0, unsigned binary format has to be used: The value based on the resolution has to be right aligned with the MSB on the left. For 14-bits and 12-bits resolution, unused bit have to be 0s Reset value is 0x0000. If DATAFORMAT = 1, 2s-complement format has to be used. The value based on the resolution has to be left aligned with the LSB on the right. For 14-bits and 12-bits resolution, unused bit have to be 0s Reset value is 0x8000.	RW	0x0000

:ADC:WCHI

Address offset	0x0000 1150
Description	WC HIGH ULP_ADCHP Window Comparator High Threshold 0 Register. The data format that is used to write and read WCHI0 depends on the value of the DATAFORMAT bit in the CTL1 register. If DATAFORMAT = 0, the data is binary unsigned and right aligned. If DATAFORMAT = 1, the data is 2s complement and left aligned. Refer to the WCHI0 bit-field description for details. CTL0.ENC must be set to 0 to write to this register. Design Note: To minimize cycles transforming data, the data written to WCHI0 should be transformed in DATAFORMAT = 0 to match the MEMRESx register so a direct comparison can be done. Thus, there are extra cycles to write to this register but no penalty when a comparison is done.
Type	RW

Bits	Field Name	Description	Type	Reset
31:16	Reserved		RO	0x0000
15:0	DATA	ULP_ADCHP Low threshold register 0. If DATAFORMAT = 0, unsigned binary format has to be used: The threshold value has to be right aligned, with the MSB on the left. Reset value are: 0xFFFF (16-bit), 0x3FFF (14-bit) or 0x0FFF (12-bit) If DATAFORMAT = 1, 2s-complement format has to be used. The value based on the resolution has to be left aligned with the LSB on the right. For 14-bits and 12-bits resolution, unused bit have to be 0s Reset value are: 0x7FFF (16-bit), 0x7FFC (14-bit) or 0x7FF0 (12-bit)	RW	0x0000

:ADC:FIFODATA

Address offset	0x0000 1160
Description	Virtual data register used to do a read from FIFO.
Type	RO

Bits	Field Name	Description			Type	Reset
31:0	DATA	Read from data field returns the data from the top of FIFO.			RO	0x0000 0000

:ADC:ASCRES

Address offset	0x0000 1170
Description	ASC result register.
Type	RO

Bits	Field Name	Description	Type	Reset
31:16	Reserved		RO	0x0000
15:0	DATA	Data	RO	0x0000

:ADC:MEMCTL0 - MEMCTL5

Address offset	0x0000 1180-0x0000 1194 in 0x4 byte increments
Description	ULP_ADCHP Conversion Memory Control Register x (x=0 to 31) CTL0.ENC must be set to 0 to write to this register.
Type	RW

Bits	Field Name	Description		Type	Reset
31	Reserved			RO	0
30	MOD	MOD Single vs Differential		RW	0
29	FSR	Full scale range of ADC limited to 1.8V or 3.3V '0' - 3.3V '1' - 1.8V * Exact range may be limited below the above mentioned voltages based on the design constraints		RW	0
28	WINCOMP	Window Comparator Enable. Select for the current conversion if the Window Comparator feature is used.		RW	0
		0	DISABLE Window Comparator is disabled.
		1	ENABLE Window Comparator is enabled.
27:25	Reserved			RO	0x0
24	TRIG	TRIG. Indicates if a trigger will be needed to step to the next MEMCTL in the sequence.		RW	0
		0	AUTO_NEXT Automatically step to next MEMCTL register.
		1	TRIGGER_NEXT A valid trigger will step to next MEMCTL register.
23:17	Reserved			RO	0x00
16	AVGEN	Enable averaging.		RW	0
		0	DISABLE Averaging disabled.
		1	ENABLE Averaging enabled.
15:13	Reserved			RO	0x0
12	STIME	Selects the source of sample timer period. Can choose between SCOMP0 and SCOMP1.		RW	0
		0	SEL_SCOMP0 Select SCOMP0.
		1	SEL_SCOMP1 Select SCOMP1.
11:10	Reserved			RO	0x0
9:8	VRSEL	Selects the combination of V(Rp) and V(Rn) sources. It is recommended to connect VeREFn0 to on-board ground when VeREFn is selected for V(Rn). Note: A value of 3 defaults to INTREF and value of 0 defaults to EXTREF.		RW	0x1
		0x1	EXTREF EXTREF pin reference.
		0x2	INTREF INTREF reference.
7:5	Reserved			RO	0x0
4:0	CHANSEL	ULP_ADCHP Input channel select. In single ended mode, any of the 32 channels can be selected. In differential mode, this field will select which EVEN channel to be connected to the vin+ input. The vin- is automatically set to the next ODD channel. (CHANSEL+1)		RW	0x00
		0x00	CHAN_0 If DIFIN= 0: Ain+ = A0. If DIFIN = 1: Ain+ = A0, Ain- = A1
		0x01	CHAN_1 If DIFIN= 0: Ain+ = A1. If DIFIN = 1: Ain+ = A0, Ain- = A1
		0x02	CHAN_2 If DIFIN = 0: Ain+ = A2. If DIFIN = 1: Ain+ = A2, Ain- = A3
		0x03	CHAN_3 If DIFIN = 0: Ain+ = A3. If DIFIN = 1: Ain+ = A2, Ain- = A3
		0x04	CHAN_4 If DIFIN = 0: Ain+ = A4. If DIFIN = 1: Ain+ = A4, Ain- = A5
		0x05	CHAN_5 If DIFIN = 0: Ain+ = A5. If DIFIN = 1: Ain+ = A4, Ain- = A5
		0x06	CHAN_6 If DIFIN = 0: Ain+ = A6. If DIFIN = 1: Ain+ = A6, Ain- = A7
		0x07	CHAN_7 If DIFIN = 0: Ain+ = A7. If DIFIN = 1: Ain+ = A6, Ain- = A7
		0x08	CHAN_8 If DIFIN = 0: Ain+ = A8. If DIFIN = 1: Ain+ = A8, Ain- = A9
		0x09	CHAN_9 If DIFIN= 0: Ain+ = A9. If DIFIN = 1: Ain+ = A8, Ain- = A9
		0x0A	CHAN_10 If DIFIN= 0: Ain+ = A10. If DIFIN = 1: Ain+ = A10, Ain- = A11
		0x0B	CHAN_11 If DIFIN= 0: Ain+ = A11. If DIFIN = 1: Ain+ = A10, Ain- = A11
		0x0C	CHAN_12 If DIFIN= 0: Ain+ = A12. If DIFIN = 1: Ain+ = A12, Ain- = A13
		0x0D	CHAN_13 If DIFIN= 0: Ain+ = A13. If DIFIN = 1: Ain+ = A12, Ain- = A13
		0x0E	CHAN_14 If DIFIN= 0: Ain+ = A14. If DIFIN = 1: Ain+ = A14, Ain- = A15
		0x0F	CHAN_15 If DIFIN= 0: Ain+ = A15. If DIFIN = 1: Ain+ = A14, Ain- = A15
		0x10	CHAN_16 If DIFIN= 0: Ain+ = A16. If DIFIN = 1: Ain+ = A16, Ain- = A17
		0x11	CHAN_17 If DIFIN= 0: Ain+ = A17. If DIFIN = 1: Ain+ = A16, Ain- = A17
		0x12	CHAN_18 If DIFIN= 0: Ain+ = A18. If DIFIN = 1: Ain+ = A18, Ain- = A19
		0x13	CHAN_19 If DIFIN= 0: Ain+ = A19. If DIFIN = 1: Ain+ = A18, Ain- = A19
		0x14	CHAN_20 If DIFIN= 0: Ain+ = A20. If DIFIN = 1: Ain+ = A20, Ain- = A21
		0x15	CHAN_21 If DIFIN= 0: Ain+ = A21. If DIFIN = 1: Ain+ = A20, Ain- = A21
		0x16	CHAN_22 If DIFIN= 0: Ain+ = A22. If DIFIN = 1: Ain+ = A22, Ain- = A23
		0x17	CHAN_23 If DIFIN= 0: Ain+ = A23. If DIFIN = 1: Ain+ = A22, Ain- = A23
		0x18	CHAN_24 If DIFIN= 0: Ain+ = A24. If DIFIN = 1: Ain+ = A24, Ain- = A25
		0x19	CHAN_25 If DIFIN= 0: Ain+ = A25. If DIFIN = 1: Ain+ = A24, Ain- = A25
		0x1A	CHAN_26 If DIFIN= 0: Ain+ = A26. If DIFIN = 1: Ain+ = A26, Ain- = A27
		0x1B	CHAN_27 If DIFIN= 0: Ain+ = A27. If DIFIN = 1: Ain+ = A26, Ain- = A27
		0x1C	CHAN_28 If DIFIN= 0: Ain+ = A28. If DIFIN = 1: Ain+ = A28, Ain- = A29
		0x1D	CHAN_29 If DIFIN= 0: Ain+ = A29. If DIFIN = 1: Ain+ = A28, Ain- = A29
		0x1E	CHAN_30 If DIFIN= 0: Ain+ = A30. If DIFIN = 1: Ain+ = A30, Ain- = A31
		0x1F	CHAN_31 If DIFIN= 0: Ain+ = A31. If DIFIN = 1: Ain+ = A30, Ain- = A31

:ADC:MEMRES0 - MEMRES15

Address offset	0x0000 1280-0x0000 12BC in 0x4 byte increments
Description	Memory Results Register
Type	RO

Bits	Field Name	Description	Type	Reset
31:16	Reserved		RO	0x0000
15:0	DATA	MEMRESx result register. If DATAFORMAT = 0, unsigned binary: The conversion results are right aligned. In 14 and 12 bit mode, the unused MSB bits are forced to 0. If DATAFORMAT = 1, 2s-complement format: The conversion results are left aligned. In 14 and 12 bit mode, the unused LSB bits are forced to 0. The data is stored in the right-justified format and is converted to the left-justified 2s-complement format during read back. Reading this register clears the corresponding bit in RIS.	RO	0x0000

:ADC:STA

Address offset	0x0000 1340
Description	STA ULP_ADCHP Status Register 0
Type	RO

Bits	Field Name	Description		Type	Reset
31:3	Reserved			RO	0x0000 0000
2	ASCACT	ASC active		RO	0
		Read 0	IDLE Idle or done
		Read 1	ACTIVE ASC active
1	REFBUFRDY	Indicates reference buffer is powered up.		RO	0
		Read 0	NOTREADY REFBUF not ready.
		Read 1	READY REFBUF is ready.
0	BUSY	ULP_ADCHP busy. This bit indicates that an active sample or conversion operation is in progress.		RO	0
		Read 0	IDLE No sampling or conversion in progress.
		Read 1	ACTIVE A sample or conversion is in progress.

:ADC:TEST0

Address offset	0x0000 1E00
Description	Test0 register for ATB Mux sel for ATBBUF and ATBUNBUF
Type	RW

Bits	Field Name	Description	Type	Reset
31	Reserved		RO	0
30	ATBBUFEN	ATB_BUF Enable ADC Signal = ull_dft_atb_usc_ulpadchp_en<1> := 1	RW	0
29	ATBUNBUFEN	ATB_UNBUF Enable ADC Signal = ull_dft_atb_usc_ulpadchp_en<0> := 1	RW	0
28:13	Reserved		RO	0x0000
12:8	AMUNBUFSEL	ATBUNBUF MUX Sel ull_dft_atb_usc_ulpadchp_unbuf_muxsel<4> : Vint REF BUF1 Output ull_dft_atb_usc_ulpadchp_unbuf_muxsel<3> : Vint REF BUF2 Output ull_dft_atb_usc_ulpadchp_unbuf_muxsel<2> : ADC internal VREFN signal ull_dft_atb_usc_ulpadchp_unbuf_muxsel<1> : Not used ull_dft_atb_usc_ulpadchp_unbuf_muxsel<0> : Not used	RW	0x00
7:5	Reserved		RO	0x0
4:0	AMBUFSEL	ATBBUF MUX Sel Bit 4: DIG LDO Output Bit 3: Ana LDO output Bit 2: CM buffer output Bit 1 , and Bit 0 : VDDA3P3 signal	RW	0x00

:ADC:TEST1

Address offset	0x0000 1E04
Description	DTB MUX Selection
Type	RW

Bits	Field Name	Description	Type	Reset
31:5	Reserved		RO	0x000 0000
4:0	DTBMSEL	DTB Mux Sel ull_dft_dtb_usc_ulpadchp_muxsel<0x0> : ADC 16 bit data ull_dft_dtb_usc_ulpadchp_muxsel<0x1> : DTB0: ADC CLK DIV2 DTB1 - 9 : See implementation document for detail signal name.	RW	0x00

:ADC:TEST2

Address offset	0x0000 1E08
Description	ATB Ch sel as ADC input MUX Test mode sel, ATB REF and CAP OSVT enable
Type	RW

Bits	Field Name	Description	Type	Reset
31	CDACOVSTEN	ADC P_CDAC CAP OVST Enable Control Signal ull_usc_ulpadchp_dft_i<31>:1 -> ADC CDAC CAP OVST Enable Control Signal	RW	0
30:25	Reserved		RO	0x00
24	LTRIMEN	Latch trim enable.	RW	0
23:21	Reserved		RO	0x0
20	CMPGNTRIM	COMP GAIN TRIM Resistor Trim Enable Control Signal ull_usc_ulpadchp_dft_i<30>:1 -> Resistor Trim Enable Control Signal	RW	0
19:9	Reserved		RO	0x000
8	MUXTSEL	MUX TEST SELECTOR ADC Input MUX test mode selection: ull_usc_ulpachp_mux_testmode_i<1:0>: 0x01 : Selected Even ch short with ATBBUF CH sel ull_usc_ulpachp_mux_testmode_i<1:0>: 0x10 : Selected Odd ch short with ATBUnBUFCh sel	RW	0
7:0	Reserved		RO	0x00

:ADC:TEST3

Address offset	0x0000 1E0C
Description	ADC CAL Accumulation Register
Type	RW

Bits	Field Name	Description			Type	Reset
31:0	CALACUML	Accumulation of # samples during Calibration step			RW	0x0000 0000

:ADC:TEST4

Address offset	0x0000 1E10
Description	CAL Control register: Average Sample count, Step number, Recall En and Debug option to override ull_usc_ulpadchp_dft_i<26:0>.
Type	RW

Bits	Field Name	Description	Type	Reset
31	HWSTPSELDIS	By Enabling this bit, DLC written value overwritten of ull_usc_ulpadchp_dft_i<26:0> from TEST7 register. This is for debug.	RW	0
30:25	Reserved		RO	0x00
24	CAL_MOD_EN	ADC CDAC Calibration mode enable	RW	0
23:22	Reserved		RO	0x0
21:16	CALSTPSEL	ADC CAL STEP SELECTION	RW	0x00
15:0	Reserved		RO	0x0000

:ADC:TEST5

Address offset	0x0000 1E14
Description	This register updated ull_usc_ulpadchp_dft_i[26:0] value if Test 5: HWSTPSELDIS bit enable
Type	RW

Bits	Field Name	Description	Type	Reset
31:10	Reserved		RO	0x00 0000
9:0	CALCAPCTL	This register updated ull_usc_ulpadchp_dft_i[26:0] value if Test 5: HWSTPSELDIS bit enabled ull_usc_ulpadchp_dft_i[26:0]	RW	0x000

:ADC:TEST6

Address offset	0x0000 1E18
Description	REFBUF ATB selection. This register is used to select the REFBUF signals on ATB.
Type	RW

Bits	Field Name	Description		Type	Reset
31:4	Reserved			RO	0x000 0000
3:0	ATBSEL	ATB selection. The undefined values are reserved and should not be used.		RW	0x0
		0x0	VAL0 Both ATEST0 and ATEST1 switches are open
		0x1	VAL1 REFBUF output (ATEST0/BUF path)
		0x2	VAL2 1st stage output (ATEST0/BUF path)
		0x4	VAL4 Resistor ladder feedback (ATEST0/BUF path)
		0x8	VAL8 1st stage source (ATEST1/UNBUF path)

:ADC:DBG1

Address offset	0x0000 1E20
Description	DBG1 COMP CTL Debug register
Type	RW

Bits	Field Name	Description			Type	Reset
31:0	CTRL	COMP Debug signals control ull_usc_ulpadchp_ctrl_comp_i[31]: Enable the use of external value for comaparor gain and IB settings			RW	0x0080 1000

:ADC:DBG2

Address offset	0x0000 1E24
Description	DEBUG 2 OSC, LATCH_OS, VTOI Debug CTL register
Type	RW

Bits	Field Name	Description	Type	Reset
31:30	Reserved		RO	0x0
29:28	VTOICTL	VTOI Debug Signals control ull_usc_ulpadchp_ctrl_vtoi_i[3:0]	RW	0x0
27:25	Reserved		RO	0x0
24	VTOI_TESTMOD_EN	VTOI TETSMOD Enable	RW	0
23:0	Reserved		RO	0x00 0000

:ADC:DBG3

Address offset	0x0000 1E28
Description	DEBUG 3 Boost, DCLK Sel, Int coex dirty and Dec disable debug control register
Type	RW

Bits	Field Name	Description	Type	Reset
31:6	Reserved		RO	0x000 0000
5	DEC1DIS	DEC1 Disable control signal	RW	0
4	DEC0DIS	DEC0 Disable control signal	RW	0
3:1	Reserved		RO	0x0
0	BSTENZ	BOOST ENZ	RW	0

:ADC:DBG4

Address offset	0x0000 1E2C
Description	DEBUG 4 ADC MSIP Control signal for Debug: adc_ctrl<31:0>
Type	RW

Bits	Field Name	Description	Type	Reset
31:16	Reserved		RO	0x0000
15:0	ADCCTL0	ADC CONTROL 0 ADC MSIP Control signal for Debug: adc_ctrl<15:0>	RW	0x0000

:ADC:CONVCTL

Address offset	0x0000 1F14
Description	Conversion Control
Type	RW

Bits	Field Name	Description	Type	Reset
31:19	Reserved		RO	0x0000
18	CONVCLKEN	CONV CLK ICG EN should be enabled after selecting CONV CLK	RW	0
17:16	CONCLKSEL	CONVERSION CLOCK SELECTOR ADC functional clock selection 0x0 - (Reset/Default) CLK_GATE 0x1 - SOC_CLK 0x2 - HFXT 0x3 - SOC_PLL_CLK_DIV note: not glitch free, therefore ICG should be enabled after selecting the right clk	RW	0x0
15	OV	OV 1 : Override, 0 : Use LUT values LUT is mentioned since the proposal was to pick up values automatically based on Internal vs External reference	RW	0
14:9	Reserved		RO	0x00
8:5	HOLD	000 : 1 Clock delay, ...., 111 : 8 Clock delay bit[3] - don't care and not used	RW	0x0
4:3	PREAMP	00 : 1 Clock delay, ..., 11 : 4 Clock delay	RW	0x0
2:0	DAC	000 : 1 Clock delay, ...., 111 : 8 Clock delay	RW	0x0

:ADC:CTRL

Address offset	0x0000 1F18
Description
Type	RW

Bits	Field Name	Description	Type	Reset
31:17	Reserved		RO	0x0000
16:9	FSBIT1	FUSE BITS 1 values for fuse OV	RW	0x20
8:0	FSBIT0	FUSE BITS 0 values for fuse OV	RW	0x000

:ADC:ADC_MOD_CTRL

Address offset	0x0000 1F1C
Description	MOD CONTROL
Type	RW

Bits	Field Name	Description	Type	Reset
31:2	Reserved		RO	0x0000 0000
1	SCASEL	SCALE SELECT 0 --> Normal output 1 --> scale 0-4223 in 0-4095 (efectively supporting 0-3.3V in 12 bit space)	RW	0
0	VREFRAN	VOLTAGE REFERENCE RANGE 0 --> 0 - 4095 in 0 - 3.2V 1 --> 0 - 4095 in 0.1 to 3.3V Only in Single Ended mode	RW	0

:ADC:INTCHCTL

Address offset	0x0000 1F20
Description	INTERNAL CHANNEL CONTROL
Type	RW

Bits	Field Name	Description	Type	Reset
31:2	Reserved		RO	0x0000 0000
1	RLOV	RLADDER OV Override Enable/Disable control for R-ladder inside RFCIO. This provides divided voltage to ADC by limiting the max. voltage. Default : 0 use value driven by ADC FSM	RW	0
0	RLVAL	RLADDER VALUE 0 --> 0 - 4095 in 0 - 3.2V 1 --> 0 - 4095 in 0.1 to 3.3V Only in Single Ended mode	RW	0

:ADC:STLTIM

Address offset	0x0000 1F24
Description	SETTLING TIME
Type	RW

Bits	Field Name	Description	Type	Reset
31:26	Reserved		RO	0x00
25:16	RCSETDEL	RC SETTLING DELAY delay value for RC SETTLING DELAY. value should be added to switch control delay. calculated using conv clk '1' - 1 conv clks '2' - 2 conv clks ... '3FF' - 1023 conv clks	RW	0x167
15:6	Reserved		RO	0x000
5:0	SWCTRLDEL	SWITCH CONTROL DELAY delay value for SWITCH CONTROL. calculated using conv clk '1' - 2 conv clks '2' - 3 conv clks ... '3F' - 64 conv clks	RW	0x27

:ADC:CLKCFG

Address offset	0x0000 2000
Description	ADC CLK CONFIG
Type	RW

Bits	Field Name	Description	Type	Reset
31:1	Reserved		RO	0x0000 0000
0	CLKCFG_STA	ENABLE '1' - enable adc clk '0' - disable adc clk	RW	0

ADC

ADC Registers Mapping Summary

:ADC Common Register Mapping Summary

ADC Instances Register Mapping Summary

ADC Register Descriptions

:ADC Common Register Descriptions

:ADC:FSCTL0

:ADC:FSCTL1

:ADC:FSCTL2

:ADC:FSCTL3

:ADC:REFBUF

:ADC:ATB

:ADC:INTEVT0IDX

:ADC:INTEVT0BM

:ADC:INTEVT0RIS

:ADC:INTEVT0MIS

:ADC:INTEVT0SET

:ADC:INTEVT0CLR

:ADC:INTEVT1IDX

:ADC:INTEVT1BM

:ADC:INTEVT1RIS

:ADC:INTEVT1MIS

:ADC:INTEVT1SET

:ADC:INTEVT1CLR

:ADC:INTEVT2IDX

:ADC:INTEVT2BM

:ADC:INTEVT2RIS

:ADC:INTEVT2MIS

:ADC:INTEVT2SET

:ADC:INTEVT2CLR

:ADC:EVTMOD

:ADC:DESC

:ADC:CTL0

:ADC:CTL1

:ADC:CTL2

:ADC:CTL3

:ADC:CLKFREQ

:ADC:SCOMP0

:ADC:SCOMP1

:ADC:REFCFG

:ADC:WCLOW

:ADC:WCHI

:ADC:FIFODATA

:ADC:ASCRES

:ADC:MEMCTL__0 - MEMCTL__5

:ADC:MEMRES__0 - MEMRES__15

:ADC:STA

:ADC:TEST0

:ADC:TEST1

:ADC:TEST2

:ADC:TEST3

:ADC:TEST4

:ADC:TEST5

:ADC:TEST6

:ADC:DBG1

:ADC:DBG2

:ADC:DBG3

:ADC:DBG4

:ADC:CONVCTL

:ADC:CTRL

:ADC:ADC_MOD_CTRL

:ADC:INTCHCTL

:ADC:STLTIM

:ADC:CLKCFG

:ADC:MEMCTL0 - MEMCTL5

:ADC:MEMRES0 - MEMRES15