HIBERNATE

This section provides information on the HIBERNATE Module Instance within this product. Each of the registers within the Module Instance is described separately below.

PRCM - POWER, RESET, CLK, MANAGEMENT INTERNAL NOTE: [confluence][https://confluence.itg.ti.com/display/WNG/PRCM+TOP+-+PRCM]

HIBERNATE Registers Mapping Summary

:HIBERNATE Common Register Mapping Summary

Register Name	Type	Register Width (Bits)	Register Reset	Address Offset
HIBSP0	RW	32	0x0000 0000	0x0000 0000
HIBSP1	RW	32	0x0000 0000	0x0000 0004
HIBSP2	RW	32	0x0000 0000	0x0000 0008
HIBSP3	RW	32	0x0000 0000	0x0000 000C
HIBSP4	RW	32	0x0000 0000	0x0000 0010
HIBSP5	RW	32	0x0000 0000	0x0000 0014
HIBSP6	RW	32	0x0000 0000	0x0000 0018
HIBSP7	RW	32	0x0000 0000	0x0000 001C
HIBCTL0	RW	32	0xA8C0 0000	0x0000 0020
HIBCTL1	RW	32	0x0000 00E0	0x0000 0024
TMRVAL0	RW	32	0x0000 0000	0x0000 0028
TMRVAL1	RW	32	0x0000 0000	0x0000 002C
HIBCTL2	RW	32	0x0000 0000	0x0000 0030
PMUSP0	RW	32	0x0000 0000	0x0000 0800

HIBERNATE Instances Register Mapping Summary

HIBERNATE Register Descriptions

:HIBERNATE Common Register Descriptions

:HIBERNATE:HIBSP0

Address offset	0x0000 0000
Description	Hibernate Scratchpad 0
Type	RW

Bits	Field Name	Description			Type	Reset
31:0	MEM_HIBSP0	Hibernate Scratchpad 0			RW	0x0000 0000

:HIBERNATE:HIBSP1

Address offset	0x0000 0004
Description	Hibernate Scratchpad 1
Type	RW

Bits	Field Name	Description			Type	Reset
31:0	MEM_HIBSP1	Hibernate Scratchpad 1			RW	0x0000 0000

:HIBERNATE:HIBSP2

Address offset	0x0000 0008
Description	Hibernate Scratchpad 2
Type	RW

Bits	Field Name	Description			Type	Reset
31:0	MEM_HIBSP2	Hibernate Scratchpad 2			RW	0x0000 0000

:HIBERNATE:HIBSP3

Address offset	0x0000 000C
Description	Hibernate Scratchpad 3
Type	RW

Bits	Field Name	Description			Type	Reset
31:0	MEM_HIBSP3	Hibernate Scratchpad 3			RW	0x0000 0000

:HIBERNATE:HIBSP4

Address offset	0x0000 0010
Description	Hibernate Scratchpad 4
Type	RW

Bits	Field Name	Description			Type	Reset
31:0	MEM_HIBSP4	Hibernate Scratchpad 4			RW	0x0000 0000

:HIBERNATE:HIBSP5

Address offset	0x0000 0014
Description	Hibernate Scratchpad 5
Type	RW

Bits	Field Name	Description			Type	Reset
31:0	MEM_HIBSP5	Hibernate Scratchpad 5			RW	0x0000 0000

:HIBERNATE:HIBSP6

Address offset	0x0000 0018
Description	Hibernate Scratchpad 6
Type	RW

Bits	Field Name	Description			Type	Reset
31:0	MEM_HIBSP6	Hibernate Scratchpad 6			RW	0x0000 0000

:HIBERNATE:HIBSP7

Address offset	0x0000 001C
Description	Hibernate Scratchpad 7
Type	RW

Bits	Field Name	Description			Type	Reset
31:0	MEM_HIBSP7	Hibernate Scratchpad 7			RW	0x0000 0000

:HIBERNATE:HIBCTL0

Address offset	0x0000 0020
Description	Hibernate Control Register 0
Type	RW

Bits	Field Name	Description			Type	Reset
31:0	TMRCFG0	Hibernate Timer Configuration 0 This register configure the 32 LSBs of Hibernate timer compare value. default is 24 Hours on 32.768KHz.			RW	0xA8C0 0000

:HIBERNATE:HIBCTL1

Address offset	0x0000 0024
Description	Hibernate Control Register 1
Type	RW

Bits	Field Name	Description	Type	Reset
31:24	Reserved		RO	0x00
23	WUEVTEN	HIBERNATE WAKEUP EVENT ENABLE '1' - enable '0' - disable	RW	0
22	CNTMOD	HIBERNATE COUNTER MODE '0' - Restart mode '1' - Continuous mode HIB_COUNTER_MODE = 0 (Restart mode): Enable rising edge (0 -> 1): Reset counter to 0 and start counting Enable falling edge (1 -> 0): Stop counting HIB_COUNTER_MODE = 1 (Continuous mode): Enable = 0: Counter disabled Enable = 1: Counter active (continues from previous value)	RW	0
21	CNTEN	HIBERNATE COUNTER ENABLE '1' - enable counter '0' - disable	RW	0
20	CLKSEL2	Clk Selectin 1: 0. LFXT 1. LFOSC	RW	0
19	CLKSEL1	Clk Selectin 1: 0. LFOSC 1. EXT CLK	RW	0
18	CLKSEL0	Clk Selectin 0: 0. LFXT 1. EXT CLK	RW	0
17:15	REFRESH	Hibernate Refresh Timer	RW	0x0
14:13	BGAPDIS	Hibernate Band Gap Disable Timer	RW	0x0
12:10	CAPSW	Hibernate Band Gap Ref Capsw Enable Timer	RW	0x0
9:5	BGAPREF	Hibernate Band Gap Ref Enable Timer Default is 0x1.	RW	0x07
4:0	TMRCFG0	Hibernate Timer Configuration 1 This register configure the 5 MSBs of Hibernate timer compare value.	RW	0x00

:HIBERNATE:TMRVAL0

Address offset	0x0000 0028
Description	Hibernate Timer Value 0. 32 LSBs of timer value
Type	RW

Bits	Field Name	Description			Type	Reset
31:0	VAL0				RO	0x0000 0000

:HIBERNATE:TMRVAL1

Address offset	0x0000 002C
Description	Hibernate Timer Value 1 5 MSBs of timer value
Type	RW

Bits	Field Name	Description	Type	Reset
31:5	Reserved		RO	0x000 0000
4:0	VAL1		RO	0x00

:HIBERNATE:HIBCTL2

Address offset	0x0000 0030
Description	Hibernate Control Register 2
Type	RW

Bits	Field Name	Description	Type	Reset
31:19	Reserved		RO	0x0000
18:3	LFXTCTRL	LFXT CONTROL	RW	0x0000
2	LFXTEN	LFXT ENABLE	RW	0
1	LFOENOVS	LFOSC ENABLE OVERRIDE SELECT un-used register	RW	0
0	LFOENOV	LFOSC ENABLE OVERRIDE	RW	0

:HIBERNATE:PMUSP0

Address offset	0x0000 0800
Description	PMU Scratchpad
Type	RW

Bits	Field Name	Description	Type	Reset
31:16	Reserved		RO	0x0000
15:0	MEM_PMUSP0	PMU Scratchpad	RW	0x0000