ADC

This section provides information on the ADC Module Instance within this product. Each of the registers within the Module Instance is described separately below.

ADC (Analog to Digital Converter) module INTERNAL_NOTE: ADC Documentation: https://confluence.itg.ti.com/pages/viewpage.action?spaceKey=BRD&title=Loki+ADC

ADC Registers Mapping Summary

:ADC Common Register Mapping Summary

Register Name	Type	Register Width (Bits)	Register Reset	Address Offset
IIDX0	RO	32	0x0000 0000	0x0000 1020
IMASK0	RW	32	0x0000 0000	0x0000 1028
RIS0	RO	32	0x0000 0000	0x0000 1030
MIS0	RO	32	0x0000 0000	0x0000 1038
ISET0	WO	32	0x0000 0000	0x0000 1040
ICLR0	WO	32	0x0000 0000	0x0000 1048
IIDX1	RO	32	0x0000 0000	0x0000 1050
IMASK1	RW	32	0x0000 0000	0x0000 1058
RIS1	RO	32	0x0000 0000	0x0000 1060
MIS1	RO	32	0x0000 0000	0x0000 1068
ISET1	WO	32	0x0000 0000	0x0000 1070
ICLR1	WO	32	0x0000 0000	0x0000 1078
IIDX2	RO	32	0x0000 0000	0x0000 1080
IMASK2	RW	32	0x0000 0000	0x0000 1088
RIS2	RO	32	0x0000 0000	0x0000 1090
MIS2	RO	32	0x0000 0000	0x0000 1098
ISET2	WO	32	0x0000 0000	0x0000 10A0
ICLR2	WO	32	0x0000 0000	0x0000 10A8
EVTMODE	RO	32	0x0000 0009	0x0000 10E0
DESC	RO	32	0x2611 0010	0x0000 10FC
CTL0	RW	32	0x0000 0000	0x0000 1100
CTL1	RW	32	0x0000 0000	0x0000 1104
CTL2	RW	32	0x0000 0000	0x0000 1108
CTL3	RW	32	0x0000 0000	0x0000 110C
SCOMP0	RW	32	0x0000 0000	0x0000 1114
SCOMP1	RW	32	0x0000 0000	0x0000 1118
REFCFG	RW	32	0x0000 0000	0x0000 111C
SCOMP2	RW	32	0x0000 0000	0x0000 1120
WCLOW0	RW	32	0x0000 0000	0x0000 1148
WCHIGH0	RW	32	0x0000 0000	0x0000 1150
WCLOW1	RW	32	0x0000 0000	0x0000 1154
WCHIGH1	RW	32	0x0000 0000	0x0000 1158
FIFODATA	RO	32	0x0000 0000	0x0000 1160
ASCRES	RO	32	0x0000 0000	0x0000 1170
MEMCTL0	RW	32	0x0000 0000	0x0000 1180
MEMCTL1	RW	32	0x0000 0000	0x0000 1184
MEMCTL2	RW	32	0x0000 0000	0x0000 1188
MEMCTL3	RW	32	0x0000 0000	0x0000 118C
MEMCTL4	RW	32	0x0000 0000	0x0000 1190
MEMCTL5	RW	32	0x0000 0000	0x0000 1194
MEMRES0	RO	32	0x0000 0000	0x0000 1280
MEMRES1	RO	32	0x0000 0000	0x0000 1284
MEMRES2	RO	32	0x0000 0000	0x0000 1288
MEMRES3	RO	32	0x0000 0000	0x0000 128C
MEMRES4	RO	32	0x0000 0000	0x0000 1290
MEMRES5	RO	32	0x0000 0000	0x0000 1294
MEMRES6	RO	32	0x0000 0000	0x0000 1298
MEMRES7	RO	32	0x0000 0000	0x0000 129C
MEMRES8	RO	32	0x0000 0000	0x0000 12A0
MEMRES9	RO	32	0x0000 0000	0x0000 12A4
MEMRES10	RO	32	0x0000 0000	0x0000 12A8
MEMRES11	RO	32	0x0000 0000	0x0000 12AC
MEMRES12	RO	32	0x0000 0000	0x0000 12B0
MEMRES13	RO	32	0x0000 0000	0x0000 12B4
MEMRES14	RO	32	0x0000 0000	0x0000 12B8
MEMRES15	RO	32	0x0000 0000	0x0000 12BC
STA	RO	32	0x0000 0000	0x0000 1340
TEST0	RW	32	0x0000 0000	0x0000 1E00
TEST1	RW	32	0x0000 0000	0x0000 1E04
TEST2	RW	32	0x0000 0000	0x0000 1E08
TEST3	RW	32	0x0000 0000	0x0000 1E0C
TEST4	RW	32	0x0000 0000	0x0000 1E10
TEST5	RW	32	0x0000 0000	0x0000 1E14
TEST6	RW	32	0x0000 0000	0x0000 1E18
TEST7	RW	32	0x0000 0000	0x0000 1E1C
TEST8	RW	32	0x0000 0000	0x0000 1E20
TEST9	RW	32	0x0000 0000	0x0000 1E24
TEST10	RW	32	0x0000 0000	0x0000 1E28
TEST11	RW	32	0x0000 0000	0x0000 1E2C
TEST12	RW	32	0x0000 0000	0x0000 1E30
FCLKCFG	RW	32	0x0000 0000	0x0000 1F14
CLK_EN	RW	32	0x0000 0000	0x0000 2000

ADC Instances Register Mapping Summary

ADC Register Descriptions

:ADC Common Register Descriptions

:ADC:IIDX0

Address offset	0x0000 1020
Description	This register provides the highest priority enabled interrupt index. 0x0 means no event pending. Interrupt 1 is the highest priority, 2 next highest, 4, 8, ... 2^31 is the least priority. That is, the least bit position that is set to 1 denotes the highest priority pending interrupt. The priority order is fixed. However, users can implement their own prioritization schemes using other registers that expose the full set of interrupts that have occurred. On each read, only one interrupt is indicated. On a read, the current interrupt (highest priority) is automatically cleared by the hardware and the corresponding interrupt flag in the RIS and MIS are cleared as well. After a read from the CPU (not from the debug interface), the register must be updated with the next highest priority interrupt, if none are pending, then it must display 0x0.
Type	RO

Bits	Field Name	Description		Type	Reset
31:10	Reserved			RO	0x00 0000
9:0	STA	Interrupt index status		RO	0x000
		Read 0x000	NOINTR No bit is set means there is no pending interrupt request
		Read 0x001	OVIFG MEMRESx overflow interrupt
		Read 0x002	TOVIFG Sequence Conversion time overflow interrupt
		Read 0x003	HIGHIFG High threshold compare interrupt
		Read 0x004	LOWIFG Low threshold compare interrupt
		Read 0x005	INIFG Primary Sequence In range comparator interrupt
		Read 0x006	DMADONE DMA done interrupt, generated on DMA transfer completion,
		Read 0x007	UVIFG MEMRESx underflow interrupt
		Read 0x009	MEMRESIFG0 MEMRES0 data loaded interrupt
		Read 0x00A	MEMRESIFG1 MEMRES1 data loaded interrupt
		Read 0x00B	MEMRESIFG2 MEMRES2 data loaded interrupt
		Read 0x00C	MEMRESIFG3 MEMRES3 data loaded interrupt
		Read 0x00D	MEMRESIFG4 Magillem Info : Information not available in the IP-XACT file
		Read 0x00E	MEMRESIFG5 MEMRES5 data loaded interrupt
		Read 0x00F	MEMRESIFG6 MEMRES6 data loaded interrupt
		Read 0x010	MEMRESIFG7 MEMRES7 data loaded interrupt
		Read 0x011	MEMRESIFG8 MEMRES8 data loaded interrupt
		Read 0x012	MEMRESIFG9 MEMRES9 data loaded interrupt
		Read 0x013	MEMRESIFG10 MEMRES10 data loaded interrupt
		Read 0x014	MEMRESIFG11 MEMRES11 data loaded interrupt
		Read 0x015	MEMRESIFG12 MEMRES12 data loaded interrupt
		Read 0x016	MEMRESIFG13 MEMRES13 data loaded interrupt
		Read 0x017	MEMRESIFG14 MEMRES14 data loaded interrupt
		Read 0x018	MEMRESIFG15 MEMRES15 data loaded interrupt

:ADC:IMASK0

Address offset	0x0000 1028
Description	Interrupt mask. This register selects interrupt sources which are allowed to pass from [RIS0.] to [MIS0.] when the corresponding bit-fields are set to 1.
Type	RW

Bits	Field Name	Description		Type	Reset
31:24	Reserved			RO	0x00
23	MEMRESIFG15	MEMRES15 conversion result interrupt mask.		RW	0
		0	DIS Disable interrupt mask
		1	EN Enable interrupt mask
22	MEMRESIFG14	MEMRES14 conversion result interrupt mask.		RW	0
		0	DIS Disable interrupt mask
		1	EN Enable interrupt mask
21	MEMRESIFG13	MEMRES13 conversion result interrupt mask.		RW	0
		0	DIS Disable interrupt mask
		1	EN Enable interrupt mask
20	MEMRESIFG12	MEMRES12 conversion result interrupt mask.		RW	0
		0	DIS Disable interrupt mask
		1	EN Enable interrupt mask
19	MEMRESIFG11	MEMRES11 conversion result interrupt mask.		RW	0
		0	DIS Disable interrupt mask
		1	EN Enable interrupt mask
18	MEMRESIFG10	MEMRES10 conversion result interrupt mask.		RW	0
		0	DIS Disable interrupt mask
		1	EN Enable interrupt mask
17	MEMRESIFG9	MEMRES9 conversion result interrupt mask.		RW	0
		0	DIS Disable interrupt mask
		1	EN Enable interrupt mask
16	MEMRESIFG8	MEMRES8 conversion result interrupt mask.		RW	0
		0	DIS Disable interrupt mask
		1	EN Enable interrupt mask
15	MEMRESIFG7	MEMRES7 conversion result interrupt mask.		RW	0
		0	DIS Disable interrupt mask
		1	EN Enable interrupt mask
14	MEMRESIFG6	MEMRES6 conversion result interrupt mask.		RW	0
		0	DIS Disable interrupt mask
		1	EN Enable interrupt mask
13	MEMRESIFG5	MEMRES5 conversion result interrupt mask.		RW	0
		0	DIS Disable interrupt mask
		1	EN Enable interrupt mask
12	MEMRESIFG4	MEMRES4 conversion result interrupt mask.		RW	0
		0	DIS Disable interrupt mask
		1	EN Enable interrupt mask
11	MEMRESIFG3	MEMRES3 conversion result interrupt mask.		RW	0
		0	DIS Disable interrupt mask
		1	EN Enable interrupt mask
10	MEMRESIFG2	MEMRES2 conversion result interrupt mask.		RW	0
		0	DIS Disable interrupt mask
		1	EN Enable interrupt mask
9	MEMRESIFG1	MEMRES1 conversion result interrupt mask.		RW	0
		0	DIS Disable interrupt mask
		1	EN Enable interrupt mask
8	MEMRESIFG0	MEMRES0 conversion result interrupt mask.		RW	0
		0	DIS Disable interrupt mask
		1	EN Enable interrupt mask
7	ASCDONE	Mask for ASC done raw interrupt flag.		RW	0
		0	DIS Disable interrupt mask
		1	EN Enable interrupt mask
6	UVIFG	Conversion underflow interrupt mask.		RW	0
		0	DIS Disable interrupt mask
		1	EN Enable interrupt mask
5	DMADONE	DMA done interrupt mask.		RW	0
		0	DIS Disable interrupt mask
		1	EN Enable interrupt mask
4	INIFG	In-range comparator interrupt mask.		RW	0
		0	DIS Disable interrupt mask
		1	EN Enable interrupt mask
3	LOWIFG	Low threshold compare interrupt mask.		RW	0
		0	DIS Disable interrupt mask
		1	EN Enable interrupt mask
2	HIGHIFG	High threshold compare interrupt mask.		RW	0
		0	DIS Disable interrupt mask
		1	EN Enable interrupt mask
1	TOVIFG	Sequence conversion time overflow interrupt mask.		RW	0
		0	DIS Disable interrupt mask
		1	EN Enable interrupt mask
0	OVIFG	Conversion overflow interrupt mask.		RW	0
		0	DIS Disable interrupt mask
		1	EN Enable interrupt mask

:ADC:RIS0

Address offset	0x0000 1030
Description	Raw interrupt status. This register reflects the state of all pending interrupts, regardless of masking. This register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the corresponding [ICLR0.*] register bit.
Type	RO

Bits	Field Name	Description		Type	Reset
31:24	Reserved			RO	0x00
23	MEMRESIFG15	Raw interrupt status for MEMRES15. This bit is set to 1 when MEMRES15 is loaded with a new conversion result. Reading MEMRES15 register will clear this bit, or when the corresponding bit in ICLR0 is set to 1		RO	0
		Read 0	CLR No new data ready.
		Read 1	SET A new data is ready to be read.
22	MEMRESIFG14	Raw interrupt status for MEMRES14. This bit is set to 1 when MEMRES14 is loaded with a new conversion result. Reading MEMRES14 register will clear this bit, or when the corresponding bit in ICLR0 is set to 1		RO	0
		Read 0	CLR No new data ready.
		Read 1	SET A new data is ready to be read.
21	MEMRESIFG13	Raw interrupt status for MEMRES13. This bit is set to 1 when MEMRES13 is loaded with a new conversion result. Reading MEMRES13 register will clear this bit, or when the corresponding bit in ICLR0 is set to 1		RO	0
		Read 0	CLR No new data ready.
		Read 1	SET A new data is ready to be read.
20	MEMRESIFG12	Raw interrupt status for MEMRES12. This bit is set to 1 when MEMRES12 is loaded with a new conversion result. Reading MEMRES12 register will clear this bit, or when the corresponding bit in ICLR0 is set to 1		RO	0
		Read 0	CLR No new data ready.
		Read 1	SET A new data is ready to be read.
19	MEMRESIFG11	Raw interrupt status for MEMRES11. This bit is set to 1 when MEMRES11 is loaded with a new conversion result. Reading MEMRES11 register will clear this bit, or when the corresponding bit in ICLR0 is set to 1		RO	0
		Read 0	CLR No new data ready.
		Read 1	SET A new data is ready to be read.
18	MEMRESIFG10	Raw interrupt status for MEMRES10. This bit is set to 1 when MEMRES10 is loaded with a new conversion result. Reading MEMRES10 register will clear this bit, or when the corresponding bit in ICLR0 is set to 1		RO	0
		Read 0	CLR No new data ready.
		Read 1	SET A new data is ready to be read.
17	MEMRESIFG9	Raw interrupt status for MEMRES9. This bit is set to 1 when MEMRES9 is loaded with a new conversion result. Reading MEMRES9 register will clear this bit, or when the corresponding bit in ICLR0 is set to 1		RO	0
		Read 0	CLR No new data ready.
		Read 1	SET A new data is ready to be read.
16	MEMRESIFG8	Raw interrupt status for MEMRES8. This bit is set to 1 when MEMRES8 is loaded with a new conversion result. Reading MEMRES8 register will clear this bit, or when the corresponding bit in ICLR0 is set to 1		RO	0
		Read 0	CLR No new data ready.
		Read 1	SET A new data is ready to be read.
15	MEMRESIFG7	Raw interrupt status for MEMRES7. This bit is set to 1 when MEMRES7 is loaded with a new conversion result. Reading MEMRES7 register will clear this bit, or when the corresponding bit in ICLR0 is set to 1		RO	0
		Read 0	CLR No new data ready.
		Read 1	SET A new data is ready to be read.
14	MEMRESIFG6	Raw interrupt status for MEMRES6. This bit is set to 1 when MEMRES6 is loaded with a new conversion result. Reading MEMRES6 register will clear this bit, or when the corresponding bit in ICLR0 is set to 1		RO	0
		Read 0	CLR No new data ready.
		Read 1	SET A new data is ready to be read.
13	MEMRESIFG5	Raw interrupt status for MEMRES5. This bit is set to 1 when MEMRES5 is loaded with a new conversion result. Reading MEMRES5 register will clear this bit, or when the corresponding bit in ICLR0 is set to 1		RO	0
		Read 0	CLR No new data ready.
		Read 1	SET A new data is ready to be read.
12	MEMRESIFG4	Raw interrupt status for MEMRES4. This bit is set to 1 when MEMRES4 is loaded with a new conversion result. Reading MEMRES4 register will clear this bit, or when the corresponding bit in ICLR0 is set to 1		RO	0
		Read 0	CLR No new data ready.
		Read 1	SET A new data is ready to be read.
11	MEMRESIFG3	Raw interrupt status for MEMRES3. This bit is set to 1 when MEMRES3 is loaded with a new conversion result. Reading MEMRES3 register will clear this bit, or when the corresponding bit in ICLR0 is set to 1		RO	0
		Read 0	CLR No new data ready.
		Read 1	SET A new data is ready to be read.
10	MEMRESIFG2	Raw interrupt status for MEMRES2. This bit is set to 1 when MEMRES2 is loaded with a new conversion result. Reading MEMRES2 register will clear this bit, or when the corresponding bit in ICLR0 is set to 1		RO	0
		Read 0	CLR No new data ready.
		Read 1	SET A new data is ready to be read.
9	MEMRESIFG1	Raw interrupt status for MEMRES1. This bit is set to 1 when MEMRES1 is loaded with a new conversion result. Reading MEMRES1 register will clear this bit, or when the corresponding bit in ICLR0 is set to 1		RO	0
		Read 0	CLR No new data ready.
		Read 1	SET A new data is ready to be read.
8	MEMRESIFG0	Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. Reading MEMRES0 register will clear this bit, or when the corresponding bit in ICLR0 is set to 1		RO	0
		Read 0	CLR No new data ready.
		Read 1	SET A new data is ready to be read.
7	ASCDONE	Raw interrupt flag for ASC done.		RO	0
		Read 0	CLR Interrupt is not pending.
		Read 1	SET Interrupt is pending.
6	UVIFG	Raw interrupt flag for MEMRESx underflow.		RO	0
		Read 0	CLR Interrupt is not pending.
		Read 1	SET Interrupt is pending.
5	DMADONE	Raw interrupt flag for DMADONE.		RO	0
		Read 0	CLR Interrupt is not pending.
		Read 1	SET Interrupt is pending.
4	INIFG	Raw interrupt status for In-range comparator.		RO	0
		Read 0	CLR Interrupt is not pending.
		Read 1	SET Interrupt is pending.
3	LOWIFG	Raw interrupt flag for the MEMRESx result register being below than the WCLOWx threshold of the window comparator.		RO	0
		Read 0	CLR Interrupt is not pending.
		Read 1	SET Interrupt is pending.
2	HIGHIFG	Raw interrupt flag for the MEMRESx result register being higher than the WCHIGHx threshold of the window comparator.		RO	0
		Read 0	CLR Interrupt is not pending.
		Read 1	SET Interrupt is pending.
1	TOVIFG	Raw interrupt flag for sequence conversion trigger overflow.		RO	0
		Read 0	CLR Interrupt is not pending.
		Read 1	SET Interrupt is pending.
0	OVIFG	Raw interrupt flag for MEMRESx overflow.		RO	0
		Read 0	CLR Interrupt is not pending.
		Read 1	SET Interrupt is pending.

:ADC:MIS0

Address offset	0x0000 1038
Description	Masked interrupt status. This register is simply a bitwise AND of the contents of [IMASK.] and [RIS.] registers. A flag set in this register can be cleared by writing 1 to the corresponding [ICLR.*] register bit.
Type	RO

Bits	Field Name	Description		Type	Reset
31:24	Reserved			RO	0x00
23	MEMRESIFG15	Masked interrupt status for MEMRES15.		RO	0
		Read 0	CLR No new data ready.
		Read 1	SET A new data is ready to be read.
22	MEMRESIFG14	Masked interrupt status for MEMRES14.		RO	0
		Read 0	CLR No new data ready.
		Read 1	SET A new data is ready to be read.
21	MEMRESIFG13	Masked interrupt status for MEMRES13.		RO	0
		Read 0	CLR No new data ready.
		Read 1	SET A new data is ready to be read.
20	MEMRESIFG12	Masked interrupt status for MEMRES12.		RO	0
		Read 0	CLR No new data ready.
		Read 1	SET A new data is ready to be read.
19	MEMRESIFG11	Masked interrupt status for MEMRES11.		RO	0
		Read 0	CLR No new data ready.
		Read 1	SET A new data is ready to be read.
18	MEMRESIFG10	Masked interrupt status for MEMRES10.		RO	0
		Read 0	CLR No new data ready.
		Read 1	SET A new data is ready to be read.
17	MEMRESIFG9	Masked interrupt status for MEMRES9.		RO	0
		Read 0	CLR No new data ready.
		Read 1	SET A new data is ready to be read.
16	MEMRESIFG8	Masked interrupt status for MEMRES8.		RO	0
		Read 0	CLR No new data ready.
		Read 1	SET A new data is ready to be read.
15	MEMRESIFG7	Masked interrupt status for MEMRES7.		RO	0
		Read 0	CLR No new data ready.
		Read 1	SET A new data is ready to be read.
14	MEMRESIFG6	Masked interrupt status for MEMRES6.		RO	0
		Read 0	CLR No new data ready.
		Read 1	SET A new data is ready to be read.
13	MEMRESIFG5	Masked interrupt status for MEMRES5.		RO	0
		Read 0	CLR No new data ready.
		Read 1	SET A new data is ready to be read.
12	MEMRESIFG4	Masked interrupt status for MEMRES4.		RO	0
		Read 0	CLR No new data ready.
		Read 1	SET A new data is ready to be read.
11	MEMRESIFG3	Masked interrupt status for MEMRES3.		RO	0
		Read 0	CLR No new data ready.
		Read 1	SET A new data is ready to be read.
10	MEMRESIFG2	Masked interrupt status for MEMRES2.		RO	0
		Read 0	CLR No new data ready.
		Read 1	SET A new data is ready to be read.
9	MEMRESIFG1	Masked interrupt status for MEMRES1.		RO	0
		Read 0	CLR No new data ready.
		Read 1	SET A new data is ready to be read.
8	MEMRESIFG0	Masked interrupt status for MEMRES0.		RO	0
		Read 0	CLR No new data ready.
		Read 1	SET A new data is ready to be read.
7	ASCDONE	Masked interrupt status for ASC done.		RO	0
		Read 0	CLR Interrupt is not pending.
		Read 1	SET Interrupt is pending.
6	UVIFG	Masked interrupt flag for MEMRESx underflow.		RO	0
		Read 0	CLR Interrupt is not pending.
		Read 1	SET Interrupt is pending.
5	DMADONE	Masked interrupt flag for DMADONE.		RO	0
		Read 0	CLR Interrupt is not pending.
		Read 1	SET Interrupt is pending.
4	INIFG	Mask INIFG in MIS0 register.		RO	0
		Read 0	CLR Interrupt is not pending.
		Read 1	SET Interrupt is pending.
3	LOWIFG	Masked interrupt flag for the MEMRESx result register being below than the WCLOWx threshold of the window comparator.		RO	0
		Read 0	CLR Interrupt is not pending.
		Read 1	SET Interrupt is pending.
2	HIGHIFG	Masked interrupt flag for the MEMRESx result register being higher than the WCHIGHx threshold of the window comparator.		RO	0
		Read 0	CLR Interrupt is not pending.
		Read 1	SET Interrupt is pending.
1	TOVIFG	Masked interrupt flag for sequence conversion timeout overflow.		RO	0
		Read 0	CLR Interrupt is not pending.
		Read 1	SET Interrupt is pending.
0	OVIFG	Masked interrupt flag for MEMRESx overflow.		RO	0
		Read 0	CLR Interrupt is not pending.
		Read 1	SET Interrupt is pending.

:ADC:ISET0

Address offset	0x0000 1040
Description	Interrupt set register. This register can used by software for diagnostics and safety checking purposes. Writing a 1 to a bit in this register will set the event and the corresponding [RIS.] bit also gets set. If the corresponding [IMASK.] bit is set, then the corresponding [MIS.*] register bit also gets set.
Type	WO

Bits	Field Name	Description		Type	Reset
31:24	Reserved			RO	0x00
23	MEMRESIFG15	Set interrupt status for MEMRES15.		WO	0
		Write 0	NO_EFFECT No new data ready.
		Write 1	SET A new data is ready to be read.
22	MEMRESIFG14	Set interrupt status for MEMRES14.		WO	0
		Write 0	NO_EFFECT No new data ready.
		Write 1	SET A new data is ready to be read.
21	MEMRESIFG13	Set interrupt status for MEMRES13.		WO	0
		Write 0	NO_EFFECT No new data ready.
		Write 1	SET A new data is ready to be read.
20	MEMRESIFG12	Set interrupt status for MEMRES12.		WO	0
		Write 0	NO_EFFECT No new data ready.
		Write 1	SET A new data is ready to be read.
19	MEMRESIFG11	Set interrupt status for MEMRES11.		WO	0
		Write 0	NO_EFFECT No new data ready.
		Write 1	SET A new data is ready to be read.
18	MEMRESIFG10	Set interrupt status for MEMRES10.		WO	0
		Write 0	NO_EFFECT No new data ready.
		Write 1	SET A new data is ready to be read.
17	MEMRESIFG9	Set interrupt status for MEMRES9.		WO	0
		Write 0	NO_EFFECT No new data ready.
		Write 1	SET A new data is ready to be read.
16	MEMRESIFG8	Set interrupt status for MEMRES8.		WO	0
		Write 0	NO_EFFECT No new data ready.
		Write 1	SET A new data is ready to be read.
15	MEMRESIFG7	Set interrupt status for MEMRES7.		WO	0
		Write 0	NO_EFFECT No new data ready.
		Write 1	SET A new data is ready to be read.
14	MEMRESIFG6	Set interrupt status for MEMRES6.		WO	0
		Write 0	NO_EFFECT No new data ready.
		Write 1	SET A new data is ready to be read.
13	MEMRESIFG5	Set interrupt status for MEMRES5.		WO	0
		Write 0	NO_EFFECT No new data ready.
		Write 1	SET A new data is ready to be read.
12	MEMRESIFG4			WO	0
		Write 0	NO_EFFECT No new data ready.
		Write 1	SET A new data is ready to be read.
11	MEMRESIFG3	Set interrupt status for MEMRES3.		WO	0
		Write 0	NO_EFFECT No new data ready.
		Write 1	SET A new data is ready to be read.
10	MEMRESIFG2	Set interrupt status for MEMRES2.		WO	0
		Write 0	NO_EFFECT No new data ready.
		Write 1	SET A new data is ready to be read.
9	MEMRESIFG1	Set interrupt status for MEMRES1.		WO	0
		Write 0	NO_EFFECT No new data ready.
		Write 1	SET A new data is ready to be read.
8	MEMRESIFG0	Set Interrupt status for MEMRES0.		WO	0
		Write 0	NO_EFFECT No new data ready.
		Write 1	SET A new data is ready to be read.
7	ASCDONE	Set interrupt for ASC done.		WO	0
		Write 0	NO_EFFECT Interrupt is not pending.
		Write 1	SET Interrupt is pending.
6	UVIFG	Set interrupt for MEMRESx underflow.		WO	0
		Write 0	NO_EFFECT Interrupt is not pending.
		Write 1	SET Interrupt is pending.
5	DMADONE	Set interrupt for DMADONE.		WO	0
		Write 0	NO_EFFECT Interrupt is not pending.
		Write 1	SET Interrupt is pending.
4	INIFG	Set INIFG interrupt register.		WO	0
		Write 0	NO_EFFECT Interrupt is not pending.
		Write 1	SET Interrupt is pending.
3	LOWIFG	Set interrupt for MEMRESx result register being below than the WCLOWx threshold of the window comparator.		WO	0
		Write 0	NO_EFFECT Interrupt is not pending.
		Write 1	SET Interrupt is pending.
2	HIGHIFG	Set Interrupt for the MEMRESx result register being higher than the WCHIGHx threshold of the window comparator.		WO	0
		Write 0	NO_EFFECT Interrupt is not pending.
		Write 1	SET Interrupt is pending.
1	TOVIFG	Set interrupt for sequence conversion timeout overflow.		WO	0
		Write 0	NO_EFFECT Interrupt is not pending.
		Write 1	SET Interrupt is pending.
0	OVIFG	Set Interrupt for MEMRESx overflow.		WO	0
		Write 0	NO_EFFECT Interrupt is not pending.
		Write 1	SET Interrupt is pending.

:ADC:ICLR0

Address offset	0x0000 1048
Description	Interrupt clear register. This register allows software to clear interrupts. Writing a 1 to a bit in this register will clear the event and the corresponding [RIS.] bit also gets cleared. If the corresponding [IMASK.] bit is set, then the corresponding [MIS.*] register bit also gets cleared.
Type	WO

Bits	Field Name	Description		Type	Reset
31:24	Reserved			RO	0x00
23	MEMRESIFG15	Clear interrupt status for MEMRES15.		WO	0
		Write 0	NO_EFFECT No new data ready.
		Write 1	CLR A new data is ready to be read.
22	MEMRESIFG14	Clear interrupt status for MEMRES14.		WO	0
		Write 0	NO_EFFECT No new data ready.
		Write 1	CLR A new data is ready to be read.
21	MEMRESIFG13	Clear interrupt status for MEMRES13.		WO	0
		Write 0	NO_EFFECT No new data ready.
		Write 1	CLR A new data is ready to be read.
20	MEMRESIFG12	Clear interrupt status for MEMRES12.		WO	0
		Write 0	NO_EFFECT No new data ready.
		Write 1	CLR A new data is ready to be read.
19	MEMRESIFG11	Clear interrupt status for MEMRES11.		WO	0
		Write 0	NO_EFFECT No new data ready.
		Write 1	CLR A new data is ready to be read.
18	MEMRESIFG10	Clear interrupt status for MEMRES10.		WO	0
		Write 0	NO_EFFECT No new data ready.
		Write 1	CLR A new data is ready to be read.
17	MEMRESIFG9	Clear interrupt status for MEMRES9.		WO	0
		Write 0	NO_EFFECT No new data ready.
		Write 1	CLR A new data is ready to be read.
16	MEMRESIFG8	Clear interrupt status for MEMRES8.		WO	0
		Write 0	NO_EFFECT No new data ready.
		Write 1	CLR A new data is ready to be read.
15	MEMRESIFG7	Clear interrupt status for MEMRES7.		WO	0
		Write 0	NO_EFFECT No new data ready.
		Write 1	CLR A new data is ready to be read.
14	MEMRESIFG6	Clear interrupt status for MEMRES6.		WO	0
		Write 0	NO_EFFECT No new data ready.
		Write 1	CLR A new data is ready to be read.
13	MEMRESIFG5	Clear interrupt status for MEMRES5.		WO	0
		Write 0	NO_EFFECT No new data ready.
		Write 1	CLR A new data is ready to be read.
12	MEMRESIFG4	Clear interrupt status for MEMRES4.		WO	0
		Write 0	NO_EFFECT No new data ready.
		Write 1	CLR A new data is ready to be read.
11	MEMRESIFG3	Clear interrupt status for MEMRES3.		WO	0
		Write 0	NO_EFFECT No new data ready.
		Write 1	CLR A new data is ready to be read.
10	MEMRESIFG2	Clear interrupt status for MEMRES2.		WO	0
		Write 0	NO_EFFECT No new data ready.
		Write 1	CLR A new data is ready to be read.
9	MEMRESIFG1	Clear interrupt status for MEMRES1.		WO	0
		Write 0	NO_EFFECT No new data ready.
		Write 1	CLR A new data is ready to be read.
8	MEMRESIFG0	Clear interrupt status for MEMRES0.		WO	0
		Write 0	NO_EFFECT No new data ready.
		Write 1	CLR A new data is ready to be read.
7	ASCDONE	Clear ASC done flag in RIS.		WO	0
		Write 0	NO_EFFECT Interrupt is not pending.
		Write 1	CLR Interrupt is pending.
6	UVIFG	Clear interrupt flag for MEMRESx underflow.		WO	0
		Write 0	NO_EFFECT Interrupt is not pending.
		Write 1	CLR Interrupt is pending.
5	DMADONE	Clear interrupt flag for DMADONE.		WO	0
		Write 0	NO_EFFECT Interrupt is not pending.
		Write 1	CLR Interrupt is pending.
4	INIFG	Clear INIFG in MIS0 register.		WO	0
		Write 0	NO_EFFECT Interrupt is not pending.
		Write 1	CLR Interrupt is pending.
3	LOWIFG	Clear interrupt flag for the MEMRESx result register being below than the WCLOWx threshold of the window comparator.		WO	0
		Write 0	NO_EFFECT Interrupt is not pending.
		Write 1	CLR Interrupt is pending.
2	HIGHIFG	Clear interrupt flag for the MEMRESx result register being higher than the WCHIGHx threshold of the window comparator.		WO	0
		Write 0	NO_EFFECT Interrupt is not pending.
		Write 1	CLR Interrupt is pending.
1	TOVIFG	Clear interrupt flag for sequence conversion timeout overflow.		WO	0
		Write 0	NO_EFFECT Interrupt is not pending.
		Write 1	CLR Interrupt is pending.
0	OVIFG	Clear interrupt flag for MEMRESx overflow.		WO	0
		Write 0	NO_EFFECT Interrupt is not pending.
		Write 1	CLR Interrupt is pending.

:ADC:IIDX1

Address offset	0x0000 1050
Description	This register provides the highest priority enabled interrupt index. 0x0 means no event pending. Interrupt 1 is the highest priority, 2 next highest, 4, 8, ... 2^31 is the least priority. That is, the least bit position that is set to 1 denotes the highest priority pending interrupt. The priority order is fixed. However, users can implement their own prioritization schemes using other registers that expose the full set of interrupts that have occurred. On each read, only one interrupt is indicated. On a read, the current interrupt (highest priority) is automatically cleared by the hardware and the corresponding interrupt flag in the RIS and MIS are cleared as well. After a read from the CPU (not from the debug interface), the register must be updated with the next highest priority interrupt, if none are pending, then it must display 0x0.
Type	RO

Bits	Field Name	Description		Type	Reset
31:10	Reserved			RO	0x00 0000
9:0	STA	Interrupt index status		RO	0x000
		Read 0x000	NOINTR No bit is set means there is no pending interrupt request
		Read 0x003	HIGHIFG High threshold compare interrupt
		Read 0x004	LOWIFG Low threshold compare interrupt
		Read 0x005	INIFG Primary Sequence In range comparator interrupt
		Read 0x009	MEMRESIFG0 MEMRES0 data loaded interrupt

:ADC:IMASK1

Address offset	0x0000 1058
Description	Interrupt mask. This register selects interrupt sources which are allowed to pass from [RIS0.] to [MIS0.] when the corresponding bit-fields are set to 1.
Type	RW

Bits	Field Name	Description		Type	Reset
31:9	Reserved			RO	0x00 0000
8	MEMRESIFG0	MEMRES0 conversion result interrupt mask.		RW	0
		0	CLR No new data ready.
		1	SET A new data is ready to be read.
7:5	Reserved			RO	0x0
4	INIFG	In-range comparator interrupt mask.		RW	0
		0	CLR Interrupt is not pending.
		1	SET Interrupt is pending.
3	LOWIFG	Low threshold compare interrupt mask.		RW	0
		0	CLR Interrupt is not pending.
		1	SET Interrupt is pending.
2	HIGHIFG	High threshold compare interrupt mask.		RW	0
		0	CLR Interrupt is not pending.
		1	SET Interrupt is pending.
1:0	Reserved			RO	0x0

:ADC:RIS1

Address offset	0x0000 1060
Description	Raw interrupt status. This register reflects the state of all pending interrupts, regardless of masking. This register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the corresponding [ICLR0.*] register bit.
Type	RO

Bits	Field Name	Description		Type	Reset
31:9	Reserved			RO	0x00 0000
8	MEMRESIFG0	Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. Reading MEMRES0 register will clear this bit, or when the corresponding bit in ICLR1 is set to 1		RO	0
		Read 0	CLR No new data ready.
		Read 1	SET A new data is ready to be read.
7:5	Reserved			RO	0x0
4	INIFG	Raw interrupt status for In-range comparator.		RO	0
		Read 0	CLR Interrupt is not pending.
		Read 1	SET Interrupt is pending.
3	LOWIFG	Raw interrupt flag for the MEMRESx result register being below than the WCLOWx threshold of the window comparator.		RO	0
		Read 0	CLR Interrupt is not pending.
		Read 1	SET Interrupt is pending.
2	HIGHIFG	Raw interrupt flag for the MEMRESx result register being higher than the WCHIGHx threshold of the window comparator.		RO	0
		Read 0	CLR Interrupt is not pending.
		Read 1	SET Interrupt is pending.
1:0	Reserved			RO	0x0

:ADC:MIS1

Address offset	0x0000 1068
Description	Masked interrupt status. This register is simply a bitwise AND of the contents of [IMASK.] and [RIS.] registers. A flag set in this register can be cleared by writing 1 to the corresponding [ICLR.*] register bit.
Type	RO

Bits	Field Name	Description		Type	Reset
31:9	Reserved			RO	0x00 0000
8	MEMRESIFG0	Masked interrupt status for MEMRES0.		RO	0
		Read 0	CLR No new data ready.
		Read 1	SET A new data is ready to be read.
7:5	Reserved			RO	0x0
4	INIFG	Mask INIFG in MIS1 register.		RO	0
		Read 0	CLR Interrupt is not pending.
		Read 1	SET Interrupt is pending.
3	LOWIFG	Masked interrupt flag for the MEMRESx result register being below than the WCLOWx threshold of the window comparator.		RO	0
		Read 0	CLR Interrupt is not pending.
		Read 1	SET Interrupt is pending.
2	HIGHIFG	Masked interrupt flag for the MEMRESx result register being higher than the WCHIGHx threshold of the window comparator.		RO	0
		Read 0	CLR Interrupt is not pending.
		Read 1	SET Interrupt is pending.
1:0	Reserved			RO	0x0

:ADC:ISET1

Address offset	0x0000 1070
Description	Interrupt set register. This register can used by software for diagnostics and safety checking purposes. Writing a 1 to a bit in this register will set the event and the corresponding [RIS.] bit also gets set. If the corresponding [IMASK.] bit is set, then the corresponding [MIS.*] register bit also gets set.
Type	WO

Bits	Field Name	Description		Type	Reset
31:9	Reserved			RO	0x00 0000
8	MEMRESIFG0	Set Interrupt status for MEMRES0.		WO	0
		Write 0	NO_EFFECT No new data ready.
		Write 1	SET A new data is ready to be read.
7:5	Reserved			RO	0x0
4	INIFG	Set INIFG interrupt register.		WO	0
		Write 0	NO_EFFECT Interrupt is not pending.
		Write 1	SET Interrupt is pending.
3	LOWIFG	Set interrupt for MEMRESx result register being below than the WCLOWx threshold of the window comparator.		WO	0
		Write 0	NO_EFFECT Interrupt is not pending.
		Write 1	SET Interrupt is pending.
2	HIGHIFG	Set Interrupt for the MEMRESx result register being higher than the WCHIGHx threshold of the window comparator.		WO	0
		Write 0	NO_EFFECT Interrupt is not pending.
		Write 1	SET Interrupt is pending.
1:0	Reserved			RO	0x0

:ADC:ICLR1

Address offset	0x0000 1078
Description	Interrupt clear register. This register allows software to clear interrupts. Writing a 1 to a bit in this register will clear the event and the corresponding [RIS.] bit also gets cleared. If the corresponding [IMASK.] bit is set, then the corresponding [MIS.*] register bit also gets cleared.
Type	WO

Bits	Field Name	Description		Type	Reset
31:9	Reserved			RO	0x00 0000
8	MEMRESIFG0	Clear interrupt status for MEMRES0.		WO	0
		Write 0	NO_EFFECT No new data ready.
		Write 1	CLR A new data is ready to be read.
7:5	Reserved			RO	0x0
4	INIFG	Clear INIFG in MIS1 register.		WO	0
		Write 0	NO_EFFECT Interrupt is not pending.
		Write 1	CLR Interrupt is pending.
3	LOWIFG	Clear interrupt flag for the MEMRESx result register being below than the WCLOWx threshold of the window comparator.		WO	0
		Write 0	NO_EFFECT Interrupt is not pending.
		Write 1	CLR Interrupt is pending.
2	HIGHIFG	Clear interrupt flag for the MEMRESx result register being higher than the WCHIGHx threshold of the window comparator.		WO	0
		Write 0	NO_EFFECT Interrupt is not pending.
		Write 1	CLR Interrupt is pending.
1:0	Reserved			RO	0x0

:ADC:IIDX2

Address offset	0x0000 1080
Description	This register provides the highest priority enabled interrupt index. 0x0 means no event pending. Interrupt 1 is the highest priority, 2 next highest, 4, 8, ... 2^31 is the least priority. That is, the least bit position that is set to 1 denotes the highest priority pending interrupt. The priority order is fixed. However, users can implement their own prioritization schemes using other registers that expose the full set of interrupts that have occurred. On each read, only one interrupt is indicated. On a read, the current interrupt (highest priority) is automatically cleared by the hardware and the corresponding interrupt flag in the RIS and MIS are cleared as well. After a read from the CPU (not from the debug interface), the register must be updated with the next highest priority interrupt, if none are pending, then it must display 0x0.
Type	RO

Bits	Field Name	Description		Type	Reset
31:10	Reserved			RO	0x00 0000
9:0	STA	Interrupt index status		RO	0x000
		Read 0x000	NOINTR No bit is set means there is no pending interrupt request
		Read 0x009	MEMRESIFG0 MEMRES0 data loaded interrupt
		Read 0x00A	MEMRESIFG1 MEMRES1 data loaded interrupt
		Read 0x00B	MEMRESIFG2 MEMRES2 data loaded interrupt
		Read 0x00C	MEMRESIFG3 MEMRES3 data loaded interrupt
		Read 0x00D	MEMRESIFG4 Magillem Info : Information not available in the IP-XACT file
		Read 0x00E	MEMRESIFG5 MEMRES5 data loaded interrupt
		Read 0x00F	MEMRESIFG6 MEMRES6 data loaded interrupt
		Read 0x010	MEMRESIFG7 MEMRES7 data loaded interrupt
		Read 0x011	MEMRESIFG8 MEMRES8 data loaded interrupt
		Read 0x012	MEMRESIFG9 MEMRES9 data loaded interrupt
		Read 0x013	MEMRESIFG10 MEMRES10 data loaded interrupt
		Read 0x014	MEMRESIFG11 MEMRES11 data loaded interrupt
		Read 0x015	MEMRESIFG12 MEMRES12 data loaded interrupt
		Read 0x016	MEMRESIFG13 MEMRES13 data loaded interrupt
		Read 0x017	MEMRESIFG14 MEMRES14 data loaded interrupt
		Read 0x018	MEMRESIFG15 MEMRES15 data loaded interrupt

:ADC:IMASK2

Address offset	0x0000 1088
Description	Interrupt mask. This register selects interrupt sources which are allowed to pass from [RIS0.] to [MIS0.] when the corresponding bit-fields are set to 1.
Type	RW

Bits	Field Name	Description		Type	Reset
31:24	Reserved			RO	0x00
23	MEMRESIFG15	MEMRES15 conversion result interrupt mask.		RW	0
		0	CLR No new data ready.
		1	SET A new data is ready to be read.
22	MEMRESIFG14	MEMRES14 conversion result interrupt mask.		RW	0
		0	CLR No new data ready.
		1	SET A new data is ready to be read.
21	MEMRESIFG13	MEMRES13 conversion result interrupt mask.		RW	0
		0	CLR No new data ready.
		1	SET A new data is ready to be read.
20	MEMRESIFG12	MEMRES12 conversion result interrupt mask.		RW	0
		0	CLR No new data ready.
		1	SET A new data is ready to be read.
19	MEMRESIFG11	MEMRES11 conversion result interrupt mask.		RW	0
		0	CLR No new data ready.
		1	SET A new data is ready to be read.
18	MEMRESIFG10	MEMRES10 conversion result interrupt mask.		RW	0
		0	CLR No new data ready.
		1	SET A new data is ready to be read.
17	MEMRESIFG9	MEMRES9 conversion result interrupt mask.		RW	0
		0	CLR No new data ready.
		1	SET A new data is ready to be read.
16	MEMRESIFG8	MEMRES8 conversion result interrupt mask.		RW	0
		0	CLR No new data ready.
		1	SET A new data is ready to be read.
15	MEMRESIFG7	MEMRES7 conversion result interrupt mask.		RW	0
		0	CLR No new data ready.
		1	SET A new data is ready to be read.
14	MEMRESIFG6	MEMRES6 conversion result interrupt mask.		RW	0
		0	CLR No new data ready.
		1	SET A new data is ready to be read.
13	MEMRESIFG5	MEMRES5 conversion result interrupt mask.		RW	0
		0	CLR No new data ready.
		1	SET A new data is ready to be read.
12	MEMRESIFG4	MEMRES4 conversion result interrupt mask.		RW	0
		0	CLR No new data ready.
		1	SET A new data is ready to be read.
11	MEMRESIFG3	MEMRES3 conversion result interrupt mask.		RW	0
		0	CLR No new data ready.
		1	SET A new data is ready to be read.
10	MEMRESIFG2	MEMRES2 conversion result interrupt mask.		RW	0
		0	CLR No new data ready.
		1	SET A new data is ready to be read.
9	MEMRESIFG1	MEMRES1 conversion result interrupt mask.		RW	0
		0	CLR No new data ready.
		1	SET A new data is ready to be read.
8	MEMRESIFG0	MEMRES0 conversion result interrupt mask.		RW	0
		0	CLR No new data ready.
		1	SET A new data is ready to be read.
7:0	Reserved			RO	0x00

:ADC:RIS2

Address offset	0x0000 1090
Description	Raw interrupt status. This register reflects the state of all pending interrupts, regardless of masking. This register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the corresponding [ICLR0.*] register bit.
Type	RO

Bits	Field Name	Description		Type	Reset
31:24	Reserved			RO	0x00
23	MEMRESIFG15	Raw interrupt status for MEMRES15. This bit is set to 1 when MEMRES15 is loaded with a new conversion result. Reading MEMRES15 register will clear this bit, or when the corresponding bit in ICLR2 is set to 1		RO	0
		Read 0	CLR No new data ready.
		Read 1	SET A new data is ready to be read.
22	MEMRESIFG14	Raw interrupt status for MEMRES14. This bit is set to 1 when MEMRES14 is loaded with a new conversion result. Reading MEMRES14 register will clear this bit, or when the corresponding bit in ICLR2 is set to 1		RO	0
		Read 0	CLR No new data ready.
		Read 1	SET A new data is ready to be read.
21	MEMRESIFG13	Raw interrupt status for MEMRES13. This bit is set to 1 when MEMRES13 is loaded with a new conversion result. Reading MEMRES13 register will clear this bit, or when the corresponding bit in ICLR2 is set to 1		RO	0
		Read 0	CLR No new data ready.
		Read 1	SET A new data is ready to be read.
20	MEMRESIFG12	Raw interrupt status for MEMRES12. This bit is set to 1 when MEMRES12 is loaded with a new conversion result. Reading MEMRES12 register will clear this bit, or when the corresponding bit in ICLR2 is set to 1		RO	0
		Read 0	CLR No new data ready.
		Read 1	SET A new data is ready to be read.
19	MEMRESIFG11	Raw interrupt status for MEMRES11. This bit is set to 1 when MEMRES11 is loaded with a new conversion result. Reading MEMRES11 register will clear this bit, or when the corresponding bit in ICLR2 is set to 1		RO	0
		Read 0	CLR No new data ready.
		Read 1	SET A new data is ready to be read.
18	MEMRESIFG10	Raw interrupt status for MEMRES10. This bit is set to 1 when MEMRES10 is loaded with a new conversion result. Reading MEMRES10 register will clear this bit, or when the corresponding bit in ICLR2 is set to 1		RO	0
		Read 0	CLR No new data ready.
		Read 1	SET A new data is ready to be read.
17	MEMRESIFG9	Raw interrupt status for MEMRES9. This bit is set to 1 when MEMRES9 is loaded with a new conversion result. Reading MEMRES9 register will clear this bit, or when the corresponding bit in ICLR2 is set to 1		RO	0
		Read 0	CLR No new data ready.
		Read 1	SET A new data is ready to be read.
16	MEMRESIFG8	Raw interrupt status for MEMRES8. This bit is set to 1 when MEMRES8 is loaded with a new conversion result. Reading MEMRES8 register will clear this bit, or when the corresponding bit in ICLR2 is set to 1		RO	0
		Read 0	CLR No new data ready.
		Read 1	SET A new data is ready to be read.
15	MEMRESIFG7	Raw interrupt status for MEMRES7. This bit is set to 1 when MEMRES7 is loaded with a new conversion result. Reading MEMRES7 register will clear this bit, or when the corresponding bit in ICLR2 is set to 1		RO	0
		Read 0	CLR No new data ready.
		Read 1	SET A new data is ready to be read.
14	MEMRESIFG6	Raw interrupt status for MEMRES6. This bit is set to 1 when MEMRES6 is loaded with a new conversion result. Reading MEMRES6 register will clear this bit, or when the corresponding bit in ICLR2 is set to 1		RO	0
		Read 0	CLR No new data ready.
		Read 1	SET A new data is ready to be read.
13	MEMRESIFG5	Raw interrupt status for MEMRES5. This bit is set to 1 when MEMRES5 is loaded with a new conversion result. Reading MEMRES5 register will clear this bit, or when the corresponding bit in ICLR2 is set to 1		RO	0
		Read 0	CLR No new data ready.
		Read 1	SET A new data is ready to be read.
12	MEMRESIFG4	Raw interrupt status for MEMRES4. This bit is set to 1 when MEMRES4 is loaded with a new conversion result. Reading MEMRES4 register will clear this bit, or when the corresponding bit in ICLR2 is set to 1		RO	0
		Read 0	CLR No new data ready.
		Read 1	SET A new data is ready to be read.
11	MEMRESIFG3	Raw interrupt status for MEMRES3. This bit is set to 1 when MEMRES3 is loaded with a new conversion result. Reading MEMRES3 register will clear this bit, or when the corresponding bit in ICLR2 is set to 1		RO	0
		Read 0	CLR No new data ready.
		Read 1	SET A new data is ready to be read.
10	MEMRESIFG2	Raw interrupt status for MEMRES2. This bit is set to 1 when MEMRES2 is loaded with a new conversion result. Reading MEMRES2 register will clear this bit, or when the corresponding bit in ICLR2 is set to 1		RO	0
		Read 0	CLR No new data ready.
		Read 1	SET A new data is ready to be read.
9	MEMRESIFG1	Raw interrupt status for MEMRES1. This bit is set to 1 when MEMRES1 is loaded with a new conversion result. Reading MEMRES1 register will clear this bit, or when the corresponding bit in ICLR2 is set to 1		RO	0
		Read 0	CLR No new data ready.
		Read 1	SET A new data is ready to be read.
8	MEMRESIFG0	Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. Reading MEMRES0 register will clear this bit, or when the corresponding bit in ICLR2 is set to 1		RO	0
		Read 0	CLR No new data ready.
		Read 1	SET A new data is ready to be read.
7:0	Reserved			RO	0x00

:ADC:MIS2

Address offset	0x0000 1098
Description	Extension of Masked interrupt status. This register is simply a bitwise AND of the contents of [IMASK.] and [RIS.] registers. A flag set in this register can be cleared by writing 1 to the corresponding [ICLR.*] register bit.
Type	RO

Bits	Field Name	Description		Type	Reset
31:24	Reserved			RO	0x00
23	MEMRESIFG15	Masked interrupt status for MEMRES15.		RO	0
		Read 0	CLR No new data ready.
		Read 1	SET A new data is ready to be read.
22	MEMRESIFG14	Masked interrupt status for MEMRES14.		RO	0
		Read 0	CLR No new data ready.
		Read 1	SET A new data is ready to be read.
21	MEMRESIFG13	Masked interrupt status for MEMRES13.		RO	0
		Read 0	CLR No new data ready.
		Read 1	SET A new data is ready to be read.
20	MEMRESIFG12	Masked interrupt status for MEMRES12.		RO	0
		Read 0	CLR No new data ready.
		Read 1	SET A new data is ready to be read.
19	MEMRESIFG11	Masked interrupt status for MEMRES11.		RO	0
		Read 0	CLR No new data ready.
		Read 1	SET A new data is ready to be read.
18	MEMRESIFG10	Masked interrupt status for MEMRES10.		RO	0
		Read 0	CLR No new data ready.
		Read 1	SET A new data is ready to be read.
17	MEMRESIFG9	Masked interrupt status for MEMRES9.		RO	0
		Read 0	CLR No new data ready.
		Read 1	SET A new data is ready to be read.
16	MEMRESIFG8	Masked interrupt status for MEMRES8.		RO	0
		Read 0	CLR No new data ready.
		Read 1	SET A new data is ready to be read.
15	MEMRESIFG7	Masked interrupt status for MEMRES7.		RO	0
		Read 0	CLR No new data ready.
		Read 1	SET A new data is ready to be read.
14	MEMRESIFG6	Masked interrupt status for MEMRES6.		RO	0
		Read 0	CLR No new data ready.
		Read 1	SET A new data is ready to be read.
13	MEMRESIFG5	Masked interrupt status for MEMRES5.		RO	0
		Read 0	CLR No new data ready.
		Read 1	SET A new data is ready to be read.
12	MEMRESIFG4	Masked interrupt status for MEMRES4.		RO	0
		Read 0	CLR No new data ready.
		Read 1	SET A new data is ready to be read.
11	MEMRESIFG3	Masked interrupt status for MEMRES3.		RO	0
		Read 0	CLR No new data ready.
		Read 1	SET A new data is ready to be read.
10	MEMRESIFG2	Masked interrupt status for MEMRES2.		RO	0
		Read 0	CLR No new data ready.
		Read 1	SET A new data is ready to be read.
9	MEMRESIFG1	Masked interrupt status for MEMRES1.		RO	0
		Read 0	CLR No new data ready.
		Read 1	SET A new data is ready to be read.
8	MEMRESIFG0	Masked interrupt status for MEMRES0.		RO	0
		Read 0	CLR No new data ready.
		Read 1	SET A new data is ready to be read.
7:0	Reserved			RO	0x00

:ADC:ISET2

Address offset	0x0000 10A0
Description	Interrupt set register. This register can used by software for diagnostics and safety checking purposes. Writing a 1 to a bit in this register will set the event and the corresponding [RIS.] bit also gets set. If the corresponding [IMASK.] bit is set, then the corresponding [MIS.*] register bit also gets set.
Type	WO

Bits	Field Name	Description		Type	Reset
31:24	Reserved			RO	0x00
23	MEMRESIFG15	Set interrupt status for MEMRES15.		WO	0
		Write 0	NO_EFFECT No new data ready.
		Write 1	SET A new data is ready to be read.
22	MEMRESIFG14	Set interrupt status for MEMRES14.		WO	0
		Write 0	NO_EFFECT No new data ready.
		Write 1	SET A new data is ready to be read.
21	MEMRESIFG13	Set interrupt status for MEMRES13.		WO	0
		Write 0	NO_EFFECT No new data ready.
		Write 1	SET A new data is ready to be read.
20	MEMRESIFG12	Set interrupt status for MEMRES12.		WO	0
		Write 0	NO_EFFECT No new data ready.
		Write 1	SET A new data is ready to be read.
19	MEMRESIFG11	Set interrupt status for MEMRES11.		WO	0
		Write 0	NO_EFFECT No new data ready.
		Write 1	SET A new data is ready to be read.
18	MEMRESIFG10	Set interrupt status for MEMRES10.		WO	0
		Write 0	NO_EFFECT No new data ready.
		Write 1	SET A new data is ready to be read.
17	MEMRESIFG9	Set interrupt status for MEMRES9.		WO	0
		Write 0	NO_EFFECT No new data ready.
		Write 1	SET A new data is ready to be read.
16	MEMRESIFG8	Set interrupt status for MEMRES8.		WO	0
		Write 0	NO_EFFECT No new data ready.
		Write 1	SET A new data is ready to be read.
15	MEMRESIFG7	Set interrupt status for MEMRES7.		WO	0
		Write 0	NO_EFFECT No new data ready.
		Write 1	SET A new data is ready to be read.
14	MEMRESIFG6	Set interrupt status for MEMRES6.		WO	0
		Write 0	NO_EFFECT No new data ready.
		Write 1	SET A new data is ready to be read.
13	MEMRESIFG5	Set interrupt status for MEMRES5.		WO	0
		Write 0	NO_EFFECT No new data ready.
		Write 1	SET A new data is ready to be read.
12	MEMRESIFG4	Set interrupt status for MEMRES4.		WO	0
		Write 0	NO_EFFECT No new data ready.
		Write 1	SET A new data is ready to be read.
11	MEMRESIFG3	Set interrupt status for MEMRES3.		WO	0
		Write 0	NO_EFFECT No new data ready.
		Write 1	SET A new data is ready to be read.
10	MEMRESIFG2	Set interrupt status for MEMRES2.		WO	0
		Write 0	NO_EFFECT No new data ready.
		Write 1	SET A new data is ready to be read.
9	MEMRESIFG1	Set interrupt status for MEMRES1.		WO	0
		Write 0	NO_EFFECT No new data ready.
		Write 1	SET A new data is ready to be read.
8	MEMRESIFG0	Set Interrupt status for MEMRES0.		WO	0
		Write 0	NO_EFFECT No new data ready.
		Write 1	SET A new data is ready to be read.
7:0	Reserved			RO	0x00

:ADC:ICLR2

Address offset	0x0000 10A8
Description	Interrupt clear register. This register allows software to clear interrupts. Writing a 1 to a bit in this register will clear the event and the corresponding [RIS.] bit also gets cleared. If the corresponding [IMASK.] bit is set, then the corresponding [MIS.*] register bit also gets cleared.
Type	WO

Bits	Field Name	Description		Type	Reset
31:24	Reserved			RO	0x00
23	MEMRESIFG15	Clear interrupt status for MEMRES15.		WO	0
		Write 0	NO_EFFECT No new data ready.
		Write 1	CLR A new data is ready to be read.
22	MEMRESIFG14	Clear interrupt status for MEMRES14.		WO	0
		Write 0	NO_EFFECT No new data ready.
		Write 1	CLR A new data is ready to be read.
21	MEMRESIFG13	Clear interrupt status for MEMRES13.		WO	0
		Write 0	NO_EFFECT No new data ready.
		Write 1	CLR A new data is ready to be read.
20	MEMRESIFG12	Clear interrupt status for MEMRES12.		WO	0
		Write 0	NO_EFFECT No new data ready.
		Write 1	CLR A new data is ready to be read.
19	MEMRESIFG11	Clear interrupt status for MEMRES11.		WO	0
		Write 0	NO_EFFECT No new data ready.
		Write 1	CLR A new data is ready to be read.
18	MEMRESIFG10	Clear interrupt status for MEMRES10.		WO	0
		Write 0	NO_EFFECT No new data ready.
		Write 1	CLR A new data is ready to be read.
17	MEMRESIFG9	Clear interrupt status for MEMRES9.		WO	0
		Write 0	NO_EFFECT No new data ready.
		Write 1	CLR A new data is ready to be read.
16	MEMRESIFG8	Clear interrupt status for MEMRES8.		WO	0
		Write 0	NO_EFFECT No new data ready.
		Write 1	CLR A new data is ready to be read.
15	MEMRESIFG7	Clear interrupt status for MEMRES7.		WO	0
		Write 0	NO_EFFECT No new data ready.
		Write 1	CLR A new data is ready to be read.
14	MEMRESIFG6	Clear interrupt status for MEMRES6.		WO	0
		Write 0	NO_EFFECT No new data ready.
		Write 1	CLR A new data is ready to be read.
13	MEMRESIFG5	Clear interrupt status for MEMRES5.		WO	0
		Write 0	NO_EFFECT No new data ready.
		Write 1	CLR A new data is ready to be read.
12	MEMRESIFG4	Clear interrupt status for MEMRES4.		WO	0
		Write 0	NO_EFFECT No new data ready.
		Write 1	CLR A new data is ready to be read.
11	MEMRESIFG3	Clear interrupt status for MEMRES3.		WO	0
		Write 0	NO_EFFECT No new data ready.
		Write 1	CLR A new data is ready to be read.
10	MEMRESIFG2	Clear interrupt status for MEMRES2.		WO	0
		Write 0	NO_EFFECT No new data ready.
		Write 1	CLR A new data is ready to be read.
9	MEMRESIFG1	Clear interrupt status for MEMRES1.		WO	0
		Write 0	NO_EFFECT No new data ready.
		Write 1	CLR A new data is ready to be read.
8	MEMRESIFG0	Clear interrupt status for MEMRES0.		WO	0
		Write 0	NO_EFFECT No new data ready.
		Write 1	CLR A new data is ready to be read.
7:0	Reserved			RO	0x00

:ADC:EVTMODE

Address offset	0x0000 10E0
Description	Event mode register. It is used to select whether each line is disabled, in software mode (software clears the RIS) or in hardware mode (hardware clears the RIS)
Type	RO

Bits	Field Name	Description		Type	Reset
31:4	Reserved			RO	0x000 0000
3:2	EVT1CFG	Event line mode select for event corresponding to INT_EVENT1		RO	0x2
		Read 0x0	DISABLE The interrupt or event line is disabled.
		Read 0x1	SOFTWARE The interrupt or event line is in software mode. Software must clear the RIS.
		Read 0x2	HARDWARE The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag.
1:0	INT0CFG	Event line mode select for event corresponding to INT_EVENT0		RO	0x1
		Read 0x0	DISABLE The interrupt or event line is disabled.
		Read 0x1	SOFTWARE The interrupt or event line is in software mode. Software must clear the RIS.
		Read 0x2	HARDWARE The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag.

:ADC:DESC

Address offset	0x0000 10FC
Description	This register identifies the peripheral and its exact version.
Type	RO

Bits	Field Name	Description		Type	Reset
31:16	MODULEID	Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness.		RO	0x2611
		Read 0x0000	MINIMUM Smallest value
		Read 0xFFFF	MAXIMUM Highest possible value
15:12	FEATUREVER	Feature Set for the module instance		RO	0x0
		Read 0x0	MINIMUM Smallest value
		Read 0xF	MAXIMUM Highest possible value
11:8	INSTNUM	Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances		RO	0x0
7:4	MAJREV	Major rev of the IP		RO	0x1
		Read 0x0	MINIMUM Smallest value
		Read 0xF	MAXIMUM Highest possible value
3:0	MINREV	Minor rev of the IP		RO	0x0
		Read 0x0	MINIMUM Smallest value
		Read 0xF	MAXIMUM Highest possible value

:ADC:CTL0

Address offset	0x0000 1100
Description	Control Register 0
Type	RW

Bits	Field Name	Description		Type	Reset
31:29	Reserved			RO	0x0
28	VDDIOVAL	VDDIO value		RW	0
		0	VDDIO1P8V VDDIO is 1.8V
		1	VDDIO3P3V VDDIO is 3.3V
27	SCAPCLR	Sample Capacitor Clear feature		RW	0
		0	DIS Disable Sample Capacitor Clear feature
		1	EN Enable Sample Capacitor Clear feature. This will add 1 more cycle for every channel conversion.
26:17	Reserved			RO	0x000
16	PWRDN	Power down policy		RW	0
		0	AUTO ADC is powered down on completion of a conversion if there is no pending trigger
		1	MANUAL ADC remains powered on as long as it is enabled through software.
15:1	Reserved			RO	0x0000
0	ENC	Enable conversion		RW	0
		0	OFF Conversion disabled. ENC change from ON to OFF will abort single or repeat sequence on a MEMCTLx boundary. The current conversion will finish and result stored in corresponding MEMRESx.
		1	ON Conversion enabled. ADC sequencer waits for the programmed trigger (software or hardware).

:ADC:CTL1

Address offset	0x0000 1104
Description	Control Register 1
Type	RW

Bits	Field Name	Description		Type	Reset
31	Reserved			RO	0
30:28	AVGD	Hardware averager denominator. The number to divide the accumulated value by (this is a shift). Note results register is maximum of 16-bits long so if not shifted appropirately result will be truncated.		RW	0x0
		0x0	SHIFT0 No shift
		0x1	SHIFT1 1 bit shift
		0x2	SHIFT2 2 bit shift
		0x3	SHIFT3 3 bit shift
		0x4	SHIFT4 4 bit shift
		0x5	SHIFT5 5 bit shift
		0x6	SHIFT6 6 bit shift
		0x7	SHIFT7 7 bit shift
27	Reserved			RO	0
26:24	AVGN	Hardware averager numerator. Selects number of conversions to accumulate for current MEMCTLx and then is get divided by AVGD. Result will be stored in MEMRESx.		RW	0x0
		0x0	DISABLE Disables averager
		0x1	AVG_2 Averages 2 conversions before storing in MEMRESx register
		0x2	AVG_4 Averages 4 conversions before storing in MEMRESx register
		0x3	AVG_8 Averages 8 conversions before storing in MEMRESx register
		0x4	AVG_16 Averages 16 conversions before storing in MEMRESx register
		0x5	AVG_32 Averages 32 conversions before storing in MEMRESx register
		0x6	AVG_64 Averages 64 conversions before storing in MEMRESx register
		0x7	AVG_128 Averages 128 conversions before storing in MEMRESx register
23:18	Reserved			RO	0x00
17:16	CONSEQ	Conversion sequence mode		RW	0x0
		0x0	SINGLE ADC channel in MEMCTLx pointed by STARTADD will be converted once
		0x1	SEQUENCE ADC channel sequence pointed by STARTADD and ENDADD will be converted once
		0x2	REPEATSINGLE ADC channel in MEMCTLx pointed by STARTADD will be converted repeatedly
		0x3	REPEATSEQUENCE ADC channel sequence pointed by STARTADD and ENDADD will be converted repeatedly
15:9	Reserved			RO	0x00
8	SC	Start of conversion		RW	0
		0	STOP When SAMPMODE is set to MANUAL, clearing this bit will end the sample phase and the conversion phase will start. When SAMPMODE is set to AUTO, writing 0 has no effect.
		1	START When SAMPMODE is set to MANUAL, setting this bit will start the sample phase. Sample phase will last as long as this bit is set. When SAMPMODE is set to AUTO, setting this bit will trigger the timer based sample time.
7:1	Reserved			RO	0x00
0	TRIGSRC	Sample trigger source		RW	0
		0	SOFTWARE Software trigger
		1	EVENT Hardware event trigger

:ADC:CTL2

Address offset	0x0000 1108
Description	Control Register 2
Type	RW

Bits	Field Name	Description		Type	Reset
31:29	Reserved			RO	0x0
28:24	ENDADD	Sequence end address. These bits select which MEMCTLx is the last one for the sequence mode. The value of ENDADD is 0x00 to 0x05 corresponding to MEMCTL0 to MEMCTL5.		RW	0x00
		0x00	ADDR_00 MEMCTL0 is selected as end address of sequence.
		0x01	ADDR_01 MEMCTL1 is selected as end address of sequence.
		0x02	ADDR_02 MEMCTL2 is selected as end address of sequence.
		0x03	ADDR_03 MEMCTL3 is selected as end address of sequence.
		0x04	ADDR_04 MEMCTL4 is selected as end address of sequence.
		0x05	ADDR_05 MEMCTL5 is selected as end address of sequence.
23:21	Reserved			RO	0x0
20:16	STARTADD	Sequencer start address. These bits select which MEMCTLx is used for single conversion or as first MEMCTL for sequence mode. The value of STARTADD is 0x00 to 0x05, corresponding to MEMCTL0 to MEMCTL5.		RW	0x00
		0x00	ADDR_00 MEMCTL0 is selected as start address of a sequence or for a single conversion.
		0x01	ADDR_01 MEMCTL1 is selected as start address of a sequence or for a single conversion.
		0x02	ADDR_02 MEMCTL2 is selected as start address of a sequence or for a single conversion.
		0x03	ADDR_03 MEMCTL3 is selected as start address of a sequence or for a single conversion.
		0x04	ADDR_04 MEMCTL4 is selected as start address of a sequence or for a single conversion.
		0x05	ADDR_05 MEMCTL5 is selected as start address of a sequence or for a single conversion.
15:11	Reserved			RO	0x00
10	FIFOEN	Enable FIFO based operation		RW	0
		0	DIS Disable
		1	EN Enable
9	Reserved			RO	0
8	DMAEN	Enable DMA trigger for data transfer. Note: DMAEN bit is cleared by hardware based on DMA done signal at the end of data transfer. Software has to re-enable DMAEN bit for ADC to generate DMA triggers.		RW	0
		0	DIS DMA trigger not enabled
		1	EN DMA trigger enabled
7:3	Reserved			RO	0x00
2:1	RES	Resolution. These bits define the resolutoin of ADC conversion result. Note : A value of 3 defaults to 12-bits resolution.		RW	0x0
		0x0	BIT_12 12-bits resolution
		0x1	BIT_10 10-bits resolution
		0x2	BIT_8 8-bits resolution
0	DF	Data read-back format. Data is always stored in binary unsigned format.		RW	0
		0	UNSIGNED Digital result reads as Binary Unsigned.
		1	SIGNED Digital result reads Signed Binary. (2s complement), left aligned.

:ADC:CTL3

Address offset	0x0000 110C
Description	Control Register 3. This register is used to configure ADC for ad-hoc single conversion.
Type	RW

Bits	Field Name	Description		Type	Reset
31:15	Reserved			RO	0x0 0000
14	ASCFSR	Full Scale Range Selection		RW	0
		0	FSR3P3 Full Scale Range of ADC is up to 3.3V
		1	FSR1P8 Full Scalre Range of ADC is up to 1.8V
13:12	ASCVRSELP	Selects positive voltage reference for ASC operation. VREFM must be connected to on-board ground when external reference option is selected. Note: Writing value 0x3 defaults to INTREF.		RW	0x0
		0x0	VDDIO VDDIO reference
		0x1	EXTREF External reference from AREF+/AREF- pins
		0x2	INTREF Internal reference
11	ASCVRSELM	Selects between External and Internal Ground		RW	0
		0	INTGND Select Internal Ground
		1	EXTGND Select External Ground
10	Reserved			RO	0
9:8	ASCSTIME	ASC sample time compare value select. This is used to select between SCOMP0, SCOMP1 and SCOMP2 registers for ASC operation.		RW	0x0
		0x0	SEL_SCOMP0 Select SCOMP0
		0x1	SEL_SCOMP1 Select SCOMP1
		0x2	SEL_SCOMP2 Select SCOMP2
7:4	Reserved			RO	0x0
3:0	ASCCHSEL	ASC channel select		RW	0x0
		0x0	CHAN_0 Selects channel 0
		0x1	CHAN_1 Selects channel 1
		0x2	CHAN_2 Selects channel 2
		0x3	CHAN_3 Selects channel 3
		0x4	CHAN_4 Selects channel 4
		0x5	CHAN_5 Selects channel 5
		0x6	CHAN_6 Selects channel 6
		0x7	CHAN_7 Selects channel 7
		0x8	CHAN_8 Selects channel 8
		0x9	CHAN_9 Selects channel 9
		0xA	CHAN_10 Selects channel 10
		0xB	CHAN_11 Selects channel 11
		0xC	CHAN_12 Selects channel 12
		0xD	CHAN_13 Selects channel 13
		0xE	CHAN_14 Selects channel 14
		0xF	CHAN_15 Selects channel 15

:ADC:SCOMP0

Address offset	0x0000 1114
Description	Sample time compare 0 register. Specifies the sample time, in number of ADC sample clock cycles. CTL0.ENC must be set to 0 to write to this register.
Type	RW

Bits	Field Name	Description	Type	Reset
31:14	Reserved		RO	0x0 0000
13:0	VAL	Specifies the number of sample clocks. When VAL = 0 or 1, number of sample clocks = Sample clock divide value. When VAL > 1, number of sample clocks = VAL x Sample clock divide value. Note: Sample clock divide value is not the value written to SCLKDIV but the actual divide value (SCLKDIV = 2 implies divide value is 4). Example: VAL = 4, SCLKDIV = 3 implies 32 sample clock cycles.	RW	0x0000

:ADC:SCOMP1

Address offset	0x0000 1118
Description	Sample time compare 1 register. Specifies the sample time, in number of ADC sample clock cycles. CTL0.ENC must be set to 0 to write to this register.
Type	RW

Bits	Field Name	Description	Type	Reset
31:14	Reserved		RO	0x0 0000
13:0	VAL	Specifies the number of sample clocks. When VAL = 0 or 1, number of sample clocks = Sample clock divide value. When VAL > 1, number of sample clocks = VAL x Sample clock divide value. Note: Sample clock divide value is not the value written to SCLKDIV but the actual divide value (SCLKDIV = 2 implies divide value is 4). Example: VAL = 4, SCLKDIV = 3 implies 32 sample clock cycles.	RW	0x0000

:ADC:REFCFG

Address offset	0x0000 111C
Description	Reference buffer configuration register
Type	RW

Bits	Field Name	Description		Type	Reset
31:2	Reserved			RO	0x0000 0000
1	REFVSEL	Configures reference buffer output voltage		RW	0
		0	V1P4 REFBUF generates 1.4V output
		1	V2P5 REFBUF generates 2.5V output
0	REFEN	Reference buffer enable		RW	0
		0	DIS Disable
		1	EN Enable

:ADC:SCOMP2

Address offset	0x0000 1120
Description	Sample time compare 2 register. Specifies the sample time, in number of ADC sample clock cycles. CTL0.ENC must be set to 0 to write to this register.
Type	RW

Bits	Field Name	Description	Type	Reset
31:14	Reserved		RO	0x0 0000
13:0	VAL	Specifies the number of sample clocks. When VAL = 0 or 1, number of sample clocks = Sample clock divide value. When VAL > 1, number of sample clocks = VAL x Sample clock divide value. Note: Sample clock divide value is not the value written to SCLKDIV but the actual divide value (SCLKDIV = 2 implies divide value is 4). Example: VAL = 4, SCLKDIV = 3 implies 32 sample clock cycles.	RW	0x0000

:ADC:WCLOW0

Address offset	0x0000 1148
Description	Window Comparator 0 Low Threshold Register. The data format that is used to write and read WCLOW0 depends on the value of DF bit in CTL2 register. CTL0.ENC must be 0 to write to this register. Note: Change in ADC data format or resolution does not reset WCLOW0.
Type	RW

Bits	Field Name	Description	Type	Reset
31:16	Reserved		RO	0x0000
15:0	DATA	If DF = 0, unsigned binary format has to be used. The value based on the resolution has to be right aligned with the MSB on the left. For 10-bits and 8-bits resolution, unused bits have to be 0s. If DF = 1, 2s-complement format has to be used. The value based on the resolution has to be left aligned with the LSB on the right. For 10-bits and 8-bits resolution, unused bits have to be 0s.	RW	0x0000

:ADC:WCHIGH0

Address offset	0x0000 1150
Description	Window Comparator 0 High Threshold Register. The data format that is used to write and read WCHIGH0 depends on the value of DF bit in CTL2 register. CTL0.ENC must be 0 to write to this register. Note: Change in ADC data format or resolution does not reset WCHIGH0.
Type	RW

Bits	Field Name	Description	Type	Reset
31:16	Reserved		RO	0x0000
15:0	DATA	If DF = 0, unsigned binary format has to be used. The threshold value has to be right aligned, with the MSB on the left. For 10-bits and 8-bits resolution, unused bit have to be 0s. If DF = 1, 2s-complement format has to be used. The value based on the resolution has to be left aligned with the LSB on the right. For 10-bits and 8-bits resolution, unused bit have to be 0s.	RW	0x0000

:ADC:WCLOW1

Address offset	0x0000 1154
Description	Window Comparator 1 Low Threshold Register. The data format that is used to write and read WCLOW1 depends on the value of DF bit in CTL2 register. CTL0.ENC must be 0 to write to this register. Note: Change in ADC data format or resolution does not reset WCLOW1.
Type	RW

Bits	Field Name	Description	Type	Reset
31:16	Reserved		RO	0x0000
15:0	DATA	If DF = 0, unsigned binary format has to be used. The value based on the resolution has to be right aligned with the MSB on the left. For 10-bits and 8-bits resolution, unused bits have to be 0s. If DF = 1, 2s-complement format has to be used. The value based on the resolution has to be left aligned with the LSB on the right. For 10-bits and 8-bits resolution, unused bits have to be 0s.	RW	0x0000

:ADC:WCHIGH1

Address offset	0x0000 1158
Description	Window Comparator 1 High Threshold Register. The data format that is used to write and read WCHIGH1 depends on the value of DF bit in CTL2 register. CTL0.ENC must be 0 to write to this register. Note: Change in ADC data format or resolution does not reset WCHIGH1.
Type	RW

Bits	Field Name	Description	Type	Reset
31:16	Reserved		RO	0x0000
15:0	DATA	If DF = 0, unsigned binary format has to be used. The threshold value has to be right aligned, with the MSB on the left. For 10-bits and 8-bits resolution, unused bit have to be 0s. If DF = 1, 2s-complement format has to be used. The value based on the resolution has to be left aligned with the LSB on the right. For 10-bits and 8-bits resolution, unused bit have to be 0s.	RW	0x0000

:ADC:FIFODATA

Address offset	0x0000 1160
Description	FIFO data register. This is a virtual register used to read from FIFO.
Type	RO

Bits	Field Name	Description			Type	Reset
31:0	DATA	Read from this data field returns the ADC sample from FIFO.			RO	0x0000 0000

:ADC:ASCRES

Address offset	0x0000 1170
Description	ASC result register
Type	RO

Bits	Field Name	Description	Type	Reset
31:16	Reserved		RO	0x0000
15:0	DATA	Result of ADC ad-hoc single conversion. If DF = 0, unsigned binary: The conversion result is right aligned. In 10 and 8 bit modes, the unused MSB bits are forced to 0. If DF = 1, 2s-complement format: The conversion result is left aligned. In 10 and 8 bit modes, the unused LSB bits are forced to 0. The data is stored in the right-justified format and is converted to the left-justified 2s-complement format during read back.	RO	0x0000

:ADC:MEMCTL0

Address offset	0x0000 1180
Description	Conversion Memory Control Register 0. CTL0.ENC must be set to 0 to write to this register.
Type	RW

Bits	Field Name	Description		Type	Reset
31:30	Reserved			RO	0x0
29	FSR	Full Scale Range		RW	0
		0	FSR3P3 FSR is 3.3V
		1	FSR1P8 FSR is 1.8V
28	WINCOMP	Enable window comparator.		RW	0
		0	DIS Disable
		1	EN Enable
27	WCSEL	Window Comparator Selection		RW	0
		0	SEL_WC0 Select SEL_WC0
		1	SEL_WC1 Select WC1
26:25	Reserved			RO	0x0
24	TRG	Trigger policy. Indicates if a trigger will be needed to step to the next MEMCTL in the sequence or to perform next conversion in the case of repeat single channel conversions.		RW	0
		0	AUTO_NEXT Next conversion is automatic
		1	TRIGGER_NEXT Next conversion requires a trigger
23:17	Reserved			RO	0x00
16	AVGEN	Enable hardware averaging.		RW	0
		0	DIS Averaging disabled.
		1	EN Averaging enabled.
15:14	Reserved			RO	0x0
13:12	STIME	Selects the source of sample timer period between SCOMP0, SCOMP1 and SCOMP2.		RW	0x0
		0x0	SEL_SCOMP0 Select SCOMP0
		0x1	SEL_SCOMP1 Select SCOMP1
		0x2	SEL_SCOMP2 Select SCOMP2
11:10	Reserved			RO	0x0
9:8	VRSELP	Selects positive voltage reference for ASC operation. VREFM must be connected to on-board ground when external reference option is selected. Note: Writing value 0x3 defaults to INTREF.		RW	0x0
		0x0	VDDIO VDDIO reference
		0x1	EXTREF External reference from AREF+/AREF- pins
		0x2	INTREF Internal reference
7	VRSELM	Selects between External and Internal Ground		RW	0
		0	INTGND Select Internal Ground
		1	EXTGND Select External Ground
6:4	Reserved			RO	0x0
3:0	CHANSEL	Input channel select.		RW	0x0
		0x0	CHAN_0 Selects channel 0
		0x1	CHAN_1 Selects channel 1
		0x2	CHAN_2 Selects channel 2
		0x3	CHAN_3 Selects channel 3
		0x4	CHAN_4 Selects channel 4
		0x5	CHAN_5 Selects channel 5
		0x6	CHAN_6 Selects channel 6
		0x7	CHAN_7 Selects channel 7
		0x8	CHAN_8 Selects channel 8
		0x9	CHAN_9 Selects channel 9
		0xA	CHAN_10 Selects channel 10
		0xB	CHAN_11 Selects channel 11
		0xC	CHAN_12 Selects channel 12
		0xD	CHAN_13 Selects channel 13
		0xE	CHAN_14 Selects channel 14
		0xF	CHAN_15 Selects channel 15

:ADC:MEMCTL1

Address offset	0x0000 1184
Description	Conversion Memory Control Register 1. CTL0.ENC must be set to 0 to write to this register.
Type	RW

Bits	Field Name	Description		Type	Reset
31:30	Reserved			RO	0x0
29	FSR	Full Scale Range		RW	0
		0	FSR3P3 FSR is 3.3V
		1	FSR1P8 FSR is 1.8V
28	WINCOMP	Enable window comparator.		RW	0
		0	DIS Disable
		1	EN Enable
27	WCSEL	Window Comparator Selection		RW	0
		0	SEL_WC0 Select SEL_WC0
		1	SEL_WC1 Select WC1
26:25	Reserved			RO	0x0
24	TRG	Trigger policy. Indicates if a trigger will be needed to step to the next MEMCTL in the sequence or to perform next conversion in the case of repeat single channel conversions.		RW	0
		0	AUTO_NEXT Next conversion is automatic
		1	TRIGGER_NEXT Next conversion requires a trigger
23:17	Reserved			RO	0x00
16	AVGEN	Enable hardware averaging.		RW	0
		0	DIS Averaging disabled.
		1	EN Averaging enabled.
15:14	Reserved			RO	0x0
13:12	STIME	Selects the source of sample timer period between SCOMP0, SCOMP1 and SCOMP2.		RW	0x0
		0x0	SEL_SCOMP0 Select SCOMP0
		0x1	SEL_SCOMP1 Select SCOMP1
		0x2	SEL_SCOMP2 Select SCOMP2
11:10	Reserved			RO	0x0
9:8	VRSELP	Selects positive voltage reference for ASC operation. VREFM must be connected to on-board ground when external reference option is selected. Note: Writing value 0x3 defaults to INTREF.		RW	0x0
		0x0	VDDIO VDDIO reference
		0x1	EXTREF External reference from AREF+/AREF- pins
		0x2	INTREF Internal reference
7	VRSELM	Selects between External and Internal Ground		RW	0
		0	INTGND Select Internal Ground
		1	EXTGND Select External Ground
6:4	Reserved			RO	0x0
3:0	CHANSEL	Input channel select.		RW	0x0
		0x0	CHAN_0 Selects channel 0
		0x1	CHAN_1 Selects channel 1
		0x2	CHAN_2 Selects channel 2
		0x3	CHAN_3 Selects channel 3
		0x4	CHAN_4 Selects channel 4
		0x5	CHAN_5 Selects channel 5
		0x6	CHAN_6 Selects channel 6
		0x7	CHAN_7 Selects channel 7
		0x8	CHAN_8 Selects channel 8
		0x9	CHAN_9 Selects channel 9
		0xA	CHAN_10 Selects channel 10
		0xB	CHAN_11 Selects channel 11
		0xC	CHAN_12 Selects channel 12
		0xD	CHAN_13 Selects channel 13
		0xE	CHAN_14 Selects channel 14
		0xF	CHAN_15 Selects channel 15

:ADC:MEMCTL2

Address offset	0x0000 1188
Description	Conversion Memory Control Register 2. CTL0.ENC must be set to 0 to write to this register.
Type	RW

Bits	Field Name	Description		Type	Reset
31:30	Reserved			RO	0x0
29	FSR	Full Scale Range		RW	0
		0	FSR3P3 FSR is 3.3V
		1	FSR1P8 FSR is 1.8V
28	WINCOMP	Enable window comparator.		RW	0
		0	DIS Disable
		1	EN Enable
27	WCSEL	Window Comparator Selection		RW	0
		0	SEL_WC0 Select SEL_WC0
		1	SEL_WC1 Select WC1
26:25	Reserved			RO	0x0
24	TRG	Trigger policy. Indicates if a trigger will be needed to step to the next MEMCTL in the sequence or to perform next conversion in the case of repeat single channel conversions.		RW	0
		0	AUTO_NEXT Next conversion is automatic
		1	TRIGGER_NEXT Next conversion requires a trigger
23:17	Reserved			RO	0x00
16	AVGEN	Enable hardware averaging.		RW	0
		0	DIS Averaging disabled.
		1	EN Averaging enabled.
15:14	Reserved			RO	0x0
13:12	STIME	Selects the source of sample timer period between SCOMP0, SCOMP1 and SCOMP2.		RW	0x0
		0x0	SEL_SCOMP0 Select SCOMP0
		0x1	SEL_SCOMP1 Select SCOMP1
		0x2	SEL_SCOMP2 Select SCOMP2
11:10	Reserved			RO	0x0
9:8	VRSELP	Selects positive voltage reference for ASC operation. VREFM must be connected to on-board ground when external reference option is selected. Note: Writing value 0x3 defaults to INTREF.		RW	0x0
		0x0	VDDIO VDDIO reference
		0x1	EXTREF External reference from AREF+/AREF- pins
		0x2	INTREF Internal reference
7	VRSELM	Selects between External and Internal Ground		RW	0
		0	INTGND Select Internal Ground
		1	EXTGND Select External Ground
6:4	Reserved			RO	0x0
3:0	CHANSEL	Input channel select.		RW	0x0
		0x0	CHAN_0 Selects channel 0
		0x1	CHAN_1 Selects channel 1
		0x2	CHAN_2 Selects channel 2
		0x3	CHAN_3 Selects channel 3
		0x4	CHAN_4 Selects channel 4
		0x5	CHAN_5 Selects channel 5
		0x6	CHAN_6 Selects channel 6
		0x7	CHAN_7 Selects channel 7
		0x8	CHAN_8 Selects channel 8
		0x9	CHAN_9 Selects channel 9
		0xA	CHAN_10 Selects channel 10
		0xB	CHAN_11 Selects channel 11
		0xC	CHAN_12 Selects channel 12
		0xD	CHAN_13 Selects channel 13
		0xE	CHAN_14 Selects channel 14
		0xF	CHAN_15 Selects channel 15

:ADC:MEMCTL3

Address offset	0x0000 118C
Description	Conversion Memory Control Register 3. CTL0.ENC must be set to 0 to write to this register.
Type	RW

Bits	Field Name	Description		Type	Reset
31:30	Reserved			RO	0x0
29	FSR	Full Scale Range		RW	0
		0	FSR3P3 FSR is 3.3V
		1	FSR1P8 FSR is 1.8V
28	WINCOMP	Enable window comparator.		RW	0
		0	DIS Disable
		1	EN Enable
27	WCSEL	Window Comparator Selection		RW	0
		0	SEL_WC0 Select SEL_WC0
		1	SEL_WC1 Select WC1
26:25	Reserved			RO	0x0
24	TRG	Trigger policy. Indicates if a trigger will be needed to step to the next MEMCTL in the sequence or to perform next conversion in the case of repeat single channel conversions.		RW	0
		0	AUTO_NEXT Next conversion is automatic
		1	TRIGGER_NEXT Next conversion requires a trigger
23:17	Reserved			RO	0x00
16	AVGEN	Enable hardware averaging.		RW	0
		0	DIS Averaging disabled.
		1	EN Averaging enabled.
15:14	Reserved			RO	0x0
13:12	STIME	Selects the source of sample timer period between SCOMP0, SCOMP1 and SCOMP2.		RW	0x0
		0x0	SEL_SCOMP0 Select SCOMP0
		0x1	SEL_SCOMP1 Select SCOMP1
		0x2	SEL_SCOMP2 Select SCOMP2
11:10	Reserved			RO	0x0
9:8	VRSELP	Selects positive voltage reference for ASC operation. VREFM must be connected to on-board ground when external reference option is selected. Note: Writing value 0x3 defaults to INTREF.		RW	0x0
		0x0	VDDIO VDDIO reference
		0x1	EXTREF External reference from AREF+/AREF- pins
		0x2	INTREF Internal reference
7	VRSELM	Selects between External and Internal Ground		RW	0
		0	INTGND Select Internal Ground
		1	EXTGND Select External Ground
6:4	Reserved			RO	0x0
3:0	CHANSEL	Input channel select.		RW	0x0
		0x0	CHAN_0 Selects channel 0
		0x1	CHAN_1 Selects channel 1
		0x2	CHAN_2 Selects channel 2
		0x3	CHAN_3 Selects channel 3
		0x4	CHAN_4 Selects channel 4
		0x5	CHAN_5 Selects channel 5
		0x6	CHAN_6 Selects channel 6
		0x7	CHAN_7 Selects channel 7
		0x8	CHAN_8 Selects channel 8
		0x9	CHAN_9 Selects channel 9
		0xA	CHAN_10 Selects channel 10
		0xB	CHAN_11 Selects channel 11
		0xC	CHAN_12 Selects channel 12
		0xD	CHAN_13 Selects channel 13
		0xE	CHAN_14 Selects channel 14
		0xF	CHAN_15 Selects channel 15

:ADC:MEMCTL4

Address offset	0x0000 1190
Description	Conversion Memory Control Register 4. CTL0.ENC must be set to 0 to write to this register.
Type	RW

Bits	Field Name	Description		Type	Reset
31:30	Reserved			RO	0x0
29	FSR	Full Scale Range		RW	0
		0	FSR3P3 FSR is 3.3V
		1	FSR1P8 FSR is 1.8V
28	WINCOMP	Enable window comparator.		RW	0
		0	DIS Disable
		1	EN Enable
27	WCSEL	Window Comparator Selection		RW	0
		0	SEL_WC0 Select SEL_WC0
		1	SEL_WC1 Select WC1
26:25	Reserved			RO	0x0
24	TRG	Trigger policy. Indicates if a trigger will be needed to step to the next MEMCTL in the sequence or to perform next conversion in the case of repeat single channel conversions.		RW	0
		0	AUTO_NEXT Next conversion is automatic
		1	TRIGGER_NEXT Next conversion requires a trigger
23:17	Reserved			RO	0x00
16	AVGEN	Enable hardware averaging.		RW	0
		0	DIS Averaging disabled.
		1	EN Averaging enabled.
15:14	Reserved			RO	0x0
13:12	STIME	Selects the source of sample timer period between SCOMP0, SCOMP1 and SCOMP2.		RW	0x0
		0x0	SEL_SCOMP0 Select SCOMP0
		0x1	SEL_SCOMP1 Select SCOMP1
		0x2	SEL_SCOMP2 Select SCOMP2
11:10	Reserved			RO	0x0
9:8	VRSELP	Selects positive voltage reference for ASC operation. VREFM must be connected to on-board ground when external reference option is selected. Note: Writing value 0x3 defaults to INTREF.		RW	0x0
		0x0	VDDIO VDDIO reference
		0x1	EXTREF External reference from AREF+/AREF- pins
		0x2	INTREF Internal reference
7	VRSELM	Selects between External and Internal Ground		RW	0
		0	INTGND Select Internal Ground
		1	EXTGND Select External Ground
6:4	Reserved			RO	0x0
3:0	CHANSEL	Input channel select.		RW	0x0
		0x0	CHAN_0 Selects channel 0
		0x1	CHAN_1 Selects channel 1
		0x2	CHAN_2 Selects channel 2
		0x3	CHAN_3 Selects channel 3
		0x4	CHAN_4 Selects channel 4
		0x5	CHAN_5 Selects channel 5
		0x6	CHAN_6 Selects channel 6
		0x7	CHAN_7 Selects channel 7
		0x8	CHAN_8 Selects channel 8
		0x9	CHAN_9 Selects channel 9
		0xA	CHAN_10 Selects channel 10
		0xB	CHAN_11 Selects channel 11
		0xC	CHAN_12 Selects channel 12
		0xD	CHAN_13 Selects channel 13
		0xE	CHAN_14 Selects channel 14
		0xF	CHAN_15 Selects channel 15

:ADC:MEMCTL5

Address offset	0x0000 1194
Description	Conversion Memory Control Register 5. CTL0.ENC must be set to 0 to write to this register.
Type	RW

Bits	Field Name	Description		Type	Reset
31:30	Reserved			RO	0x0
29	FSR	Full Scale Range		RW	0
		0	FSR3P3 FSR is 3.3V
		1	FSR1P8 FSR is 1.8V
28	WINCOMP	Enable window comparator.		RW	0
		0	DIS Disable
		1	EN Enable
27	WCSEL	Window Comparator Selection		RW	0
		0	SEL_WC0 Select SEL_WC0
		1	SEL_WC1 Select WC1
26:25	Reserved			RO	0x0
24	TRG	Trigger policy. Indicates if a trigger will be needed to step to the next MEMCTL in the sequence or to perform next conversion in the case of repeat single channel conversions.		RW	0
		0	AUTO_NEXT Next conversion is automatic
		1	TRIGGER_NEXT Next conversion requires a trigger
23:17	Reserved			RO	0x00
16	AVGEN	Enable hardware averaging.		RW	0
		0	DIS Averaging disabled.
		1	EN Averaging enabled.
15:14	Reserved			RO	0x0
13:12	STIME	Selects the source of sample timer period between SCOMP0, SCOMP1 and SCOMP2.		RW	0x0
		0x0	SEL_SCOMP0 Select SCOMP0
		0x1	SEL_SCOMP1 Select SCOMP1
		0x2	SEL_SCOMP2 Select SCOMP2
11:10	Reserved			RO	0x0
9:8	VRSELP	Selects positive voltage reference for ASC operation. VREFM must be connected to on-board ground when external reference option is selected. Note: Writing value 0x3 defaults to INTREF.		RW	0x0
		0x0	VDDIO VDDIO reference
		0x1	EXTREF External reference from AREF+/AREF- pins
		0x2	INTREF Internal reference
7	VRSELM	Selects between External and Internal Ground		RW	0
		0	INTGND Select Internal Ground
		1	EXTGND Select External Ground
6:4	Reserved			RO	0x0
3:0	CHANSEL	Input channel select.		RW	0x0
		0x0	CHAN_0 Selects channel 0
		0x1	CHAN_1 Selects channel 1
		0x2	CHAN_2 Selects channel 2
		0x3	CHAN_3 Selects channel 3
		0x4	CHAN_4 Selects channel 4
		0x5	CHAN_5 Selects channel 5
		0x6	CHAN_6 Selects channel 6
		0x7	CHAN_7 Selects channel 7
		0x8	CHAN_8 Selects channel 8
		0x9	CHAN_9 Selects channel 9
		0xA	CHAN_10 Selects channel 10
		0xB	CHAN_11 Selects channel 11
		0xC	CHAN_12 Selects channel 12
		0xD	CHAN_13 Selects channel 13
		0xE	CHAN_14 Selects channel 14
		0xF	CHAN_15 Selects channel 15

:ADC:MEMRES0

Address offset	0x0000 1280
Description	Memory Result Register 0
Type	RO

Bits	Field Name	Description	Type	Reset
31:16	Reserved		RO	0x0000
15:0	DATA	If DF = 0, unsigned binary: The conversion results are right aligned. In 10 and 8 bit modes, the unused MSB bits are forced to 0. If DF = 1, 2s-complement format: The conversion results are left aligned. In 10 and 8 bit modes, the unused LSB bits are forced to 0. The data is stored in the right-justified format and is converted to the left-justified 2s-complement format during read back.	RO	0x0000

:ADC:MEMRES1

Address offset	0x0000 1284
Description	Memory Result Register 1
Type	RO

Bits	Field Name	Description	Type	Reset
31:16	Reserved		RO	0x0000
15:0	DATA	If DF = 0, unsigned binary: The conversion results are right aligned. In 10 and 8 bit modes, the unused MSB bits are forced to 0. If DF = 1, 2s-complement format: The conversion results are left aligned. In 10 and 8 bit modes, the unused LSB bits are forced to 0. The data is stored in the right-justified format and is converted to the left-justified 2s-complement format during read back.	RO	0x0000

:ADC:MEMRES2

Address offset	0x0000 1288
Description	Memory Result Register 2
Type	RO

Bits	Field Name	Description	Type	Reset
31:16	Reserved		RO	0x0000
15:0	DATA	If DF = 0, unsigned binary: The conversion results are right aligned. In 10 and 8 bit modes, the unused MSB bits are forced to 0. If DF = 1, 2s-complement format: The conversion results are left aligned. In 10 and 8 bit modes, the unused LSB bits are forced to 0. The data is stored in the right-justified format and is converted to the left-justified 2s-complement format during read back.	RO	0x0000

:ADC:MEMRES3

Address offset	0x0000 128C
Description	Memory Result Register 3
Type	RO

Bits	Field Name	Description	Type	Reset
31:16	Reserved		RO	0x0000
15:0	DATA	If DF = 0, unsigned binary: The conversion results are right aligned. In 10 and 8 bit modes, the unused MSB bits are forced to 0. If DF = 1, 2s-complement format: The conversion results are left aligned. In 10 and 8 bit modes, the unused LSB bits are forced to 0. The data is stored in the right-justified format and is converted to the left-justified 2s-complement format during read back.	RO	0x0000

:ADC:MEMRES4

Address offset	0x0000 1290
Description	Memory Result Register 4
Type	RO

Bits	Field Name	Description	Type	Reset
31:16	Reserved		RO	0x0000
15:0	DATA	If DF = 0, unsigned binary: The conversion results are right aligned. In 10 and 8 bit modes, the unused MSB bits are forced to 0. If DF = 1, 2s-complement format: The conversion results are left aligned. In 10 and 8 bit modes, the unused LSB bits are forced to 0. The data is stored in the right-justified format and is converted to the left-justified 2s-complement format during read back.	RO	0x0000

:ADC:MEMRES5

Address offset	0x0000 1294
Description	Memory Result Register 5
Type	RO

Bits	Field Name	Description	Type	Reset
31:16	Reserved		RO	0x0000
15:0	DATA	If DF = 0, unsigned binary: The conversion results are right aligned. In 10 and 8 bit modes, the unused MSB bits are forced to 0. If DF = 1, 2s-complement format: The conversion results are left aligned. In 10 and 8 bit modes, the unused LSB bits are forced to 0. The data is stored in the right-justified format and is converted to the left-justified 2s-complement format during read back.	RO	0x0000

:ADC:MEMRES6

Address offset	0x0000 1298
Description	Memory Result Register 6
Type	RO

Bits	Field Name	Description	Type	Reset
31:16	Reserved		RO	0x0000
15:0	DATA	If DF = 0, unsigned binary: The conversion results are right aligned. In 10 and 8 bit modes, the unused MSB bits are forced to 0. If DF = 1, 2s-complement format: The conversion results are left aligned. In 10 and 8 bit modes, the unused LSB bits are forced to 0. The data is stored in the right-justified format and is converted to the left-justified 2s-complement format during read back.	RO	0x0000

:ADC:MEMRES7

Address offset	0x0000 129C
Description	Memory Result Register 7
Type	RO

Bits	Field Name	Description	Type	Reset
31:16	Reserved		RO	0x0000
15:0	DATA	If DF = 0, unsigned binary: The conversion results are right aligned. In 10 and 8 bit modes, the unused MSB bits are forced to 0. If DF = 1, 2s-complement format: The conversion results are left aligned. In 10 and 8 bit modes, the unused LSB bits are forced to 0. The data is stored in the right-justified format and is converted to the left-justified 2s-complement format during read back.	RO	0x0000

:ADC:MEMRES8

Address offset	0x0000 12A0
Description	Memory Result Register 8
Type	RO

Bits	Field Name	Description	Type	Reset
31:16	Reserved		RO	0x0000
15:0	DATA	If DF = 0, unsigned binary: The conversion results are right aligned. In 10 and 8 bit modes, the unused MSB bits are forced to 0. If DF = 1, 2s-complement format: The conversion results are left aligned. In 10 and 8 bit modes, the unused LSB bits are forced to 0. The data is stored in the right-justified format and is converted to the left-justified 2s-complement format during read back.	RO	0x0000

:ADC:MEMRES9

Address offset	0x0000 12A4
Description	Memory Result Register 9
Type	RO

Bits	Field Name	Description	Type	Reset
31:16	Reserved		RO	0x0000
15:0	DATA	If DF = 0, unsigned binary: The conversion results are right aligned. In 10 and 8 bit modes, the unused MSB bits are forced to 0. If DF = 1, 2s-complement format: The conversion results are left aligned. In 10 and 8 bit modes, the unused LSB bits are forced to 0. The data is stored in the right-justified format and is converted to the left-justified 2s-complement format during read back.	RO	0x0000

:ADC:MEMRES10

Address offset	0x0000 12A8
Description	Memory Result Register 10
Type	RO

Bits	Field Name	Description	Type	Reset
31:16	Reserved		RO	0x0000
15:0	DATA	If DF = 0, unsigned binary: The conversion results are right aligned. In 10 and 8 bit modes, the unused MSB bits are forced to 0. If DF = 1, 2s-complement format: The conversion results are left aligned. In 10 and 8 bit modes, the unused LSB bits are forced to 0. The data is stored in the right-justified format and is converted to the left-justified 2s-complement format during read back.	RO	0x0000

:ADC:MEMRES11

Address offset	0x0000 12AC
Description	Memory Result Register 11
Type	RO

Bits	Field Name	Description	Type	Reset
31:16	Reserved		RO	0x0000
15:0	DATA	If DF = 0, unsigned binary: The conversion results are right aligned. In 10 and 8 bit modes, the unused MSB bits are forced to 0. If DF = 1, 2s-complement format: The conversion results are left aligned. In 10 and 8 bit modes, the unused LSB bits are forced to 0. The data is stored in the right-justified format and is converted to the left-justified 2s-complement format during read back.	RO	0x0000

:ADC:MEMRES12

Address offset	0x0000 12B0
Description	Memory Result Register 12
Type	RO

Bits	Field Name	Description	Type	Reset
31:16	Reserved		RO	0x0000
15:0	DATA	If DF = 0, unsigned binary: The conversion results are right aligned. In 10 and 8 bit modes, the unused MSB bits are forced to 0. If DF = 1, 2s-complement format: The conversion results are left aligned. In 10 and 8 bit modes, the unused LSB bits are forced to 0. The data is stored in the right-justified format and is converted to the left-justified 2s-complement format during read back.	RO	0x0000

:ADC:MEMRES13

Address offset	0x0000 12B4
Description	Memory Result Register 13
Type	RO

Bits	Field Name	Description	Type	Reset
31:16	Reserved		RO	0x0000
15:0	DATA	If DF = 0, unsigned binary: The conversion results are right aligned. In 10 and 8 bit modes, the unused MSB bits are forced to 0. If DF = 1, 2s-complement format: The conversion results are left aligned. In 10 and 8 bit modes, the unused LSB bits are forced to 0. The data is stored in the right-justified format and is converted to the left-justified 2s-complement format during read back.	RO	0x0000

:ADC:MEMRES14

Address offset	0x0000 12B8
Description	Memory Result Register 14
Type	RO

Bits	Field Name	Description	Type	Reset
31:16	Reserved		RO	0x0000
15:0	DATA	If DF = 0, unsigned binary: The conversion results are right aligned. In 10 and 8 bit modes, the unused MSB bits are forced to 0. If DF = 1, 2s-complement format: The conversion results are left aligned. In 10 and 8 bit modes, the unused LSB bits are forced to 0. The data is stored in the right-justified format and is converted to the left-justified 2s-complement format during read back.	RO	0x0000

:ADC:MEMRES15

Address offset	0x0000 12BC
Description	Memory Result Register 15
Type	RO

Bits	Field Name	Description	Type	Reset
31:16	Reserved		RO	0x0000
15:0	DATA	If DF = 0, unsigned binary: The conversion results are right aligned. In 10 and 8 bit modes, the unused MSB bits are forced to 0. If DF = 1, 2s-complement format: The conversion results are left aligned. In 10 and 8 bit modes, the unused LSB bits are forced to 0. The data is stored in the right-justified format and is converted to the left-justified 2s-complement format during read back.	RO	0x0000

:ADC:STA

Address offset	0x0000 1340
Description	Status Register
Type	RO

Bits	Field Name	Description		Type	Reset
31:3	Reserved			RO	0x0000 0000
2	ASCACT	ASC active		RO	0
		Read 0	IDLE Idle or done
		Read 1	ACTIVE ASC active
1	Reserved			RO	0
0	BUSY	Busy. This bit indicates that an active ADC sample or conversion operation is in progress.		RO	0
		Read 0	IDLE No ADC sampling or conversion in progress.
		Read 1	ACTIVE ADC sampling or conversion is in progress.

:ADC:TEST0

Address offset	0x0000 1E00
Description	Test 0 register. This is used to select ADC internal analog signals on ATEST0 and ATEST1.
Type	RW

Bits	Field Name	Description		Type	Reset
31	Reserved			RO	0
30	ATEST0_EN	ATEST0 enable.		RW	0
		0	DIS Disable
		1	EN Enable
29	ATEST1_EN	ATEST1 enable.		RW	0
		0	DIS Disable
		1	EN Enable
28:11	Reserved			RO	0x0 0000
10:8	ATEST1_MUXSEL	This is used to select analog signal on ATEST1. The undefined values are reserved and must not be used.		RW	0x0
7:3	Reserved			RO	0x00
2:0	ATEST0_MUXSEL	This is used to select analog signal on ATEST0. The undefined values are reserved and must not be used.		RW	0x0

:ADC:TEST1

Address offset	0x0000 1E04
Description	Test 1 register. This is used to select ADC internal signals on DTB.
Type	RW

Bits	Field Name	Description	Type	Reset
31:5	Reserved		RO	0x000 0000
4:0	DTB_MUXSEL	DTB mux select.	RW	0x00

:ADC:TEST2

Address offset	0x0000 1E08
Description	Test 1 register. This is used to select ADC internal signals on DTB.
Type	RW

Bits	Field Name	Description	Type	Reset
31:8	Reserved		RO	0x00 0000
7:5	SPARE	Spare bits	RW	0x0
4:2	CMPCLK	Comparator clock and CDAC clock control	RW	0x0
1	BOOSTENZ	Boost Enable	RW	0
0	CPTESTEN	Charge Pump Test Enable	RW	0

:ADC:TEST3

Address offset	0x0000 1E0C
Description	ADC CAL Accumulation Register
Type	RW

Bits	Field Name	Description			Type	Reset
31:0	CAL_ACUML	Accumulation of # samples during Calibration step			RW	0x0000 0000

:ADC:TEST4

Address offset	0x0000 1E10
Description	CAL Control register: Average Sample count, Step number, Recal En and Debug option to override ull_usc_ulpadchp_dft_i<26:0>.
Type	RW

Bits	Field Name	Description	Type	Reset
31	HW_STEP_SEL_DIS	By Enabling this bit, DLC written value overwritten of ull_usc_ulpadchp_dft_i<26:0> from TEST5 regsiter. This is for debug.	RW	0
30:25	Reserved		RO	0x00
24	CAL_MODE_EN	ADC CDAC Calibration mode enable	RW	0
23:22	Reserved		RO	0x0
21:16	CAL_STEP_SEL	ADC CAL STEP SELECTION	RW	0x00
15:0	Reserved		RO	0x0000

:ADC:TEST5

Address offset	0x0000 1E14
Description	This regsiter updated ull_usc_ulpadchp_dft_i[26:0] value if Test 5: HW_STEP_SEL_DIS bit enable
Type	RW

Bits	Field Name	Description	Type	Reset
31:10	Reserved		RO	0x00 0000
9:0	CAL_CAP_CTL	This regsiter updated ull_usc_ulpadchp_dft_i[26:0] value if Test 5: HW_STEP_SEL_DIS bit enabled ull_usc_ulpadchp_dft_i[26:0]	RW	0x000

:ADC:TEST6

Address offset	0x0000 1E18
Description	Test 6 register. This register is used to hold static trim values.
Type	RW

Bits	Field Name	Description	Type	Reset
31:10	Reserved		RO	0x00 0000
9	SPARE	Spare bits	RW	0
8	RCEN	REFBUF RC Filter enable	RW	0
7:6	RESPROG	Resistor programmability to adjust REFBUF settling time	RW	0x0
5:4	IBPROG	Increase bias current in REFBUF for higher bandwidth	RW	0x0
3:2	CMPDLY	Comparator delay programmability	RW	0x0
1:0	CMPIBIAS	ADC comparator Ibias programmability	RW	0x0

:ADC:TEST7

Address offset	0x0000 1E1C
Description	Test 7 register. This register is used the configuration/output values of lower 32 CDAC trim bits.
Type	RW

Bits	Field Name	Description			Type	Reset
31:0	CFG0	Lower 32 bits of CDAC trim configuration. Post trim mapping, this would be overwritten with lower 32 CDAC trim bits driven to MSIP			RW	0x0000 0000

:ADC:TEST8

Address offset	0x0000 1E20
Description	Test 8 register. This register is used the configuration/output values of middle 32 CDAC trim bits.
Type	RW

Bits	Field Name	Description			Type	Reset
31:0	CFG1	Middle 32 bits of CDAC trim configuration. Post trim mapping, this would be overwritten with middle 32 CDAC trim bits driven to MSIP			RW	0x0000 0000

:ADC:TEST9

Address offset	0x0000 1E24
Description	Test 9 register. This register is used the configuration/output values of upper 32 CDAC trim bits.
Type	RW

Bits	Field Name	Description	Type	Reset
31:5	Reserved		RO	0x000 0000
4:0	CFG2	Upper 5 bits of CDAC trim configuration. Post trim mapping, this would be overwritten with upper 5 CDAC trim bits driven to MSIP	RW	0x00

:ADC:TEST10

Address offset	0x0000 1E28
Description	Test 10 register. This register is used to override the fuse bits and use values in TEST7/TEST8/TEST9 as CDAC trims.
Type	RW

Bits	Field Name	Description		Type	Reset
31:10	Reserved			RO	0x00 0000
9:0	FUSEOVRD	Override fuse bits		RW	0x000
		0x001	CM11 CM11 CDAC capacitor trim will be driven with the value in TEST7[6:0].
		0x002	CM10 CM11 CDAC capacitor trim will be driven with the value in TEST7[13:7].
		0x100	CBAL CBAL CDAC capacitor trim will be driven with the value in TEST9[30:24].
		0x200	OFFSET Offset trims will be driven with values in {TEST9.CFG2[4:0], TEST8.CFG1[31]}

:ADC:TEST11

Address offset	0x0000 1E2C
Description	Test 11 register. This register holds the fuse values used for CDAC trims.
Type	RW

Bits	Field Name	Description			Type	Reset
31:0	FUSE	CDAC trim values stored in fuse			RW	0x0000 0000

:ADC:TEST12

Address offset	0x0000 1E30
Description	Test 12 register. This register holds the override enable and override values for channel select signal
Type	RW

Bits	Field Name	Description	Type	Reset
31:6	Reserved		RO	0x000 0000
5:3	OVRDVAL	Override value for channel select. Bit 0 for channel 12, Bit 1 for channel 13 and Bit 2 reserved for future use.	RW	0x0
2:0	OVRDEN	Override enable for channel select. Bit 0 for channel 12, Bit 1 for channel 13 and Bit 2 reserved for future use.	RW	0x0

:ADC:FCLKCFG

Address offset	0x0000 1F14
Description	Functional Clock Configuration Register
Type	RW

Bits	Field Name	Description		Type	Reset
31:19	Reserved			RO	0x0000
18	ADCFCLKEN	ADC Functional Clock Enable		RW	0
		0	DIS Clock is disabled
		1	EN Clock is enabled
17	Reserved			RO	0
16	ADCFCLKSEL	ADC Functional Clock Selection		RW	0
		0	PLL PLL Clock
		1	HFXT HFXT Clock
15	Reserved			RO	0
14	EXTREFMASK	Masks External Reference selection while generating clock. Generates conversion clock with frequency designed for internal reference voltage.		RW	0
		0	HFXT52M HFXT Frequency is 52MHz
		1	HFXT40M HFXT Frequency is 40MHz
13	INTREFMASK	Masks Internal Reference selection while generating clock. Generates conversion clock with frequency designed for EXTREF/VDDIO references.		RW	0
		0	DIS Internal Reference selection is not masked
		1	EN Mask Internal Reference Selection
12:0	Reserved			RO	0x0000

:ADC:CLK_EN

Address offset	0x0000 2000
Description
Type	RW

Bits	Field Name	Description		Type	Reset
31:1	Reserved			RO	0x0000 0000
0	CLK_EN_STATUS	Clock Enable		RW	0
		0	DIS Disable ADC Clock
		1	EN Enable ADC Clock