TI Cortex-M4 Timing Benchmarks

Target Platform: ti.platforms.simplelink:CC3220SF:1

Tool Chain Version: 20.2.0

BIOS Version: bios_6_81_00_03_eng

XDCTools Version: xdctools_3_61_00_16_core

Benchmark	Cycles
Interrupt Latency	181
Hwi_restore()	19
Hwi_disable()	26
Hwi dispatcher prolog	146
Hwi dispatcher epilog	324
Hwi dispatcher	465
Hardware Interrupt to Blocked Task	760
Hardware Interrupt to Software Interrupt	511
Swi_enable()	113
Swi_disable()	26
Post Software Interrupt Again	51
Post Software Interrupt without Context Switch	135
Post Software Interrupt with Context Switch	274
Create a New Task without Context Switch	4004
Set a Task Priority without a Context Switch	261
Task_yield()	277
Post Semaphore No Waiting Task	140
Post Semaphore No Task Switch	263
Post Semaphore with Task Switch	353
Pend on Semaphore No Context Switch	123
Pend on Semaphore with Task Switch	413
Clock_getTicks()	24
POSIX Create a New Task without Context Switch	7498
POSIX Set a Task Priority without a Context Switch	341
POSIX Post Semaphore No Waiting Task	165
POSIX Post Semaphore No Task Switch	292
POSIX Post Semaphore with Task Switch	384
POSIX Pend on Semaphore No Context Switch	140
POSIX Pend on Semaphore with Task Switch	442

The benchmark application was built using BIOS.LibType_Custom with the following BIOS.customCCOpts settings: “–endian=little -mv7M4 –float_support=vfplib –abi=eabi -q -ms –opt_for_speed=2 –program_level_compile -o3”.

To minimize the effects of wait states, the performance measurements are collected at optimal CPU clock speeds on MSP432 and Tiva devices.

See the SYS/BIOS User’s Guide for more information regarding how interrupt latency is calculated.