IAR Cortex-M4 Timing Benchmarks

Target Platform: ti.platforms.simplelink:CC3220SF:1

Tool Chain Version: 8.50.1.245

BIOS Version: bios_6_81_00_03_eng

XDCTools Version: xdctools_3_61_00_16_core

Benchmark	Cycles
Interrupt Latency	223
Hwi_restore()	26
Hwi_disable()	28
Hwi dispatcher prolog	186
Hwi dispatcher epilog	371
Hwi dispatcher	536
Hardware Interrupt to Blocked Task	851
Hardware Interrupt to Software Interrupt	565
Swi_enable()	128
Swi_disable()	35
Post Software Interrupt Again	32
Post Software Interrupt without Context Switch	131
Post Software Interrupt with Context Switch	282
Create a New Task without Context Switch	3784
Set a Task Priority without a Context Switch	282
Task_yield()	324
Post Semaphore No Waiting Task	125
Post Semaphore No Task Switch	288
Post Semaphore with Task Switch	379
Pend on Semaphore No Context Switch	100
Pend on Semaphore with Task Switch	423
Clock_getTicks()	31
POSIX Create a New Task without Context Switch	6949
POSIX Set a Task Priority without a Context Switch	370
POSIX Post Semaphore No Waiting Task	159
POSIX Post Semaphore No Task Switch	322
POSIX Post Semaphore with Task Switch	408
POSIX Pend on Semaphore No Context Switch	81
POSIX Pend on Semaphore with Task Switch	439

The M4 target also supports zero latency interrupts. See ti.sysbios.family.arm.m3.Hwi CDOCs for details.

See the SYS/BIOS User’s Guide for more information regarding how interrupt latency is calculated.