IAR Cortex-M4 with hard FP Timing Benchmarks

Target Platform: ti.platforms.msp432:MSP432E401Y

Tool Chain Version: 8.50.1.245

BIOS Version: bios_6_81_00_03_eng

XDCTools Version: xdctools_3_61_00_16_core

Benchmark	Cycles
Interrupt Latency	193
Hwi_restore()	11
Hwi_disable()	12
Hwi dispatcher prolog	134
Hwi dispatcher epilog	238
Hwi dispatcher	360
Hardware Interrupt to Blocked Task	564
Hardware Interrupt to Software Interrupt	367
Swi_enable()	65
Swi_disable()	19
Post Software Interrupt Again	21
Post Software Interrupt without Context Switch	90
Post Software Interrupt with Context Switch	181
Create a New Task without Context Switch	2182
Set a Task Priority without a Context Switch	162
Task_yield()	232
Post Semaphore No Waiting Task	70
Post Semaphore No Task Switch	176
Post Semaphore with Task Switch	270
Pend on Semaphore No Context Switch	62
Pend on Semaphore with Task Switch	295
Clock_getTicks()	12
POSIX Create a New Task without Context Switch	3943
POSIX Set a Task Priority without a Context Switch	207
POSIX Post Semaphore No Waiting Task	86
POSIX Post Semaphore No Task Switch	194
POSIX Post Semaphore with Task Switch	280
POSIX Pend on Semaphore No Context Switch	55
POSIX Pend on Semaphore with Task Switch	302

The M4F target also supports zero latency interrupts. See ti.sysbios.family.arm.m3.Hwi cdocs for details.

See the SYS/BIOS User’s Guide for more information regarding how interrupt latency is calculated.