GCC Cortex-M4 with hard FP Timing Benchmarks

Target Platform: ti.platforms.msp432:MSP432E401Y

Tool Chain Version: 9.2.1

BIOS Version: bios_6_81_00_03_eng

XDCTools Version: xdctools_3_61_00_16_core

Benchmark	Cycles
Interrupt Latency	301
Hwi_restore()	9
Hwi_disable()	12
Hwi dispatcher prolog	164
Hwi dispatcher epilog	269
Hwi dispatcher	426
Hardware Interrupt to Blocked Task	725
Hardware Interrupt to Software Interrupt	467
Swi_enable()	78
Swi_disable()	19
Post Software Interrupt Again	34
Post Software Interrupt without Context Switch	93
Post Software Interrupt with Context Switch	213
Create a New Task without Context Switch	3428
Set a Task Priority without a Context Switch	188
Task_yield()	289
Post Semaphore No Waiting Task	110
Post Semaphore No Task Switch	261
Post Semaphore with Task Switch	376
Pend on Semaphore No Context Switch	74
Pend on Semaphore with Task Switch	408
Clock_getTicks()	14
POSIX Create a New Task without Context Switch	6717
POSIX Set a Task Priority without a Context Switch	258
POSIX Post Semaphore No Waiting Task	119
POSIX Post Semaphore No Task Switch	274
POSIX Post Semaphore with Task Switch	393
POSIX Pend on Semaphore No Context Switch	89
POSIX Pend on Semaphore with Task Switch	426

The benchmark application was built using BIOS.LibType_Custom with the following BIOS.customCCOpts settings:

“-mcpu=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16 -mabi=aapcs -O3 -Wunused -Wunknown-pragmas -ffunction-sections -fdata-sections -Dti_sysbios_Build_useHwiMacros -Dfar= -D__DYNAMIC_REENT__”.

The M4F target also supports zero latency interrupts. See ti.sysbios.family.arm.m3.Hwi cdocs for details.

See the SYS/BIOS User’s Guide for more information regarding how interrupt latency is calculated.