MSP432E4 DriverLib API Guide  1.11.00.03
hw_pwm.h
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1 //*****************************************************************************
2 //
3 // hw_pwm.h - Defines and Macros for Pulse Width Modulation (PWM) ports.
4 //
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37 
38 #ifndef __HW_PWM_H__
39 #define __HW_PWM_H__
40 
41 //*****************************************************************************
42 //
43 // The following are defines for the PWM register offsets.
44 //
45 //*****************************************************************************
46 #define PWM_O_CTL 0x00000000 // PWM Master Control
47 #define PWM_O_SYNC 0x00000004 // PWM Time Base Sync
48 #define PWM_O_ENABLE 0x00000008 // PWM Output Enable
49 #define PWM_O_INVERT 0x0000000C // PWM Output Inversion
50 #define PWM_O_FAULT 0x00000010 // PWM Output Fault
51 #define PWM_O_INTEN 0x00000014 // PWM Interrupt Enable
52 #define PWM_O_RIS 0x00000018 // PWM Raw Interrupt Status
53 #define PWM_O_ISC 0x0000001C // PWM Interrupt Status and Clear
54 #define PWM_O_STATUS 0x00000020 // PWM Status
55 #define PWM_O_FAULTVAL 0x00000024 // PWM Fault Condition Value
56 #define PWM_O_ENUPD 0x00000028 // PWM Enable Update
57 #define PWM_O_0_CTL 0x00000040 // PWM0 Control
58 #define PWM_O_0_INTEN 0x00000044 // PWM0 Interrupt and Trigger
59  // Enable
60 #define PWM_O_0_RIS 0x00000048 // PWM0 Raw Interrupt Status
61 #define PWM_O_0_ISC 0x0000004C // PWM0 Interrupt Status and Clear
62 #define PWM_O_0_LOAD 0x00000050 // PWM0 Load
63 #define PWM_O_0_COUNT 0x00000054 // PWM0 Counter
64 #define PWM_O_0_CMPA 0x00000058 // PWM0 Compare A
65 #define PWM_O_0_CMPB 0x0000005C // PWM0 Compare B
66 #define PWM_O_0_GENA 0x00000060 // PWM0 Generator A Control
67 #define PWM_O_0_GENB 0x00000064 // PWM0 Generator B Control
68 #define PWM_O_0_DBCTL 0x00000068 // PWM0 Dead-Band Control
69 #define PWM_O_0_DBRISE 0x0000006C // PWM0 Dead-Band Rising-Edge Delay
70 #define PWM_O_0_DBFALL 0x00000070 // PWM0 Dead-Band
71  // Falling-Edge-Delay
72 #define PWM_O_0_FLTSRC0 0x00000074 // PWM0 Fault Source 0
73 #define PWM_O_0_FLTSRC1 0x00000078 // PWM0 Fault Source 1
74 #define PWM_O_0_MINFLTPER 0x0000007C // PWM0 Minimum Fault Period
75 #define PWM_O_1_CTL 0x00000080 // PWM1 Control
76 #define PWM_O_1_INTEN 0x00000084 // PWM1 Interrupt and Trigger
77  // Enable
78 #define PWM_O_1_RIS 0x00000088 // PWM1 Raw Interrupt Status
79 #define PWM_O_1_ISC 0x0000008C // PWM1 Interrupt Status and Clear
80 #define PWM_O_1_LOAD 0x00000090 // PWM1 Load
81 #define PWM_O_1_COUNT 0x00000094 // PWM1 Counter
82 #define PWM_O_1_CMPA 0x00000098 // PWM1 Compare A
83 #define PWM_O_1_CMPB 0x0000009C // PWM1 Compare B
84 #define PWM_O_1_GENA 0x000000A0 // PWM1 Generator A Control
85 #define PWM_O_1_GENB 0x000000A4 // PWM1 Generator B Control
86 #define PWM_O_1_DBCTL 0x000000A8 // PWM1 Dead-Band Control
87 #define PWM_O_1_DBRISE 0x000000AC // PWM1 Dead-Band Rising-Edge Delay
88 #define PWM_O_1_DBFALL 0x000000B0 // PWM1 Dead-Band
89  // Falling-Edge-Delay
90 #define PWM_O_1_FLTSRC0 0x000000B4 // PWM1 Fault Source 0
91 #define PWM_O_1_FLTSRC1 0x000000B8 // PWM1 Fault Source 1
92 #define PWM_O_1_MINFLTPER 0x000000BC // PWM1 Minimum Fault Period
93 #define PWM_O_2_CTL 0x000000C0 // PWM2 Control
94 #define PWM_O_2_INTEN 0x000000C4 // PWM2 Interrupt and Trigger
95  // Enable
96 #define PWM_O_2_RIS 0x000000C8 // PWM2 Raw Interrupt Status
97 #define PWM_O_2_ISC 0x000000CC // PWM2 Interrupt Status and Clear
98 #define PWM_O_2_LOAD 0x000000D0 // PWM2 Load
99 #define PWM_O_2_COUNT 0x000000D4 // PWM2 Counter
100 #define PWM_O_2_CMPA 0x000000D8 // PWM2 Compare A
101 #define PWM_O_2_CMPB 0x000000DC // PWM2 Compare B
102 #define PWM_O_2_GENA 0x000000E0 // PWM2 Generator A Control
103 #define PWM_O_2_GENB 0x000000E4 // PWM2 Generator B Control
104 #define PWM_O_2_DBCTL 0x000000E8 // PWM2 Dead-Band Control
105 #define PWM_O_2_DBRISE 0x000000EC // PWM2 Dead-Band Rising-Edge Delay
106 #define PWM_O_2_DBFALL 0x000000F0 // PWM2 Dead-Band
107  // Falling-Edge-Delay
108 #define PWM_O_2_FLTSRC0 0x000000F4 // PWM2 Fault Source 0
109 #define PWM_O_2_FLTSRC1 0x000000F8 // PWM2 Fault Source 1
110 #define PWM_O_2_MINFLTPER 0x000000FC // PWM2 Minimum Fault Period
111 #define PWM_O_3_CTL 0x00000100 // PWM3 Control
112 #define PWM_O_3_INTEN 0x00000104 // PWM3 Interrupt and Trigger
113  // Enable
114 #define PWM_O_3_RIS 0x00000108 // PWM3 Raw Interrupt Status
115 #define PWM_O_3_ISC 0x0000010C // PWM3 Interrupt Status and Clear
116 #define PWM_O_3_LOAD 0x00000110 // PWM3 Load
117 #define PWM_O_3_COUNT 0x00000114 // PWM3 Counter
118 #define PWM_O_3_CMPA 0x00000118 // PWM3 Compare A
119 #define PWM_O_3_CMPB 0x0000011C // PWM3 Compare B
120 #define PWM_O_3_GENA 0x00000120 // PWM3 Generator A Control
121 #define PWM_O_3_GENB 0x00000124 // PWM3 Generator B Control
122 #define PWM_O_3_DBCTL 0x00000128 // PWM3 Dead-Band Control
123 #define PWM_O_3_DBRISE 0x0000012C // PWM3 Dead-Band Rising-Edge Delay
124 #define PWM_O_3_DBFALL 0x00000130 // PWM3 Dead-Band
125  // Falling-Edge-Delay
126 #define PWM_O_3_FLTSRC0 0x00000134 // PWM3 Fault Source 0
127 #define PWM_O_3_FLTSRC1 0x00000138 // PWM3 Fault Source 1
128 #define PWM_O_3_MINFLTPER 0x0000013C // PWM3 Minimum Fault Period
129 #define PWM_O_0_FLTSEN 0x00000800 // PWM0 Fault Pin Logic Sense
130 #define PWM_O_0_FLTSTAT0 0x00000804 // PWM0 Fault Status 0
131 #define PWM_O_0_FLTSTAT1 0x00000808 // PWM0 Fault Status 1
132 #define PWM_O_1_FLTSEN 0x00000880 // PWM1 Fault Pin Logic Sense
133 #define PWM_O_1_FLTSTAT0 0x00000884 // PWM1 Fault Status 0
134 #define PWM_O_1_FLTSTAT1 0x00000888 // PWM1 Fault Status 1
135 #define PWM_O_2_FLTSEN 0x00000900 // PWM2 Fault Pin Logic Sense
136 #define PWM_O_2_FLTSTAT0 0x00000904 // PWM2 Fault Status 0
137 #define PWM_O_2_FLTSTAT1 0x00000908 // PWM2 Fault Status 1
138 #define PWM_O_3_FLTSEN 0x00000980 // PWM3 Fault Pin Logic Sense
139 #define PWM_O_3_FLTSTAT0 0x00000984 // PWM3 Fault Status 0
140 #define PWM_O_3_FLTSTAT1 0x00000988 // PWM3 Fault Status 1
141 #define PWM_O_PP 0x00000FC0 // PWM Peripheral Properties
142 #define PWM_O_CC 0x00000FC8 // PWM Clock Configuration
143 
144 //*****************************************************************************
145 //
146 // The following are defines for the bit fields in the PWM_O_CTL register.
147 //
148 //*****************************************************************************
149 #define PWM_CTL_GLOBALSYNC3 0x00000008 // Update PWM Generator 3
150 #define PWM_CTL_GLOBALSYNC2 0x00000004 // Update PWM Generator 2
151 #define PWM_CTL_GLOBALSYNC1 0x00000002 // Update PWM Generator 1
152 #define PWM_CTL_GLOBALSYNC0 0x00000001 // Update PWM Generator 0
153 
154 //*****************************************************************************
155 //
156 // The following are defines for the bit fields in the PWM_O_SYNC register.
157 //
158 //*****************************************************************************
159 #define PWM_SYNC_SYNC3 0x00000008 // Reset Generator 3 Counter
160 #define PWM_SYNC_SYNC2 0x00000004 // Reset Generator 2 Counter
161 #define PWM_SYNC_SYNC1 0x00000002 // Reset Generator 1 Counter
162 #define PWM_SYNC_SYNC0 0x00000001 // Reset Generator 0 Counter
163 
164 //*****************************************************************************
165 //
166 // The following are defines for the bit fields in the PWM_O_ENABLE register.
167 //
168 //*****************************************************************************
169 #define PWM_ENABLE_PWM7EN 0x00000080 // MnPWM7 Output Enable
170 #define PWM_ENABLE_PWM6EN 0x00000040 // MnPWM6 Output Enable
171 #define PWM_ENABLE_PWM5EN 0x00000020 // MnPWM5 Output Enable
172 #define PWM_ENABLE_PWM4EN 0x00000010 // MnPWM4 Output Enable
173 #define PWM_ENABLE_PWM3EN 0x00000008 // MnPWM3 Output Enable
174 #define PWM_ENABLE_PWM2EN 0x00000004 // MnPWM2 Output Enable
175 #define PWM_ENABLE_PWM1EN 0x00000002 // MnPWM1 Output Enable
176 #define PWM_ENABLE_PWM0EN 0x00000001 // MnPWM0 Output Enable
177 
178 //*****************************************************************************
179 //
180 // The following are defines for the bit fields in the PWM_O_INVERT register.
181 //
182 //*****************************************************************************
183 #define PWM_INVERT_PWM7INV 0x00000080 // Invert MnPWM7 Signal
184 #define PWM_INVERT_PWM6INV 0x00000040 // Invert MnPWM6 Signal
185 #define PWM_INVERT_PWM5INV 0x00000020 // Invert MnPWM5 Signal
186 #define PWM_INVERT_PWM4INV 0x00000010 // Invert MnPWM4 Signal
187 #define PWM_INVERT_PWM3INV 0x00000008 // Invert MnPWM3 Signal
188 #define PWM_INVERT_PWM2INV 0x00000004 // Invert MnPWM2 Signal
189 #define PWM_INVERT_PWM1INV 0x00000002 // Invert MnPWM1 Signal
190 #define PWM_INVERT_PWM0INV 0x00000001 // Invert MnPWM0 Signal
191 
192 //*****************************************************************************
193 //
194 // The following are defines for the bit fields in the PWM_O_FAULT register.
195 //
196 //*****************************************************************************
197 #define PWM_FAULT_FAULT7 0x00000080 // MnPWM7 Fault
198 #define PWM_FAULT_FAULT6 0x00000040 // MnPWM6 Fault
199 #define PWM_FAULT_FAULT5 0x00000020 // MnPWM5 Fault
200 #define PWM_FAULT_FAULT4 0x00000010 // MnPWM4 Fault
201 #define PWM_FAULT_FAULT3 0x00000008 // MnPWM3 Fault
202 #define PWM_FAULT_FAULT2 0x00000004 // MnPWM2 Fault
203 #define PWM_FAULT_FAULT1 0x00000002 // MnPWM1 Fault
204 #define PWM_FAULT_FAULT0 0x00000001 // MnPWM0 Fault
205 
206 //*****************************************************************************
207 //
208 // The following are defines for the bit fields in the PWM_O_INTEN register.
209 //
210 //*****************************************************************************
211 #define PWM_INTEN_INTFAULT3 0x00080000 // Interrupt Fault 3
212 #define PWM_INTEN_INTFAULT2 0x00040000 // Interrupt Fault 2
213 #define PWM_INTEN_INTFAULT1 0x00020000 // Interrupt Fault 1
214 #define PWM_INTEN_INTFAULT0 0x00010000 // Interrupt Fault 0
215 #define PWM_INTEN_INTPWM3 0x00000008 // PWM3 Interrupt Enable
216 #define PWM_INTEN_INTPWM2 0x00000004 // PWM2 Interrupt Enable
217 #define PWM_INTEN_INTPWM1 0x00000002 // PWM1 Interrupt Enable
218 #define PWM_INTEN_INTPWM0 0x00000001 // PWM0 Interrupt Enable
219 
220 //*****************************************************************************
221 //
222 // The following are defines for the bit fields in the PWM_O_RIS register.
223 //
224 //*****************************************************************************
225 #define PWM_RIS_INTFAULT3 0x00080000 // Interrupt Fault PWM 3
226 #define PWM_RIS_INTFAULT2 0x00040000 // Interrupt Fault PWM 2
227 #define PWM_RIS_INTFAULT1 0x00020000 // Interrupt Fault PWM 1
228 #define PWM_RIS_INTFAULT0 0x00010000 // Interrupt Fault PWM 0
229 #define PWM_RIS_INTPWM3 0x00000008 // PWM3 Interrupt Asserted
230 #define PWM_RIS_INTPWM2 0x00000004 // PWM2 Interrupt Asserted
231 #define PWM_RIS_INTPWM1 0x00000002 // PWM1 Interrupt Asserted
232 #define PWM_RIS_INTPWM0 0x00000001 // PWM0 Interrupt Asserted
233 
234 //*****************************************************************************
235 //
236 // The following are defines for the bit fields in the PWM_O_ISC register.
237 //
238 //*****************************************************************************
239 #define PWM_ISC_INTFAULT3 0x00080000 // FAULT3 Interrupt Asserted
240 #define PWM_ISC_INTFAULT2 0x00040000 // FAULT2 Interrupt Asserted
241 #define PWM_ISC_INTFAULT1 0x00020000 // FAULT1 Interrupt Asserted
242 #define PWM_ISC_INTFAULT0 0x00010000 // FAULT0 Interrupt Asserted
243 #define PWM_ISC_INTPWM3 0x00000008 // PWM3 Interrupt Status
244 #define PWM_ISC_INTPWM2 0x00000004 // PWM2 Interrupt Status
245 #define PWM_ISC_INTPWM1 0x00000002 // PWM1 Interrupt Status
246 #define PWM_ISC_INTPWM0 0x00000001 // PWM0 Interrupt Status
247 
248 //*****************************************************************************
249 //
250 // The following are defines for the bit fields in the PWM_O_STATUS register.
251 //
252 //*****************************************************************************
253 #define PWM_STATUS_FAULT3 0x00000008 // Generator 3 Fault Status
254 #define PWM_STATUS_FAULT2 0x00000004 // Generator 2 Fault Status
255 #define PWM_STATUS_FAULT1 0x00000002 // Generator 1 Fault Status
256 #define PWM_STATUS_FAULT0 0x00000001 // Generator 0 Fault Status
257 
258 //*****************************************************************************
259 //
260 // The following are defines for the bit fields in the PWM_O_FAULTVAL register.
261 //
262 //*****************************************************************************
263 #define PWM_FAULTVAL_PWM7 0x00000080 // MnPWM7 Fault Value
264 #define PWM_FAULTVAL_PWM6 0x00000040 // MnPWM6 Fault Value
265 #define PWM_FAULTVAL_PWM5 0x00000020 // MnPWM5 Fault Value
266 #define PWM_FAULTVAL_PWM4 0x00000010 // MnPWM4 Fault Value
267 #define PWM_FAULTVAL_PWM3 0x00000008 // MnPWM3 Fault Value
268 #define PWM_FAULTVAL_PWM2 0x00000004 // MnPWM2 Fault Value
269 #define PWM_FAULTVAL_PWM1 0x00000002 // MnPWM1 Fault Value
270 #define PWM_FAULTVAL_PWM0 0x00000001 // MnPWM0 Fault Value
271 
272 //*****************************************************************************
273 //
274 // The following are defines for the bit fields in the PWM_O_ENUPD register.
275 //
276 //*****************************************************************************
277 #define PWM_ENUPD_ENUPD7_M 0x0000C000 // MnPWM7 Enable Update Mode
278 #define PWM_ENUPD_ENUPD7_IMM 0x00000000 // Immediate
279 #define PWM_ENUPD_ENUPD7_LSYNC 0x00008000 // Locally Synchronized
280 #define PWM_ENUPD_ENUPD7_GSYNC 0x0000C000 // Globally Synchronized
281 #define PWM_ENUPD_ENUPD6_M 0x00003000 // MnPWM6 Enable Update Mode
282 #define PWM_ENUPD_ENUPD6_IMM 0x00000000 // Immediate
283 #define PWM_ENUPD_ENUPD6_LSYNC 0x00002000 // Locally Synchronized
284 #define PWM_ENUPD_ENUPD6_GSYNC 0x00003000 // Globally Synchronized
285 #define PWM_ENUPD_ENUPD5_M 0x00000C00 // MnPWM5 Enable Update Mode
286 #define PWM_ENUPD_ENUPD5_IMM 0x00000000 // Immediate
287 #define PWM_ENUPD_ENUPD5_LSYNC 0x00000800 // Locally Synchronized
288 #define PWM_ENUPD_ENUPD5_GSYNC 0x00000C00 // Globally Synchronized
289 #define PWM_ENUPD_ENUPD4_M 0x00000300 // MnPWM4 Enable Update Mode
290 #define PWM_ENUPD_ENUPD4_IMM 0x00000000 // Immediate
291 #define PWM_ENUPD_ENUPD4_LSYNC 0x00000200 // Locally Synchronized
292 #define PWM_ENUPD_ENUPD4_GSYNC 0x00000300 // Globally Synchronized
293 #define PWM_ENUPD_ENUPD3_M 0x000000C0 // MnPWM3 Enable Update Mode
294 #define PWM_ENUPD_ENUPD3_IMM 0x00000000 // Immediate
295 #define PWM_ENUPD_ENUPD3_LSYNC 0x00000080 // Locally Synchronized
296 #define PWM_ENUPD_ENUPD3_GSYNC 0x000000C0 // Globally Synchronized
297 #define PWM_ENUPD_ENUPD2_M 0x00000030 // MnPWM2 Enable Update Mode
298 #define PWM_ENUPD_ENUPD2_IMM 0x00000000 // Immediate
299 #define PWM_ENUPD_ENUPD2_LSYNC 0x00000020 // Locally Synchronized
300 #define PWM_ENUPD_ENUPD2_GSYNC 0x00000030 // Globally Synchronized
301 #define PWM_ENUPD_ENUPD1_M 0x0000000C // MnPWM1 Enable Update Mode
302 #define PWM_ENUPD_ENUPD1_IMM 0x00000000 // Immediate
303 #define PWM_ENUPD_ENUPD1_LSYNC 0x00000008 // Locally Synchronized
304 #define PWM_ENUPD_ENUPD1_GSYNC 0x0000000C // Globally Synchronized
305 #define PWM_ENUPD_ENUPD0_M 0x00000003 // MnPWM0 Enable Update Mode
306 #define PWM_ENUPD_ENUPD0_IMM 0x00000000 // Immediate
307 #define PWM_ENUPD_ENUPD0_LSYNC 0x00000002 // Locally Synchronized
308 #define PWM_ENUPD_ENUPD0_GSYNC 0x00000003 // Globally Synchronized
309 
310 //*****************************************************************************
311 //
312 // The following are defines for the bit fields in the PWM_O_0_CTL register.
313 //
314 //*****************************************************************************
315 #define PWM_0_CTL_LATCH 0x00040000 // Latch Fault Input
316 #define PWM_0_CTL_MINFLTPER 0x00020000 // Minimum Fault Period
317 #define PWM_0_CTL_FLTSRC 0x00010000 // Fault Condition Source
318 #define PWM_0_CTL_DBFALLUPD_M 0x0000C000 // PWMnDBFALL Update Mode
319 #define PWM_0_CTL_DBFALLUPD_I 0x00000000 // Immediate
320 #define PWM_0_CTL_DBFALLUPD_LS 0x00008000 // Locally Synchronized
321 #define PWM_0_CTL_DBFALLUPD_GS 0x0000C000 // Globally Synchronized
322 #define PWM_0_CTL_DBRISEUPD_M 0x00003000 // PWMnDBRISE Update Mode
323 #define PWM_0_CTL_DBRISEUPD_I 0x00000000 // Immediate
324 #define PWM_0_CTL_DBRISEUPD_LS 0x00002000 // Locally Synchronized
325 #define PWM_0_CTL_DBRISEUPD_GS 0x00003000 // Globally Synchronized
326 #define PWM_0_CTL_DBCTLUPD_M 0x00000C00 // PWMnDBCTL Update Mode
327 #define PWM_0_CTL_DBCTLUPD_I 0x00000000 // Immediate
328 #define PWM_0_CTL_DBCTLUPD_LS 0x00000800 // Locally Synchronized
329 #define PWM_0_CTL_DBCTLUPD_GS 0x00000C00 // Globally Synchronized
330 #define PWM_0_CTL_GENBUPD_M 0x00000300 // PWMnGENB Update Mode
331 #define PWM_0_CTL_GENBUPD_I 0x00000000 // Immediate
332 #define PWM_0_CTL_GENBUPD_LS 0x00000200 // Locally Synchronized
333 #define PWM_0_CTL_GENBUPD_GS 0x00000300 // Globally Synchronized
334 #define PWM_0_CTL_GENAUPD_M 0x000000C0 // PWMnGENA Update Mode
335 #define PWM_0_CTL_GENAUPD_I 0x00000000 // Immediate
336 #define PWM_0_CTL_GENAUPD_LS 0x00000080 // Locally Synchronized
337 #define PWM_0_CTL_GENAUPD_GS 0x000000C0 // Globally Synchronized
338 #define PWM_0_CTL_CMPBUPD 0x00000020 // Comparator B Update Mode
339 #define PWM_0_CTL_CMPAUPD 0x00000010 // Comparator A Update Mode
340 #define PWM_0_CTL_LOADUPD 0x00000008 // Load Register Update Mode
341 #define PWM_0_CTL_DEBUG 0x00000004 // Debug Mode
342 #define PWM_0_CTL_MODE 0x00000002 // Counter Mode
343 #define PWM_0_CTL_ENABLE 0x00000001 // PWM Block Enable
344 
345 //*****************************************************************************
346 //
347 // The following are defines for the bit fields in the PWM_O_0_INTEN register.
348 //
349 //*****************************************************************************
350 #define PWM_0_INTEN_TRCMPBD 0x00002000 // Trigger for Counter=PWMnCMPB
351  // Down
352 #define PWM_0_INTEN_TRCMPBU 0x00001000 // Trigger for Counter=PWMnCMPB Up
353 #define PWM_0_INTEN_TRCMPAD 0x00000800 // Trigger for Counter=PWMnCMPA
354  // Down
355 #define PWM_0_INTEN_TRCMPAU 0x00000400 // Trigger for Counter=PWMnCMPA Up
356 #define PWM_0_INTEN_TRCNTLOAD 0x00000200 // Trigger for Counter=PWMnLOAD
357 #define PWM_0_INTEN_TRCNTZERO 0x00000100 // Trigger for Counter=0
358 #define PWM_0_INTEN_INTCMPBD 0x00000020 // Interrupt for Counter=PWMnCMPB
359  // Down
360 #define PWM_0_INTEN_INTCMPBU 0x00000010 // Interrupt for Counter=PWMnCMPB
361  // Up
362 #define PWM_0_INTEN_INTCMPAD 0x00000008 // Interrupt for Counter=PWMnCMPA
363  // Down
364 #define PWM_0_INTEN_INTCMPAU 0x00000004 // Interrupt for Counter=PWMnCMPA
365  // Up
366 #define PWM_0_INTEN_INTCNTLOAD 0x00000002 // Interrupt for Counter=PWMnLOAD
367 #define PWM_0_INTEN_INTCNTZERO 0x00000001 // Interrupt for Counter=0
368 
369 //*****************************************************************************
370 //
371 // The following are defines for the bit fields in the PWM_O_0_RIS register.
372 //
373 //*****************************************************************************
374 #define PWM_0_RIS_INTCMPBD 0x00000020 // Comparator B Down Interrupt
375  // Status
376 #define PWM_0_RIS_INTCMPBU 0x00000010 // Comparator B Up Interrupt Status
377 #define PWM_0_RIS_INTCMPAD 0x00000008 // Comparator A Down Interrupt
378  // Status
379 #define PWM_0_RIS_INTCMPAU 0x00000004 // Comparator A Up Interrupt Status
380 #define PWM_0_RIS_INTCNTLOAD 0x00000002 // Counter=Load Interrupt Status
381 #define PWM_0_RIS_INTCNTZERO 0x00000001 // Counter=0 Interrupt Status
382 
383 //*****************************************************************************
384 //
385 // The following are defines for the bit fields in the PWM_O_0_ISC register.
386 //
387 //*****************************************************************************
388 #define PWM_0_ISC_INTCMPBD 0x00000020 // Comparator B Down Interrupt
389 #define PWM_0_ISC_INTCMPBU 0x00000010 // Comparator B Up Interrupt
390 #define PWM_0_ISC_INTCMPAD 0x00000008 // Comparator A Down Interrupt
391 #define PWM_0_ISC_INTCMPAU 0x00000004 // Comparator A Up Interrupt
392 #define PWM_0_ISC_INTCNTLOAD 0x00000002 // Counter=Load Interrupt
393 #define PWM_0_ISC_INTCNTZERO 0x00000001 // Counter=0 Interrupt
394 
395 //*****************************************************************************
396 //
397 // The following are defines for the bit fields in the PWM_O_0_LOAD register.
398 //
399 //*****************************************************************************
400 #define PWM_0_LOAD_M 0x0000FFFF // Counter Load Value
401 #define PWM_0_LOAD_S 0
402 
403 //*****************************************************************************
404 //
405 // The following are defines for the bit fields in the PWM_O_0_COUNT register.
406 //
407 //*****************************************************************************
408 #define PWM_0_COUNT_M 0x0000FFFF // Counter Value
409 #define PWM_0_COUNT_S 0
410 
411 //*****************************************************************************
412 //
413 // The following are defines for the bit fields in the PWM_O_0_CMPA register.
414 //
415 //*****************************************************************************
416 #define PWM_0_CMPA_M 0x0000FFFF // Comparator A Value
417 #define PWM_0_CMPA_S 0
418 
419 //*****************************************************************************
420 //
421 // The following are defines for the bit fields in the PWM_O_0_CMPB register.
422 //
423 //*****************************************************************************
424 #define PWM_0_CMPB_M 0x0000FFFF // Comparator B Value
425 #define PWM_0_CMPB_S 0
426 
427 //*****************************************************************************
428 //
429 // The following are defines for the bit fields in the PWM_O_0_GENA register.
430 //
431 //*****************************************************************************
432 #define PWM_0_GENA_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down
433 #define PWM_0_GENA_ACTCMPBD_NONE \
434  0x00000000 // Do nothing
435 #define PWM_0_GENA_ACTCMPBD_INV 0x00000400 // Invert pwmA
436 #define PWM_0_GENA_ACTCMPBD_ZERO \
437  0x00000800 // Drive pwmA Low
438 #define PWM_0_GENA_ACTCMPBD_ONE 0x00000C00 // Drive pwmA High
439 #define PWM_0_GENA_ACTCMPBU_M 0x00000300 // Action for Comparator B Up
440 #define PWM_0_GENA_ACTCMPBU_NONE \
441  0x00000000 // Do nothing
442 #define PWM_0_GENA_ACTCMPBU_INV 0x00000100 // Invert pwmA
443 #define PWM_0_GENA_ACTCMPBU_ZERO \
444  0x00000200 // Drive pwmA Low
445 #define PWM_0_GENA_ACTCMPBU_ONE 0x00000300 // Drive pwmA High
446 #define PWM_0_GENA_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down
447 #define PWM_0_GENA_ACTCMPAD_NONE \
448  0x00000000 // Do nothing
449 #define PWM_0_GENA_ACTCMPAD_INV 0x00000040 // Invert pwmA
450 #define PWM_0_GENA_ACTCMPAD_ZERO \
451  0x00000080 // Drive pwmA Low
452 #define PWM_0_GENA_ACTCMPAD_ONE 0x000000C0 // Drive pwmA High
453 #define PWM_0_GENA_ACTCMPAU_M 0x00000030 // Action for Comparator A Up
454 #define PWM_0_GENA_ACTCMPAU_NONE \
455  0x00000000 // Do nothing
456 #define PWM_0_GENA_ACTCMPAU_INV 0x00000010 // Invert pwmA
457 #define PWM_0_GENA_ACTCMPAU_ZERO \
458  0x00000020 // Drive pwmA Low
459 #define PWM_0_GENA_ACTCMPAU_ONE 0x00000030 // Drive pwmA High
460 #define PWM_0_GENA_ACTLOAD_M 0x0000000C // Action for Counter=LOAD
461 #define PWM_0_GENA_ACTLOAD_NONE 0x00000000 // Do nothing
462 #define PWM_0_GENA_ACTLOAD_INV 0x00000004 // Invert pwmA
463 #define PWM_0_GENA_ACTLOAD_ZERO 0x00000008 // Drive pwmA Low
464 #define PWM_0_GENA_ACTLOAD_ONE 0x0000000C // Drive pwmA High
465 #define PWM_0_GENA_ACTZERO_M 0x00000003 // Action for Counter=0
466 #define PWM_0_GENA_ACTZERO_NONE 0x00000000 // Do nothing
467 #define PWM_0_GENA_ACTZERO_INV 0x00000001 // Invert pwmA
468 #define PWM_0_GENA_ACTZERO_ZERO 0x00000002 // Drive pwmA Low
469 #define PWM_0_GENA_ACTZERO_ONE 0x00000003 // Drive pwmA High
470 
471 //*****************************************************************************
472 //
473 // The following are defines for the bit fields in the PWM_O_0_GENB register.
474 //
475 //*****************************************************************************
476 #define PWM_0_GENB_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down
477 #define PWM_0_GENB_ACTCMPBD_NONE \
478  0x00000000 // Do nothing
479 #define PWM_0_GENB_ACTCMPBD_INV 0x00000400 // Invert pwmB
480 #define PWM_0_GENB_ACTCMPBD_ZERO \
481  0x00000800 // Drive pwmB Low
482 #define PWM_0_GENB_ACTCMPBD_ONE 0x00000C00 // Drive pwmB High
483 #define PWM_0_GENB_ACTCMPBU_M 0x00000300 // Action for Comparator B Up
484 #define PWM_0_GENB_ACTCMPBU_NONE \
485  0x00000000 // Do nothing
486 #define PWM_0_GENB_ACTCMPBU_INV 0x00000100 // Invert pwmB
487 #define PWM_0_GENB_ACTCMPBU_ZERO \
488  0x00000200 // Drive pwmB Low
489 #define PWM_0_GENB_ACTCMPBU_ONE 0x00000300 // Drive pwmB High
490 #define PWM_0_GENB_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down
491 #define PWM_0_GENB_ACTCMPAD_NONE \
492  0x00000000 // Do nothing
493 #define PWM_0_GENB_ACTCMPAD_INV 0x00000040 // Invert pwmB
494 #define PWM_0_GENB_ACTCMPAD_ZERO \
495  0x00000080 // Drive pwmB Low
496 #define PWM_0_GENB_ACTCMPAD_ONE 0x000000C0 // Drive pwmB High
497 #define PWM_0_GENB_ACTCMPAU_M 0x00000030 // Action for Comparator A Up
498 #define PWM_0_GENB_ACTCMPAU_NONE \
499  0x00000000 // Do nothing
500 #define PWM_0_GENB_ACTCMPAU_INV 0x00000010 // Invert pwmB
501 #define PWM_0_GENB_ACTCMPAU_ZERO \
502  0x00000020 // Drive pwmB Low
503 #define PWM_0_GENB_ACTCMPAU_ONE 0x00000030 // Drive pwmB High
504 #define PWM_0_GENB_ACTLOAD_M 0x0000000C // Action for Counter=LOAD
505 #define PWM_0_GENB_ACTLOAD_NONE 0x00000000 // Do nothing
506 #define PWM_0_GENB_ACTLOAD_INV 0x00000004 // Invert pwmB
507 #define PWM_0_GENB_ACTLOAD_ZERO 0x00000008 // Drive pwmB Low
508 #define PWM_0_GENB_ACTLOAD_ONE 0x0000000C // Drive pwmB High
509 #define PWM_0_GENB_ACTZERO_M 0x00000003 // Action for Counter=0
510 #define PWM_0_GENB_ACTZERO_NONE 0x00000000 // Do nothing
511 #define PWM_0_GENB_ACTZERO_INV 0x00000001 // Invert pwmB
512 #define PWM_0_GENB_ACTZERO_ZERO 0x00000002 // Drive pwmB Low
513 #define PWM_0_GENB_ACTZERO_ONE 0x00000003 // Drive pwmB High
514 
515 //*****************************************************************************
516 //
517 // The following are defines for the bit fields in the PWM_O_0_DBCTL register.
518 //
519 //*****************************************************************************
520 #define PWM_0_DBCTL_ENABLE 0x00000001 // Dead-Band Generator Enable
521 
522 //*****************************************************************************
523 //
524 // The following are defines for the bit fields in the PWM_O_0_DBRISE register.
525 //
526 //*****************************************************************************
527 #define PWM_0_DBRISE_DELAY_M 0x00000FFF // Dead-Band Rise Delay
528 #define PWM_0_DBRISE_DELAY_S 0
529 
530 //*****************************************************************************
531 //
532 // The following are defines for the bit fields in the PWM_O_0_DBFALL register.
533 //
534 //*****************************************************************************
535 #define PWM_0_DBFALL_DELAY_M 0x00000FFF // Dead-Band Fall Delay
536 #define PWM_0_DBFALL_DELAY_S 0
537 
538 //*****************************************************************************
539 //
540 // The following are defines for the bit fields in the PWM_O_0_FLTSRC0
541 // register.
542 //
543 //*****************************************************************************
544 #define PWM_0_FLTSRC0_FAULT3 0x00000008 // Fault3 Input
545 #define PWM_0_FLTSRC0_FAULT2 0x00000004 // Fault2 Input
546 #define PWM_0_FLTSRC0_FAULT1 0x00000002 // Fault1 Input
547 #define PWM_0_FLTSRC0_FAULT0 0x00000001 // Fault0 Input
548 
549 //*****************************************************************************
550 //
551 // The following are defines for the bit fields in the PWM_O_0_FLTSRC1
552 // register.
553 //
554 //*****************************************************************************
555 #define PWM_0_FLTSRC1_DCMP7 0x00000080 // Digital Comparator 7
556 #define PWM_0_FLTSRC1_DCMP6 0x00000040 // Digital Comparator 6
557 #define PWM_0_FLTSRC1_DCMP5 0x00000020 // Digital Comparator 5
558 #define PWM_0_FLTSRC1_DCMP4 0x00000010 // Digital Comparator 4
559 #define PWM_0_FLTSRC1_DCMP3 0x00000008 // Digital Comparator 3
560 #define PWM_0_FLTSRC1_DCMP2 0x00000004 // Digital Comparator 2
561 #define PWM_0_FLTSRC1_DCMP1 0x00000002 // Digital Comparator 1
562 #define PWM_0_FLTSRC1_DCMP0 0x00000001 // Digital Comparator 0
563 
564 //*****************************************************************************
565 //
566 // The following are defines for the bit fields in the PWM_O_0_MINFLTPER
567 // register.
568 //
569 //*****************************************************************************
570 #define PWM_0_MINFLTPER_M 0x0000FFFF // Minimum Fault Period
571 #define PWM_0_MINFLTPER_S 0
572 
573 //*****************************************************************************
574 //
575 // The following are defines for the bit fields in the PWM_O_1_CTL register.
576 //
577 //*****************************************************************************
578 #define PWM_1_CTL_LATCH 0x00040000 // Latch Fault Input
579 #define PWM_1_CTL_MINFLTPER 0x00020000 // Minimum Fault Period
580 #define PWM_1_CTL_FLTSRC 0x00010000 // Fault Condition Source
581 #define PWM_1_CTL_DBFALLUPD_M 0x0000C000 // PWMnDBFALL Update Mode
582 #define PWM_1_CTL_DBFALLUPD_I 0x00000000 // Immediate
583 #define PWM_1_CTL_DBFALLUPD_LS 0x00008000 // Locally Synchronized
584 #define PWM_1_CTL_DBFALLUPD_GS 0x0000C000 // Globally Synchronized
585 #define PWM_1_CTL_DBRISEUPD_M 0x00003000 // PWMnDBRISE Update Mode
586 #define PWM_1_CTL_DBRISEUPD_I 0x00000000 // Immediate
587 #define PWM_1_CTL_DBRISEUPD_LS 0x00002000 // Locally Synchronized
588 #define PWM_1_CTL_DBRISEUPD_GS 0x00003000 // Globally Synchronized
589 #define PWM_1_CTL_DBCTLUPD_M 0x00000C00 // PWMnDBCTL Update Mode
590 #define PWM_1_CTL_DBCTLUPD_I 0x00000000 // Immediate
591 #define PWM_1_CTL_DBCTLUPD_LS 0x00000800 // Locally Synchronized
592 #define PWM_1_CTL_DBCTLUPD_GS 0x00000C00 // Globally Synchronized
593 #define PWM_1_CTL_GENBUPD_M 0x00000300 // PWMnGENB Update Mode
594 #define PWM_1_CTL_GENBUPD_I 0x00000000 // Immediate
595 #define PWM_1_CTL_GENBUPD_LS 0x00000200 // Locally Synchronized
596 #define PWM_1_CTL_GENBUPD_GS 0x00000300 // Globally Synchronized
597 #define PWM_1_CTL_GENAUPD_M 0x000000C0 // PWMnGENA Update Mode
598 #define PWM_1_CTL_GENAUPD_I 0x00000000 // Immediate
599 #define PWM_1_CTL_GENAUPD_LS 0x00000080 // Locally Synchronized
600 #define PWM_1_CTL_GENAUPD_GS 0x000000C0 // Globally Synchronized
601 #define PWM_1_CTL_CMPBUPD 0x00000020 // Comparator B Update Mode
602 #define PWM_1_CTL_CMPAUPD 0x00000010 // Comparator A Update Mode
603 #define PWM_1_CTL_LOADUPD 0x00000008 // Load Register Update Mode
604 #define PWM_1_CTL_DEBUG 0x00000004 // Debug Mode
605 #define PWM_1_CTL_MODE 0x00000002 // Counter Mode
606 #define PWM_1_CTL_ENABLE 0x00000001 // PWM Block Enable
607 
608 //*****************************************************************************
609 //
610 // The following are defines for the bit fields in the PWM_O_1_INTEN register.
611 //
612 //*****************************************************************************
613 #define PWM_1_INTEN_TRCMPBD 0x00002000 // Trigger for Counter=PWMnCMPB
614  // Down
615 #define PWM_1_INTEN_TRCMPBU 0x00001000 // Trigger for Counter=PWMnCMPB Up
616 #define PWM_1_INTEN_TRCMPAD 0x00000800 // Trigger for Counter=PWMnCMPA
617  // Down
618 #define PWM_1_INTEN_TRCMPAU 0x00000400 // Trigger for Counter=PWMnCMPA Up
619 #define PWM_1_INTEN_TRCNTLOAD 0x00000200 // Trigger for Counter=PWMnLOAD
620 #define PWM_1_INTEN_TRCNTZERO 0x00000100 // Trigger for Counter=0
621 #define PWM_1_INTEN_INTCMPBD 0x00000020 // Interrupt for Counter=PWMnCMPB
622  // Down
623 #define PWM_1_INTEN_INTCMPBU 0x00000010 // Interrupt for Counter=PWMnCMPB
624  // Up
625 #define PWM_1_INTEN_INTCMPAD 0x00000008 // Interrupt for Counter=PWMnCMPA
626  // Down
627 #define PWM_1_INTEN_INTCMPAU 0x00000004 // Interrupt for Counter=PWMnCMPA
628  // Up
629 #define PWM_1_INTEN_INTCNTLOAD 0x00000002 // Interrupt for Counter=PWMnLOAD
630 #define PWM_1_INTEN_INTCNTZERO 0x00000001 // Interrupt for Counter=0
631 
632 //*****************************************************************************
633 //
634 // The following are defines for the bit fields in the PWM_O_1_RIS register.
635 //
636 //*****************************************************************************
637 #define PWM_1_RIS_INTCMPBD 0x00000020 // Comparator B Down Interrupt
638  // Status
639 #define PWM_1_RIS_INTCMPBU 0x00000010 // Comparator B Up Interrupt Status
640 #define PWM_1_RIS_INTCMPAD 0x00000008 // Comparator A Down Interrupt
641  // Status
642 #define PWM_1_RIS_INTCMPAU 0x00000004 // Comparator A Up Interrupt Status
643 #define PWM_1_RIS_INTCNTLOAD 0x00000002 // Counter=Load Interrupt Status
644 #define PWM_1_RIS_INTCNTZERO 0x00000001 // Counter=0 Interrupt Status
645 
646 //*****************************************************************************
647 //
648 // The following are defines for the bit fields in the PWM_O_1_ISC register.
649 //
650 //*****************************************************************************
651 #define PWM_1_ISC_INTCMPBD 0x00000020 // Comparator B Down Interrupt
652 #define PWM_1_ISC_INTCMPBU 0x00000010 // Comparator B Up Interrupt
653 #define PWM_1_ISC_INTCMPAD 0x00000008 // Comparator A Down Interrupt
654 #define PWM_1_ISC_INTCMPAU 0x00000004 // Comparator A Up Interrupt
655 #define PWM_1_ISC_INTCNTLOAD 0x00000002 // Counter=Load Interrupt
656 #define PWM_1_ISC_INTCNTZERO 0x00000001 // Counter=0 Interrupt
657 
658 //*****************************************************************************
659 //
660 // The following are defines for the bit fields in the PWM_O_1_LOAD register.
661 //
662 //*****************************************************************************
663 #define PWM_1_LOAD_LOAD_M 0x0000FFFF // Counter Load Value
664 #define PWM_1_LOAD_LOAD_S 0
665 
666 //*****************************************************************************
667 //
668 // The following are defines for the bit fields in the PWM_O_1_COUNT register.
669 //
670 //*****************************************************************************
671 #define PWM_1_COUNT_COUNT_M 0x0000FFFF // Counter Value
672 #define PWM_1_COUNT_COUNT_S 0
673 
674 //*****************************************************************************
675 //
676 // The following are defines for the bit fields in the PWM_O_1_CMPA register.
677 //
678 //*****************************************************************************
679 #define PWM_1_CMPA_COMPA_M 0x0000FFFF // Comparator A Value
680 #define PWM_1_CMPA_COMPA_S 0
681 
682 //*****************************************************************************
683 //
684 // The following are defines for the bit fields in the PWM_O_1_CMPB register.
685 //
686 //*****************************************************************************
687 #define PWM_1_CMPB_COMPB_M 0x0000FFFF // Comparator B Value
688 #define PWM_1_CMPB_COMPB_S 0
689 
690 //*****************************************************************************
691 //
692 // The following are defines for the bit fields in the PWM_O_1_GENA register.
693 //
694 //*****************************************************************************
695 #define PWM_1_GENA_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down
696 #define PWM_1_GENA_ACTCMPBD_NONE \
697  0x00000000 // Do nothing
698 #define PWM_1_GENA_ACTCMPBD_INV 0x00000400 // Invert pwmA
699 #define PWM_1_GENA_ACTCMPBD_ZERO \
700  0x00000800 // Drive pwmA Low
701 #define PWM_1_GENA_ACTCMPBD_ONE 0x00000C00 // Drive pwmA High
702 #define PWM_1_GENA_ACTCMPBU_M 0x00000300 // Action for Comparator B Up
703 #define PWM_1_GENA_ACTCMPBU_NONE \
704  0x00000000 // Do nothing
705 #define PWM_1_GENA_ACTCMPBU_INV 0x00000100 // Invert pwmA
706 #define PWM_1_GENA_ACTCMPBU_ZERO \
707  0x00000200 // Drive pwmA Low
708 #define PWM_1_GENA_ACTCMPBU_ONE 0x00000300 // Drive pwmA High
709 #define PWM_1_GENA_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down
710 #define PWM_1_GENA_ACTCMPAD_NONE \
711  0x00000000 // Do nothing
712 #define PWM_1_GENA_ACTCMPAD_INV 0x00000040 // Invert pwmA
713 #define PWM_1_GENA_ACTCMPAD_ZERO \
714  0x00000080 // Drive pwmA Low
715 #define PWM_1_GENA_ACTCMPAD_ONE 0x000000C0 // Drive pwmA High
716 #define PWM_1_GENA_ACTCMPAU_M 0x00000030 // Action for Comparator A Up
717 #define PWM_1_GENA_ACTCMPAU_NONE \
718  0x00000000 // Do nothing
719 #define PWM_1_GENA_ACTCMPAU_INV 0x00000010 // Invert pwmA
720 #define PWM_1_GENA_ACTCMPAU_ZERO \
721  0x00000020 // Drive pwmA Low
722 #define PWM_1_GENA_ACTCMPAU_ONE 0x00000030 // Drive pwmA High
723 #define PWM_1_GENA_ACTLOAD_M 0x0000000C // Action for Counter=LOAD
724 #define PWM_1_GENA_ACTLOAD_NONE 0x00000000 // Do nothing
725 #define PWM_1_GENA_ACTLOAD_INV 0x00000004 // Invert pwmA
726 #define PWM_1_GENA_ACTLOAD_ZERO 0x00000008 // Drive pwmA Low
727 #define PWM_1_GENA_ACTLOAD_ONE 0x0000000C // Drive pwmA High
728 #define PWM_1_GENA_ACTZERO_M 0x00000003 // Action for Counter=0
729 #define PWM_1_GENA_ACTZERO_NONE 0x00000000 // Do nothing
730 #define PWM_1_GENA_ACTZERO_INV 0x00000001 // Invert pwmA
731 #define PWM_1_GENA_ACTZERO_ZERO 0x00000002 // Drive pwmA Low
732 #define PWM_1_GENA_ACTZERO_ONE 0x00000003 // Drive pwmA High
733 
734 //*****************************************************************************
735 //
736 // The following are defines for the bit fields in the PWM_O_1_GENB register.
737 //
738 //*****************************************************************************
739 #define PWM_1_GENB_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down
740 #define PWM_1_GENB_ACTCMPBD_NONE \
741  0x00000000 // Do nothing
742 #define PWM_1_GENB_ACTCMPBD_INV 0x00000400 // Invert pwmB
743 #define PWM_1_GENB_ACTCMPBD_ZERO \
744  0x00000800 // Drive pwmB Low
745 #define PWM_1_GENB_ACTCMPBD_ONE 0x00000C00 // Drive pwmB High
746 #define PWM_1_GENB_ACTCMPBU_M 0x00000300 // Action for Comparator B Up
747 #define PWM_1_GENB_ACTCMPBU_NONE \
748  0x00000000 // Do nothing
749 #define PWM_1_GENB_ACTCMPBU_INV 0x00000100 // Invert pwmB
750 #define PWM_1_GENB_ACTCMPBU_ZERO \
751  0x00000200 // Drive pwmB Low
752 #define PWM_1_GENB_ACTCMPBU_ONE 0x00000300 // Drive pwmB High
753 #define PWM_1_GENB_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down
754 #define PWM_1_GENB_ACTCMPAD_NONE \
755  0x00000000 // Do nothing
756 #define PWM_1_GENB_ACTCMPAD_INV 0x00000040 // Invert pwmB
757 #define PWM_1_GENB_ACTCMPAD_ZERO \
758  0x00000080 // Drive pwmB Low
759 #define PWM_1_GENB_ACTCMPAD_ONE 0x000000C0 // Drive pwmB High
760 #define PWM_1_GENB_ACTCMPAU_M 0x00000030 // Action for Comparator A Up
761 #define PWM_1_GENB_ACTCMPAU_NONE \
762  0x00000000 // Do nothing
763 #define PWM_1_GENB_ACTCMPAU_INV 0x00000010 // Invert pwmB
764 #define PWM_1_GENB_ACTCMPAU_ZERO \
765  0x00000020 // Drive pwmB Low
766 #define PWM_1_GENB_ACTCMPAU_ONE 0x00000030 // Drive pwmB High
767 #define PWM_1_GENB_ACTLOAD_M 0x0000000C // Action for Counter=LOAD
768 #define PWM_1_GENB_ACTLOAD_NONE 0x00000000 // Do nothing
769 #define PWM_1_GENB_ACTLOAD_INV 0x00000004 // Invert pwmB
770 #define PWM_1_GENB_ACTLOAD_ZERO 0x00000008 // Drive pwmB Low
771 #define PWM_1_GENB_ACTLOAD_ONE 0x0000000C // Drive pwmB High
772 #define PWM_1_GENB_ACTZERO_M 0x00000003 // Action for Counter=0
773 #define PWM_1_GENB_ACTZERO_NONE 0x00000000 // Do nothing
774 #define PWM_1_GENB_ACTZERO_INV 0x00000001 // Invert pwmB
775 #define PWM_1_GENB_ACTZERO_ZERO 0x00000002 // Drive pwmB Low
776 #define PWM_1_GENB_ACTZERO_ONE 0x00000003 // Drive pwmB High
777 
778 //*****************************************************************************
779 //
780 // The following are defines for the bit fields in the PWM_O_1_DBCTL register.
781 //
782 //*****************************************************************************
783 #define PWM_1_DBCTL_ENABLE 0x00000001 // Dead-Band Generator Enable
784 
785 //*****************************************************************************
786 //
787 // The following are defines for the bit fields in the PWM_O_1_DBRISE register.
788 //
789 //*****************************************************************************
790 #define PWM_1_DBRISE_RISEDELAY_M \
791  0x00000FFF // Dead-Band Rise Delay
792 #define PWM_1_DBRISE_RISEDELAY_S \
793  0
794 
795 //*****************************************************************************
796 //
797 // The following are defines for the bit fields in the PWM_O_1_DBFALL register.
798 //
799 //*****************************************************************************
800 #define PWM_1_DBFALL_FALLDELAY_M \
801  0x00000FFF // Dead-Band Fall Delay
802 #define PWM_1_DBFALL_FALLDELAY_S \
803  0
804 
805 //*****************************************************************************
806 //
807 // The following are defines for the bit fields in the PWM_O_1_FLTSRC0
808 // register.
809 //
810 //*****************************************************************************
811 #define PWM_1_FLTSRC0_FAULT3 0x00000008 // Fault3 Input
812 #define PWM_1_FLTSRC0_FAULT2 0x00000004 // Fault2 Input
813 #define PWM_1_FLTSRC0_FAULT1 0x00000002 // Fault1 Input
814 #define PWM_1_FLTSRC0_FAULT0 0x00000001 // Fault0 Input
815 
816 //*****************************************************************************
817 //
818 // The following are defines for the bit fields in the PWM_O_1_FLTSRC1
819 // register.
820 //
821 //*****************************************************************************
822 #define PWM_1_FLTSRC1_DCMP7 0x00000080 // Digital Comparator 7
823 #define PWM_1_FLTSRC1_DCMP6 0x00000040 // Digital Comparator 6
824 #define PWM_1_FLTSRC1_DCMP5 0x00000020 // Digital Comparator 5
825 #define PWM_1_FLTSRC1_DCMP4 0x00000010 // Digital Comparator 4
826 #define PWM_1_FLTSRC1_DCMP3 0x00000008 // Digital Comparator 3
827 #define PWM_1_FLTSRC1_DCMP2 0x00000004 // Digital Comparator 2
828 #define PWM_1_FLTSRC1_DCMP1 0x00000002 // Digital Comparator 1
829 #define PWM_1_FLTSRC1_DCMP0 0x00000001 // Digital Comparator 0
830 
831 //*****************************************************************************
832 //
833 // The following are defines for the bit fields in the PWM_O_1_MINFLTPER
834 // register.
835 //
836 //*****************************************************************************
837 #define PWM_1_MINFLTPER_MFP_M 0x0000FFFF // Minimum Fault Period
838 #define PWM_1_MINFLTPER_MFP_S 0
839 
840 //*****************************************************************************
841 //
842 // The following are defines for the bit fields in the PWM_O_2_CTL register.
843 //
844 //*****************************************************************************
845 #define PWM_2_CTL_LATCH 0x00040000 // Latch Fault Input
846 #define PWM_2_CTL_MINFLTPER 0x00020000 // Minimum Fault Period
847 #define PWM_2_CTL_FLTSRC 0x00010000 // Fault Condition Source
848 #define PWM_2_CTL_DBFALLUPD_M 0x0000C000 // PWMnDBFALL Update Mode
849 #define PWM_2_CTL_DBFALLUPD_I 0x00000000 // Immediate
850 #define PWM_2_CTL_DBFALLUPD_LS 0x00008000 // Locally Synchronized
851 #define PWM_2_CTL_DBFALLUPD_GS 0x0000C000 // Globally Synchronized
852 #define PWM_2_CTL_DBRISEUPD_M 0x00003000 // PWMnDBRISE Update Mode
853 #define PWM_2_CTL_DBRISEUPD_I 0x00000000 // Immediate
854 #define PWM_2_CTL_DBRISEUPD_LS 0x00002000 // Locally Synchronized
855 #define PWM_2_CTL_DBRISEUPD_GS 0x00003000 // Globally Synchronized
856 #define PWM_2_CTL_DBCTLUPD_M 0x00000C00 // PWMnDBCTL Update Mode
857 #define PWM_2_CTL_DBCTLUPD_I 0x00000000 // Immediate
858 #define PWM_2_CTL_DBCTLUPD_LS 0x00000800 // Locally Synchronized
859 #define PWM_2_CTL_DBCTLUPD_GS 0x00000C00 // Globally Synchronized
860 #define PWM_2_CTL_GENBUPD_M 0x00000300 // PWMnGENB Update Mode
861 #define PWM_2_CTL_GENBUPD_I 0x00000000 // Immediate
862 #define PWM_2_CTL_GENBUPD_LS 0x00000200 // Locally Synchronized
863 #define PWM_2_CTL_GENBUPD_GS 0x00000300 // Globally Synchronized
864 #define PWM_2_CTL_GENAUPD_M 0x000000C0 // PWMnGENA Update Mode
865 #define PWM_2_CTL_GENAUPD_I 0x00000000 // Immediate
866 #define PWM_2_CTL_GENAUPD_LS 0x00000080 // Locally Synchronized
867 #define PWM_2_CTL_GENAUPD_GS 0x000000C0 // Globally Synchronized
868 #define PWM_2_CTL_CMPBUPD 0x00000020 // Comparator B Update Mode
869 #define PWM_2_CTL_CMPAUPD 0x00000010 // Comparator A Update Mode
870 #define PWM_2_CTL_LOADUPD 0x00000008 // Load Register Update Mode
871 #define PWM_2_CTL_DEBUG 0x00000004 // Debug Mode
872 #define PWM_2_CTL_MODE 0x00000002 // Counter Mode
873 #define PWM_2_CTL_ENABLE 0x00000001 // PWM Block Enable
874 
875 //*****************************************************************************
876 //
877 // The following are defines for the bit fields in the PWM_O_2_INTEN register.
878 //
879 //*****************************************************************************
880 #define PWM_2_INTEN_TRCMPBD 0x00002000 // Trigger for Counter=PWMnCMPB
881  // Down
882 #define PWM_2_INTEN_TRCMPBU 0x00001000 // Trigger for Counter=PWMnCMPB Up
883 #define PWM_2_INTEN_TRCMPAD 0x00000800 // Trigger for Counter=PWMnCMPA
884  // Down
885 #define PWM_2_INTEN_TRCMPAU 0x00000400 // Trigger for Counter=PWMnCMPA Up
886 #define PWM_2_INTEN_TRCNTLOAD 0x00000200 // Trigger for Counter=PWMnLOAD
887 #define PWM_2_INTEN_TRCNTZERO 0x00000100 // Trigger for Counter=0
888 #define PWM_2_INTEN_INTCMPBD 0x00000020 // Interrupt for Counter=PWMnCMPB
889  // Down
890 #define PWM_2_INTEN_INTCMPBU 0x00000010 // Interrupt for Counter=PWMnCMPB
891  // Up
892 #define PWM_2_INTEN_INTCMPAD 0x00000008 // Interrupt for Counter=PWMnCMPA
893  // Down
894 #define PWM_2_INTEN_INTCMPAU 0x00000004 // Interrupt for Counter=PWMnCMPA
895  // Up
896 #define PWM_2_INTEN_INTCNTLOAD 0x00000002 // Interrupt for Counter=PWMnLOAD
897 #define PWM_2_INTEN_INTCNTZERO 0x00000001 // Interrupt for Counter=0
898 
899 //*****************************************************************************
900 //
901 // The following are defines for the bit fields in the PWM_O_2_RIS register.
902 //
903 //*****************************************************************************
904 #define PWM_2_RIS_INTCMPBD 0x00000020 // Comparator B Down Interrupt
905  // Status
906 #define PWM_2_RIS_INTCMPBU 0x00000010 // Comparator B Up Interrupt Status
907 #define PWM_2_RIS_INTCMPAD 0x00000008 // Comparator A Down Interrupt
908  // Status
909 #define PWM_2_RIS_INTCMPAU 0x00000004 // Comparator A Up Interrupt Status
910 #define PWM_2_RIS_INTCNTLOAD 0x00000002 // Counter=Load Interrupt Status
911 #define PWM_2_RIS_INTCNTZERO 0x00000001 // Counter=0 Interrupt Status
912 
913 //*****************************************************************************
914 //
915 // The following are defines for the bit fields in the PWM_O_2_ISC register.
916 //
917 //*****************************************************************************
918 #define PWM_2_ISC_INTCMPBD 0x00000020 // Comparator B Down Interrupt
919 #define PWM_2_ISC_INTCMPBU 0x00000010 // Comparator B Up Interrupt
920 #define PWM_2_ISC_INTCMPAD 0x00000008 // Comparator A Down Interrupt
921 #define PWM_2_ISC_INTCMPAU 0x00000004 // Comparator A Up Interrupt
922 #define PWM_2_ISC_INTCNTLOAD 0x00000002 // Counter=Load Interrupt
923 #define PWM_2_ISC_INTCNTZERO 0x00000001 // Counter=0 Interrupt
924 
925 //*****************************************************************************
926 //
927 // The following are defines for the bit fields in the PWM_O_2_LOAD register.
928 //
929 //*****************************************************************************
930 #define PWM_2_LOAD_LOAD_M 0x0000FFFF // Counter Load Value
931 #define PWM_2_LOAD_LOAD_S 0
932 
933 //*****************************************************************************
934 //
935 // The following are defines for the bit fields in the PWM_O_2_COUNT register.
936 //
937 //*****************************************************************************
938 #define PWM_2_COUNT_COUNT_M 0x0000FFFF // Counter Value
939 #define PWM_2_COUNT_COUNT_S 0
940 
941 //*****************************************************************************
942 //
943 // The following are defines for the bit fields in the PWM_O_2_CMPA register.
944 //
945 //*****************************************************************************
946 #define PWM_2_CMPA_COMPA_M 0x0000FFFF // Comparator A Value
947 #define PWM_2_CMPA_COMPA_S 0
948 
949 //*****************************************************************************
950 //
951 // The following are defines for the bit fields in the PWM_O_2_CMPB register.
952 //
953 //*****************************************************************************
954 #define PWM_2_CMPB_COMPB_M 0x0000FFFF // Comparator B Value
955 #define PWM_2_CMPB_COMPB_S 0
956 
957 //*****************************************************************************
958 //
959 // The following are defines for the bit fields in the PWM_O_2_GENA register.
960 //
961 //*****************************************************************************
962 #define PWM_2_GENA_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down
963 #define PWM_2_GENA_ACTCMPBD_NONE \
964  0x00000000 // Do nothing
965 #define PWM_2_GENA_ACTCMPBD_INV 0x00000400 // Invert pwmA
966 #define PWM_2_GENA_ACTCMPBD_ZERO \
967  0x00000800 // Drive pwmA Low
968 #define PWM_2_GENA_ACTCMPBD_ONE 0x00000C00 // Drive pwmA High
969 #define PWM_2_GENA_ACTCMPBU_M 0x00000300 // Action for Comparator B Up
970 #define PWM_2_GENA_ACTCMPBU_NONE \
971  0x00000000 // Do nothing
972 #define PWM_2_GENA_ACTCMPBU_INV 0x00000100 // Invert pwmA
973 #define PWM_2_GENA_ACTCMPBU_ZERO \
974  0x00000200 // Drive pwmA Low
975 #define PWM_2_GENA_ACTCMPBU_ONE 0x00000300 // Drive pwmA High
976 #define PWM_2_GENA_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down
977 #define PWM_2_GENA_ACTCMPAD_NONE \
978  0x00000000 // Do nothing
979 #define PWM_2_GENA_ACTCMPAD_INV 0x00000040 // Invert pwmA
980 #define PWM_2_GENA_ACTCMPAD_ZERO \
981  0x00000080 // Drive pwmA Low
982 #define PWM_2_GENA_ACTCMPAD_ONE 0x000000C0 // Drive pwmA High
983 #define PWM_2_GENA_ACTCMPAU_M 0x00000030 // Action for Comparator A Up
984 #define PWM_2_GENA_ACTCMPAU_NONE \
985  0x00000000 // Do nothing
986 #define PWM_2_GENA_ACTCMPAU_INV 0x00000010 // Invert pwmA
987 #define PWM_2_GENA_ACTCMPAU_ZERO \
988  0x00000020 // Drive pwmA Low
989 #define PWM_2_GENA_ACTCMPAU_ONE 0x00000030 // Drive pwmA High
990 #define PWM_2_GENA_ACTLOAD_M 0x0000000C // Action for Counter=LOAD
991 #define PWM_2_GENA_ACTLOAD_NONE 0x00000000 // Do nothing
992 #define PWM_2_GENA_ACTLOAD_INV 0x00000004 // Invert pwmA
993 #define PWM_2_GENA_ACTLOAD_ZERO 0x00000008 // Drive pwmA Low
994 #define PWM_2_GENA_ACTLOAD_ONE 0x0000000C // Drive pwmA High
995 #define PWM_2_GENA_ACTZERO_M 0x00000003 // Action for Counter=0
996 #define PWM_2_GENA_ACTZERO_NONE 0x00000000 // Do nothing
997 #define PWM_2_GENA_ACTZERO_INV 0x00000001 // Invert pwmA
998 #define PWM_2_GENA_ACTZERO_ZERO 0x00000002 // Drive pwmA Low
999 #define PWM_2_GENA_ACTZERO_ONE 0x00000003 // Drive pwmA High
1000 
1001 //*****************************************************************************
1002 //
1003 // The following are defines for the bit fields in the PWM_O_2_GENB register.
1004 //
1005 //*****************************************************************************
1006 #define PWM_2_GENB_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down
1007 #define PWM_2_GENB_ACTCMPBD_NONE \
1008  0x00000000 // Do nothing
1009 #define PWM_2_GENB_ACTCMPBD_INV 0x00000400 // Invert pwmB
1010 #define PWM_2_GENB_ACTCMPBD_ZERO \
1011  0x00000800 // Drive pwmB Low
1012 #define PWM_2_GENB_ACTCMPBD_ONE 0x00000C00 // Drive pwmB High
1013 #define PWM_2_GENB_ACTCMPBU_M 0x00000300 // Action for Comparator B Up
1014 #define PWM_2_GENB_ACTCMPBU_NONE \
1015  0x00000000 // Do nothing
1016 #define PWM_2_GENB_ACTCMPBU_INV 0x00000100 // Invert pwmB
1017 #define PWM_2_GENB_ACTCMPBU_ZERO \
1018  0x00000200 // Drive pwmB Low
1019 #define PWM_2_GENB_ACTCMPBU_ONE 0x00000300 // Drive pwmB High
1020 #define PWM_2_GENB_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down
1021 #define PWM_2_GENB_ACTCMPAD_NONE \
1022  0x00000000 // Do nothing
1023 #define PWM_2_GENB_ACTCMPAD_INV 0x00000040 // Invert pwmB
1024 #define PWM_2_GENB_ACTCMPAD_ZERO \
1025  0x00000080 // Drive pwmB Low
1026 #define PWM_2_GENB_ACTCMPAD_ONE 0x000000C0 // Drive pwmB High
1027 #define PWM_2_GENB_ACTCMPAU_M 0x00000030 // Action for Comparator A Up
1028 #define PWM_2_GENB_ACTCMPAU_NONE \
1029  0x00000000 // Do nothing
1030 #define PWM_2_GENB_ACTCMPAU_INV 0x00000010 // Invert pwmB
1031 #define PWM_2_GENB_ACTCMPAU_ZERO \
1032  0x00000020 // Drive pwmB Low
1033 #define PWM_2_GENB_ACTCMPAU_ONE 0x00000030 // Drive pwmB High
1034 #define PWM_2_GENB_ACTLOAD_M 0x0000000C // Action for Counter=LOAD
1035 #define PWM_2_GENB_ACTLOAD_NONE 0x00000000 // Do nothing
1036 #define PWM_2_GENB_ACTLOAD_INV 0x00000004 // Invert pwmB
1037 #define PWM_2_GENB_ACTLOAD_ZERO 0x00000008 // Drive pwmB Low
1038 #define PWM_2_GENB_ACTLOAD_ONE 0x0000000C // Drive pwmB High
1039 #define PWM_2_GENB_ACTZERO_M 0x00000003 // Action for Counter=0
1040 #define PWM_2_GENB_ACTZERO_NONE 0x00000000 // Do nothing
1041 #define PWM_2_GENB_ACTZERO_INV 0x00000001 // Invert pwmB
1042 #define PWM_2_GENB_ACTZERO_ZERO 0x00000002 // Drive pwmB Low
1043 #define PWM_2_GENB_ACTZERO_ONE 0x00000003 // Drive pwmB High
1044 
1045 //*****************************************************************************
1046 //
1047 // The following are defines for the bit fields in the PWM_O_2_DBCTL register.
1048 //
1049 //*****************************************************************************
1050 #define PWM_2_DBCTL_ENABLE 0x00000001 // Dead-Band Generator Enable
1051 
1052 //*****************************************************************************
1053 //
1054 // The following are defines for the bit fields in the PWM_O_2_DBRISE register.
1055 //
1056 //*****************************************************************************
1057 #define PWM_2_DBRISE_RISEDELAY_M \
1058  0x00000FFF // Dead-Band Rise Delay
1059 #define PWM_2_DBRISE_RISEDELAY_S \
1060  0
1061 
1062 //*****************************************************************************
1063 //
1064 // The following are defines for the bit fields in the PWM_O_2_DBFALL register.
1065 //
1066 //*****************************************************************************
1067 #define PWM_2_DBFALL_FALLDELAY_M \
1068  0x00000FFF // Dead-Band Fall Delay
1069 #define PWM_2_DBFALL_FALLDELAY_S \
1070  0
1071 
1072 //*****************************************************************************
1073 //
1074 // The following are defines for the bit fields in the PWM_O_2_FLTSRC0
1075 // register.
1076 //
1077 //*****************************************************************************
1078 #define PWM_2_FLTSRC0_FAULT3 0x00000008 // Fault3 Input
1079 #define PWM_2_FLTSRC0_FAULT2 0x00000004 // Fault2 Input
1080 #define PWM_2_FLTSRC0_FAULT1 0x00000002 // Fault1 Input
1081 #define PWM_2_FLTSRC0_FAULT0 0x00000001 // Fault0 Input
1082 
1083 //*****************************************************************************
1084 //
1085 // The following are defines for the bit fields in the PWM_O_2_FLTSRC1
1086 // register.
1087 //
1088 //*****************************************************************************
1089 #define PWM_2_FLTSRC1_DCMP7 0x00000080 // Digital Comparator 7
1090 #define PWM_2_FLTSRC1_DCMP6 0x00000040 // Digital Comparator 6
1091 #define PWM_2_FLTSRC1_DCMP5 0x00000020 // Digital Comparator 5
1092 #define PWM_2_FLTSRC1_DCMP4 0x00000010 // Digital Comparator 4
1093 #define PWM_2_FLTSRC1_DCMP3 0x00000008 // Digital Comparator 3
1094 #define PWM_2_FLTSRC1_DCMP2 0x00000004 // Digital Comparator 2
1095 #define PWM_2_FLTSRC1_DCMP1 0x00000002 // Digital Comparator 1
1096 #define PWM_2_FLTSRC1_DCMP0 0x00000001 // Digital Comparator 0
1097 
1098 //*****************************************************************************
1099 //
1100 // The following are defines for the bit fields in the PWM_O_2_MINFLTPER
1101 // register.
1102 //
1103 //*****************************************************************************
1104 #define PWM_2_MINFLTPER_MFP_M 0x0000FFFF // Minimum Fault Period
1105 #define PWM_2_MINFLTPER_MFP_S 0
1106 
1107 //*****************************************************************************
1108 //
1109 // The following are defines for the bit fields in the PWM_O_3_CTL register.
1110 //
1111 //*****************************************************************************
1112 #define PWM_3_CTL_LATCH 0x00040000 // Latch Fault Input
1113 #define PWM_3_CTL_MINFLTPER 0x00020000 // Minimum Fault Period
1114 #define PWM_3_CTL_FLTSRC 0x00010000 // Fault Condition Source
1115 #define PWM_3_CTL_DBFALLUPD_M 0x0000C000 // PWMnDBFALL Update Mode
1116 #define PWM_3_CTL_DBFALLUPD_I 0x00000000 // Immediate
1117 #define PWM_3_CTL_DBFALLUPD_LS 0x00008000 // Locally Synchronized
1118 #define PWM_3_CTL_DBFALLUPD_GS 0x0000C000 // Globally Synchronized
1119 #define PWM_3_CTL_DBRISEUPD_M 0x00003000 // PWMnDBRISE Update Mode
1120 #define PWM_3_CTL_DBRISEUPD_I 0x00000000 // Immediate
1121 #define PWM_3_CTL_DBRISEUPD_LS 0x00002000 // Locally Synchronized
1122 #define PWM_3_CTL_DBRISEUPD_GS 0x00003000 // Globally Synchronized
1123 #define PWM_3_CTL_DBCTLUPD_M 0x00000C00 // PWMnDBCTL Update Mode
1124 #define PWM_3_CTL_DBCTLUPD_I 0x00000000 // Immediate
1125 #define PWM_3_CTL_DBCTLUPD_LS 0x00000800 // Locally Synchronized
1126 #define PWM_3_CTL_DBCTLUPD_GS 0x00000C00 // Globally Synchronized
1127 #define PWM_3_CTL_GENBUPD_M 0x00000300 // PWMnGENB Update Mode
1128 #define PWM_3_CTL_GENBUPD_I 0x00000000 // Immediate
1129 #define PWM_3_CTL_GENBUPD_LS 0x00000200 // Locally Synchronized
1130 #define PWM_3_CTL_GENBUPD_GS 0x00000300 // Globally Synchronized
1131 #define PWM_3_CTL_GENAUPD_M 0x000000C0 // PWMnGENA Update Mode
1132 #define PWM_3_CTL_GENAUPD_I 0x00000000 // Immediate
1133 #define PWM_3_CTL_GENAUPD_LS 0x00000080 // Locally Synchronized
1134 #define PWM_3_CTL_GENAUPD_GS 0x000000C0 // Globally Synchronized
1135 #define PWM_3_CTL_CMPBUPD 0x00000020 // Comparator B Update Mode
1136 #define PWM_3_CTL_CMPAUPD 0x00000010 // Comparator A Update Mode
1137 #define PWM_3_CTL_LOADUPD 0x00000008 // Load Register Update Mode
1138 #define PWM_3_CTL_DEBUG 0x00000004 // Debug Mode
1139 #define PWM_3_CTL_MODE 0x00000002 // Counter Mode
1140 #define PWM_3_CTL_ENABLE 0x00000001 // PWM Block Enable
1141 
1142 //*****************************************************************************
1143 //
1144 // The following are defines for the bit fields in the PWM_O_3_INTEN register.
1145 //
1146 //*****************************************************************************
1147 #define PWM_3_INTEN_TRCMPBD 0x00002000 // Trigger for Counter=PWMnCMPB
1148  // Down
1149 #define PWM_3_INTEN_TRCMPBU 0x00001000 // Trigger for Counter=PWMnCMPB Up
1150 #define PWM_3_INTEN_TRCMPAD 0x00000800 // Trigger for Counter=PWMnCMPA
1151  // Down
1152 #define PWM_3_INTEN_TRCMPAU 0x00000400 // Trigger for Counter=PWMnCMPA Up
1153 #define PWM_3_INTEN_TRCNTLOAD 0x00000200 // Trigger for Counter=PWMnLOAD
1154 #define PWM_3_INTEN_TRCNTZERO 0x00000100 // Trigger for Counter=0
1155 #define PWM_3_INTEN_INTCMPBD 0x00000020 // Interrupt for Counter=PWMnCMPB
1156  // Down
1157 #define PWM_3_INTEN_INTCMPBU 0x00000010 // Interrupt for Counter=PWMnCMPB
1158  // Up
1159 #define PWM_3_INTEN_INTCMPAD 0x00000008 // Interrupt for Counter=PWMnCMPA
1160  // Down
1161 #define PWM_3_INTEN_INTCMPAU 0x00000004 // Interrupt for Counter=PWMnCMPA
1162  // Up
1163 #define PWM_3_INTEN_INTCNTLOAD 0x00000002 // Interrupt for Counter=PWMnLOAD
1164 #define PWM_3_INTEN_INTCNTZERO 0x00000001 // Interrupt for Counter=0
1165 
1166 //*****************************************************************************
1167 //
1168 // The following are defines for the bit fields in the PWM_O_3_RIS register.
1169 //
1170 //*****************************************************************************
1171 #define PWM_3_RIS_INTCMPBD 0x00000020 // Comparator B Down Interrupt
1172  // Status
1173 #define PWM_3_RIS_INTCMPBU 0x00000010 // Comparator B Up Interrupt Status
1174 #define PWM_3_RIS_INTCMPAD 0x00000008 // Comparator A Down Interrupt
1175  // Status
1176 #define PWM_3_RIS_INTCMPAU 0x00000004 // Comparator A Up Interrupt Status
1177 #define PWM_3_RIS_INTCNTLOAD 0x00000002 // Counter=Load Interrupt Status
1178 #define PWM_3_RIS_INTCNTZERO 0x00000001 // Counter=0 Interrupt Status
1179 
1180 //*****************************************************************************
1181 //
1182 // The following are defines for the bit fields in the PWM_O_3_ISC register.
1183 //
1184 //*****************************************************************************
1185 #define PWM_3_ISC_INTCMPBD 0x00000020 // Comparator B Down Interrupt
1186 #define PWM_3_ISC_INTCMPBU 0x00000010 // Comparator B Up Interrupt
1187 #define PWM_3_ISC_INTCMPAD 0x00000008 // Comparator A Down Interrupt
1188 #define PWM_3_ISC_INTCMPAU 0x00000004 // Comparator A Up Interrupt
1189 #define PWM_3_ISC_INTCNTLOAD 0x00000002 // Counter=Load Interrupt
1190 #define PWM_3_ISC_INTCNTZERO 0x00000001 // Counter=0 Interrupt
1191 
1192 //*****************************************************************************
1193 //
1194 // The following are defines for the bit fields in the PWM_O_3_LOAD register.
1195 //
1196 //*****************************************************************************
1197 #define PWM_3_LOAD_LOAD_M 0x0000FFFF // Counter Load Value
1198 #define PWM_3_LOAD_LOAD_S 0
1199 
1200 //*****************************************************************************
1201 //
1202 // The following are defines for the bit fields in the PWM_O_3_COUNT register.
1203 //
1204 //*****************************************************************************
1205 #define PWM_3_COUNT_COUNT_M 0x0000FFFF // Counter Value
1206 #define PWM_3_COUNT_COUNT_S 0
1207 
1208 //*****************************************************************************
1209 //
1210 // The following are defines for the bit fields in the PWM_O_3_CMPA register.
1211 //
1212 //*****************************************************************************
1213 #define PWM_3_CMPA_COMPA_M 0x0000FFFF // Comparator A Value
1214 #define PWM_3_CMPA_COMPA_S 0
1215 
1216 //*****************************************************************************
1217 //
1218 // The following are defines for the bit fields in the PWM_O_3_CMPB register.
1219 //
1220 //*****************************************************************************
1221 #define PWM_3_CMPB_COMPB_M 0x0000FFFF // Comparator B Value
1222 #define PWM_3_CMPB_COMPB_S 0
1223 
1224 //*****************************************************************************
1225 //
1226 // The following are defines for the bit fields in the PWM_O_3_GENA register.
1227 //
1228 //*****************************************************************************
1229 #define PWM_3_GENA_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down
1230 #define PWM_3_GENA_ACTCMPBD_NONE \
1231  0x00000000 // Do nothing
1232 #define PWM_3_GENA_ACTCMPBD_INV 0x00000400 // Invert pwmA
1233 #define PWM_3_GENA_ACTCMPBD_ZERO \
1234  0x00000800 // Drive pwmA Low
1235 #define PWM_3_GENA_ACTCMPBD_ONE 0x00000C00 // Drive pwmA High
1236 #define PWM_3_GENA_ACTCMPBU_M 0x00000300 // Action for Comparator B Up
1237 #define PWM_3_GENA_ACTCMPBU_NONE \
1238  0x00000000 // Do nothing
1239 #define PWM_3_GENA_ACTCMPBU_INV 0x00000100 // Invert pwmA
1240 #define PWM_3_GENA_ACTCMPBU_ZERO \
1241  0x00000200 // Drive pwmA Low
1242 #define PWM_3_GENA_ACTCMPBU_ONE 0x00000300 // Drive pwmA High
1243 #define PWM_3_GENA_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down
1244 #define PWM_3_GENA_ACTCMPAD_NONE \
1245  0x00000000 // Do nothing
1246 #define PWM_3_GENA_ACTCMPAD_INV 0x00000040 // Invert pwmA
1247 #define PWM_3_GENA_ACTCMPAD_ZERO \
1248  0x00000080 // Drive pwmA Low
1249 #define PWM_3_GENA_ACTCMPAD_ONE 0x000000C0 // Drive pwmA High
1250 #define PWM_3_GENA_ACTCMPAU_M 0x00000030 // Action for Comparator A Up
1251 #define PWM_3_GENA_ACTCMPAU_NONE \
1252  0x00000000 // Do nothing
1253 #define PWM_3_GENA_ACTCMPAU_INV 0x00000010 // Invert pwmA
1254 #define PWM_3_GENA_ACTCMPAU_ZERO \
1255  0x00000020 // Drive pwmA Low
1256 #define PWM_3_GENA_ACTCMPAU_ONE 0x00000030 // Drive pwmA High
1257 #define PWM_3_GENA_ACTLOAD_M 0x0000000C // Action for Counter=LOAD
1258 #define PWM_3_GENA_ACTLOAD_NONE 0x00000000 // Do nothing
1259 #define PWM_3_GENA_ACTLOAD_INV 0x00000004 // Invert pwmA
1260 #define PWM_3_GENA_ACTLOAD_ZERO 0x00000008 // Drive pwmA Low
1261 #define PWM_3_GENA_ACTLOAD_ONE 0x0000000C // Drive pwmA High
1262 #define PWM_3_GENA_ACTZERO_M 0x00000003 // Action for Counter=0
1263 #define PWM_3_GENA_ACTZERO_NONE 0x00000000 // Do nothing
1264 #define PWM_3_GENA_ACTZERO_INV 0x00000001 // Invert pwmA
1265 #define PWM_3_GENA_ACTZERO_ZERO 0x00000002 // Drive pwmA Low
1266 #define PWM_3_GENA_ACTZERO_ONE 0x00000003 // Drive pwmA High
1267 
1268 //*****************************************************************************
1269 //
1270 // The following are defines for the bit fields in the PWM_O_3_GENB register.
1271 //
1272 //*****************************************************************************
1273 #define PWM_3_GENB_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down
1274 #define PWM_3_GENB_ACTCMPBD_NONE \
1275  0x00000000 // Do nothing
1276 #define PWM_3_GENB_ACTCMPBD_INV 0x00000400 // Invert pwmB
1277 #define PWM_3_GENB_ACTCMPBD_ZERO \
1278  0x00000800 // Drive pwmB Low
1279 #define PWM_3_GENB_ACTCMPBD_ONE 0x00000C00 // Drive pwmB High
1280 #define PWM_3_GENB_ACTCMPBU_M 0x00000300 // Action for Comparator B Up
1281 #define PWM_3_GENB_ACTCMPBU_NONE \
1282  0x00000000 // Do nothing
1283 #define PWM_3_GENB_ACTCMPBU_INV 0x00000100 // Invert pwmB
1284 #define PWM_3_GENB_ACTCMPBU_ZERO \
1285  0x00000200 // Drive pwmB Low
1286 #define PWM_3_GENB_ACTCMPBU_ONE 0x00000300 // Drive pwmB High
1287 #define PWM_3_GENB_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down
1288 #define PWM_3_GENB_ACTCMPAD_NONE \
1289  0x00000000 // Do nothing
1290 #define PWM_3_GENB_ACTCMPAD_INV 0x00000040 // Invert pwmB
1291 #define PWM_3_GENB_ACTCMPAD_ZERO \
1292  0x00000080 // Drive pwmB Low
1293 #define PWM_3_GENB_ACTCMPAD_ONE 0x000000C0 // Drive pwmB High
1294 #define PWM_3_GENB_ACTCMPAU_M 0x00000030 // Action for Comparator A Up
1295 #define PWM_3_GENB_ACTCMPAU_NONE \
1296  0x00000000 // Do nothing
1297 #define PWM_3_GENB_ACTCMPAU_INV 0x00000010 // Invert pwmB
1298 #define PWM_3_GENB_ACTCMPAU_ZERO \
1299  0x00000020 // Drive pwmB Low
1300 #define PWM_3_GENB_ACTCMPAU_ONE 0x00000030 // Drive pwmB High
1301 #define PWM_3_GENB_ACTLOAD_M 0x0000000C // Action for Counter=LOAD
1302 #define PWM_3_GENB_ACTLOAD_NONE 0x00000000 // Do nothing
1303 #define PWM_3_GENB_ACTLOAD_INV 0x00000004 // Invert pwmB
1304 #define PWM_3_GENB_ACTLOAD_ZERO 0x00000008 // Drive pwmB Low
1305 #define PWM_3_GENB_ACTLOAD_ONE 0x0000000C // Drive pwmB High
1306 #define PWM_3_GENB_ACTZERO_M 0x00000003 // Action for Counter=0
1307 #define PWM_3_GENB_ACTZERO_NONE 0x00000000 // Do nothing
1308 #define PWM_3_GENB_ACTZERO_INV 0x00000001 // Invert pwmB
1309 #define PWM_3_GENB_ACTZERO_ZERO 0x00000002 // Drive pwmB Low
1310 #define PWM_3_GENB_ACTZERO_ONE 0x00000003 // Drive pwmB High
1311 
1312 //*****************************************************************************
1313 //
1314 // The following are defines for the bit fields in the PWM_O_3_DBCTL register.
1315 //
1316 //*****************************************************************************
1317 #define PWM_3_DBCTL_ENABLE 0x00000001 // Dead-Band Generator Enable
1318 
1319 //*****************************************************************************
1320 //
1321 // The following are defines for the bit fields in the PWM_O_3_DBRISE register.
1322 //
1323 //*****************************************************************************
1324 #define PWM_3_DBRISE_RISEDELAY_M \
1325  0x00000FFF // Dead-Band Rise Delay
1326 #define PWM_3_DBRISE_RISEDELAY_S \
1327  0
1328 
1329 //*****************************************************************************
1330 //
1331 // The following are defines for the bit fields in the PWM_O_3_DBFALL register.
1332 //
1333 //*****************************************************************************
1334 #define PWM_3_DBFALL_FALLDELAY_M \
1335  0x00000FFF // Dead-Band Fall Delay
1336 #define PWM_3_DBFALL_FALLDELAY_S \
1337  0
1338 
1339 //*****************************************************************************
1340 //
1341 // The following are defines for the bit fields in the PWM_O_3_FLTSRC0
1342 // register.
1343 //
1344 //*****************************************************************************
1345 #define PWM_3_FLTSRC0_FAULT3 0x00000008 // Fault3 Input
1346 #define PWM_3_FLTSRC0_FAULT2 0x00000004 // Fault2 Input
1347 #define PWM_3_FLTSRC0_FAULT1 0x00000002 // Fault1 Input
1348 #define PWM_3_FLTSRC0_FAULT0 0x00000001 // Fault0 Input
1349 
1350 //*****************************************************************************
1351 //
1352 // The following are defines for the bit fields in the PWM_O_3_FLTSRC1
1353 // register.
1354 //
1355 //*****************************************************************************
1356 #define PWM_3_FLTSRC1_DCMP7 0x00000080 // Digital Comparator 7
1357 #define PWM_3_FLTSRC1_DCMP6 0x00000040 // Digital Comparator 6
1358 #define PWM_3_FLTSRC1_DCMP5 0x00000020 // Digital Comparator 5
1359 #define PWM_3_FLTSRC1_DCMP4 0x00000010 // Digital Comparator 4
1360 #define PWM_3_FLTSRC1_DCMP3 0x00000008 // Digital Comparator 3
1361 #define PWM_3_FLTSRC1_DCMP2 0x00000004 // Digital Comparator 2
1362 #define PWM_3_FLTSRC1_DCMP1 0x00000002 // Digital Comparator 1
1363 #define PWM_3_FLTSRC1_DCMP0 0x00000001 // Digital Comparator 0
1364 
1365 //*****************************************************************************
1366 //
1367 // The following are defines for the bit fields in the PWM_O_3_MINFLTPER
1368 // register.
1369 //
1370 //*****************************************************************************
1371 #define PWM_3_MINFLTPER_MFP_M 0x0000FFFF // Minimum Fault Period
1372 #define PWM_3_MINFLTPER_MFP_S 0
1373 
1374 //*****************************************************************************
1375 //
1376 // The following are defines for the bit fields in the PWM_O_0_FLTSEN register.
1377 //
1378 //*****************************************************************************
1379 #define PWM_0_FLTSEN_FAULT3 0x00000008 // Fault3 Sense
1380 #define PWM_0_FLTSEN_FAULT2 0x00000004 // Fault2 Sense
1381 #define PWM_0_FLTSEN_FAULT1 0x00000002 // Fault1 Sense
1382 #define PWM_0_FLTSEN_FAULT0 0x00000001 // Fault0 Sense
1383 
1384 //*****************************************************************************
1385 //
1386 // The following are defines for the bit fields in the PWM_O_0_FLTSTAT0
1387 // register.
1388 //
1389 //*****************************************************************************
1390 #define PWM_0_FLTSTAT0_FAULT3 0x00000008 // Fault Input 3
1391 #define PWM_0_FLTSTAT0_FAULT2 0x00000004 // Fault Input 2
1392 #define PWM_0_FLTSTAT0_FAULT1 0x00000002 // Fault Input 1
1393 #define PWM_0_FLTSTAT0_FAULT0 0x00000001 // Fault Input 0
1394 
1395 //*****************************************************************************
1396 //
1397 // The following are defines for the bit fields in the PWM_O_0_FLTSTAT1
1398 // register.
1399 //
1400 //*****************************************************************************
1401 #define PWM_0_FLTSTAT1_DCMP7 0x00000080 // Digital Comparator 7 Trigger
1402 #define PWM_0_FLTSTAT1_DCMP6 0x00000040 // Digital Comparator 6 Trigger
1403 #define PWM_0_FLTSTAT1_DCMP5 0x00000020 // Digital Comparator 5 Trigger
1404 #define PWM_0_FLTSTAT1_DCMP4 0x00000010 // Digital Comparator 4 Trigger
1405 #define PWM_0_FLTSTAT1_DCMP3 0x00000008 // Digital Comparator 3 Trigger
1406 #define PWM_0_FLTSTAT1_DCMP2 0x00000004 // Digital Comparator 2 Trigger
1407 #define PWM_0_FLTSTAT1_DCMP1 0x00000002 // Digital Comparator 1 Trigger
1408 #define PWM_0_FLTSTAT1_DCMP0 0x00000001 // Digital Comparator 0 Trigger
1409 
1410 //*****************************************************************************
1411 //
1412 // The following are defines for the bit fields in the PWM_O_1_FLTSEN register.
1413 //
1414 //*****************************************************************************
1415 #define PWM_1_FLTSEN_FAULT3 0x00000008 // Fault3 Sense
1416 #define PWM_1_FLTSEN_FAULT2 0x00000004 // Fault2 Sense
1417 #define PWM_1_FLTSEN_FAULT1 0x00000002 // Fault1 Sense
1418 #define PWM_1_FLTSEN_FAULT0 0x00000001 // Fault0 Sense
1419 
1420 //*****************************************************************************
1421 //
1422 // The following are defines for the bit fields in the PWM_O_1_FLTSTAT0
1423 // register.
1424 //
1425 //*****************************************************************************
1426 #define PWM_1_FLTSTAT0_FAULT3 0x00000008 // Fault Input 3
1427 #define PWM_1_FLTSTAT0_FAULT2 0x00000004 // Fault Input 2
1428 #define PWM_1_FLTSTAT0_FAULT1 0x00000002 // Fault Input 1
1429 #define PWM_1_FLTSTAT0_FAULT0 0x00000001 // Fault Input 0
1430 
1431 //*****************************************************************************
1432 //
1433 // The following are defines for the bit fields in the PWM_O_1_FLTSTAT1
1434 // register.
1435 //
1436 //*****************************************************************************
1437 #define PWM_1_FLTSTAT1_DCMP7 0x00000080 // Digital Comparator 7 Trigger
1438 #define PWM_1_FLTSTAT1_DCMP6 0x00000040 // Digital Comparator 6 Trigger
1439 #define PWM_1_FLTSTAT1_DCMP5 0x00000020 // Digital Comparator 5 Trigger
1440 #define PWM_1_FLTSTAT1_DCMP4 0x00000010 // Digital Comparator 4 Trigger
1441 #define PWM_1_FLTSTAT1_DCMP3 0x00000008 // Digital Comparator 3 Trigger
1442 #define PWM_1_FLTSTAT1_DCMP2 0x00000004 // Digital Comparator 2 Trigger
1443 #define PWM_1_FLTSTAT1_DCMP1 0x00000002 // Digital Comparator 1 Trigger
1444 #define PWM_1_FLTSTAT1_DCMP0 0x00000001 // Digital Comparator 0 Trigger
1445 
1446 //*****************************************************************************
1447 //
1448 // The following are defines for the bit fields in the PWM_O_2_FLTSEN register.
1449 //
1450 //*****************************************************************************
1451 #define PWM_2_FLTSEN_FAULT3 0x00000008 // Fault3 Sense
1452 #define PWM_2_FLTSEN_FAULT2 0x00000004 // Fault2 Sense
1453 #define PWM_2_FLTSEN_FAULT1 0x00000002 // Fault1 Sense
1454 #define PWM_2_FLTSEN_FAULT0 0x00000001 // Fault0 Sense
1455 
1456 //*****************************************************************************
1457 //
1458 // The following are defines for the bit fields in the PWM_O_2_FLTSTAT0
1459 // register.
1460 //
1461 //*****************************************************************************
1462 #define PWM_2_FLTSTAT0_FAULT3 0x00000008 // Fault Input 3
1463 #define PWM_2_FLTSTAT0_FAULT2 0x00000004 // Fault Input 2
1464 #define PWM_2_FLTSTAT0_FAULT1 0x00000002 // Fault Input 1
1465 #define PWM_2_FLTSTAT0_FAULT0 0x00000001 // Fault Input 0
1466 
1467 //*****************************************************************************
1468 //
1469 // The following are defines for the bit fields in the PWM_O_2_FLTSTAT1
1470 // register.
1471 //
1472 //*****************************************************************************
1473 #define PWM_2_FLTSTAT1_DCMP7 0x00000080 // Digital Comparator 7 Trigger
1474 #define PWM_2_FLTSTAT1_DCMP6 0x00000040 // Digital Comparator 6 Trigger
1475 #define PWM_2_FLTSTAT1_DCMP5 0x00000020 // Digital Comparator 5 Trigger
1476 #define PWM_2_FLTSTAT1_DCMP4 0x00000010 // Digital Comparator 4 Trigger
1477 #define PWM_2_FLTSTAT1_DCMP3 0x00000008 // Digital Comparator 3 Trigger
1478 #define PWM_2_FLTSTAT1_DCMP2 0x00000004 // Digital Comparator 2 Trigger
1479 #define PWM_2_FLTSTAT1_DCMP1 0x00000002 // Digital Comparator 1 Trigger
1480 #define PWM_2_FLTSTAT1_DCMP0 0x00000001 // Digital Comparator 0 Trigger
1481 
1482 //*****************************************************************************
1483 //
1484 // The following are defines for the bit fields in the PWM_O_3_FLTSEN register.
1485 //
1486 //*****************************************************************************
1487 #define PWM_3_FLTSEN_FAULT3 0x00000008 // Fault3 Sense
1488 #define PWM_3_FLTSEN_FAULT2 0x00000004 // Fault2 Sense
1489 #define PWM_3_FLTSEN_FAULT1 0x00000002 // Fault1 Sense
1490 #define PWM_3_FLTSEN_FAULT0 0x00000001 // Fault0 Sense
1491 
1492 //*****************************************************************************
1493 //
1494 // The following are defines for the bit fields in the PWM_O_3_FLTSTAT0
1495 // register.
1496 //
1497 //*****************************************************************************
1498 #define PWM_3_FLTSTAT0_FAULT3 0x00000008 // Fault Input 3
1499 #define PWM_3_FLTSTAT0_FAULT2 0x00000004 // Fault Input 2
1500 #define PWM_3_FLTSTAT0_FAULT1 0x00000002 // Fault Input 1
1501 #define PWM_3_FLTSTAT0_FAULT0 0x00000001 // Fault Input 0
1502 
1503 //*****************************************************************************
1504 //
1505 // The following are defines for the bit fields in the PWM_O_3_FLTSTAT1
1506 // register.
1507 //
1508 //*****************************************************************************
1509 #define PWM_3_FLTSTAT1_DCMP7 0x00000080 // Digital Comparator 7 Trigger
1510 #define PWM_3_FLTSTAT1_DCMP6 0x00000040 // Digital Comparator 6 Trigger
1511 #define PWM_3_FLTSTAT1_DCMP5 0x00000020 // Digital Comparator 5 Trigger
1512 #define PWM_3_FLTSTAT1_DCMP4 0x00000010 // Digital Comparator 4 Trigger
1513 #define PWM_3_FLTSTAT1_DCMP3 0x00000008 // Digital Comparator 3 Trigger
1514 #define PWM_3_FLTSTAT1_DCMP2 0x00000004 // Digital Comparator 2 Trigger
1515 #define PWM_3_FLTSTAT1_DCMP1 0x00000002 // Digital Comparator 1 Trigger
1516 #define PWM_3_FLTSTAT1_DCMP0 0x00000001 // Digital Comparator 0 Trigger
1517 
1518 //*****************************************************************************
1519 //
1520 // The following are defines for the bit fields in the PWM_O_PP register.
1521 //
1522 //*****************************************************************************
1523 #define PWM_PP_GCNT_M 0x0000000F // Generators
1524 #define PWM_PP_FCNT_M 0x000000F0 // Fault Inputs (per PWM unit)
1525 #define PWM_PP_ESYNC 0x00000100 // Extended Synchronization
1526 #define PWM_PP_EFAULT 0x00000200 // Extended Fault
1527 #define PWM_PP_ONE 0x00000400 // One-Shot Mode
1528 #define PWM_PP_GCNT_S 0
1529 #define PWM_PP_FCNT_S 4
1530 
1531 //*****************************************************************************
1532 //
1533 // The following are defines for the bit fields in the PWM_O_CC register.
1534 //
1535 //*****************************************************************************
1536 #define PWM_CC_USEPWM 0x00000100 // Use PWM Clock Divisor
1537 #define PWM_CC_PWMDIV_M 0x00000007 // PWM Clock Divider
1538 #define PWM_CC_PWMDIV_2 0x00000000 // /2
1539 #define PWM_CC_PWMDIV_4 0x00000001 // /4
1540 #define PWM_CC_PWMDIV_8 0x00000002 // /8
1541 #define PWM_CC_PWMDIV_16 0x00000003 // /16
1542 #define PWM_CC_PWMDIV_32 0x00000004 // /32
1543 #define PWM_CC_PWMDIV_64 0x00000005 // /64
1544 
1545 //*****************************************************************************
1546 //
1547 // The following are defines for the PWM Generator standard offsets.
1548 //
1549 //*****************************************************************************
1550 #define PWM_O_X_CTL 0x00000000 // Gen Control Reg
1551 #define PWM_O_X_INTEN 0x00000004 // Gen Int/Trig Enable Reg
1552 #define PWM_O_X_RIS 0x00000008 // Gen Raw Int Status Reg
1553 #define PWM_O_X_ISC 0x0000000C // Gen Int Status Reg
1554 #define PWM_O_X_LOAD 0x00000010 // Gen Load Reg
1555 #define PWM_O_X_COUNT 0x00000014 // Gen Counter Reg
1556 #define PWM_O_X_CMPA 0x00000018 // Gen Compare A Reg
1557 #define PWM_O_X_CMPB 0x0000001C // Gen Compare B Reg
1558 #define PWM_O_X_GENA 0x00000020 // Gen Generator A Ctrl Reg
1559 #define PWM_O_X_GENB 0x00000024 // Gen Generator B Ctrl Reg
1560 #define PWM_O_X_DBCTL 0x00000028 // Gen Dead Band Ctrl Reg
1561 #define PWM_O_X_DBRISE 0x0000002C // Gen DB Rising Edge Delay Reg
1562 #define PWM_O_X_DBFALL 0x00000030 // Gen DB Falling Edge Delay Reg
1563 #define PWM_O_X_FLTSRC0 0x00000034 // Fault pin, comparator condition
1564 #define PWM_O_X_FLTSRC1 0x00000038 // Digital comparator condition
1565 #define PWM_O_X_MINFLTPER 0x0000003C // Fault minimum period extension
1566 #define PWM_GEN_0_OFFSET 0x00000040 // PWM0 base
1567 #define PWM_GEN_1_OFFSET 0x00000080 // PWM1 base
1568 #define PWM_GEN_2_OFFSET 0x000000C0 // PWM2 base
1569 #define PWM_GEN_3_OFFSET 0x00000100 // PWM3 base
1570 
1571 //*****************************************************************************
1572 //
1573 // The following are defines for the bit fields in the PWM_O_X_CTL register.
1574 //
1575 //*****************************************************************************
1576 #define PWM_X_CTL_LATCH 0x00040000 // Latch Fault Input
1577 #define PWM_X_CTL_MINFLTPER 0x00020000 // Minimum Fault Period
1578 #define PWM_X_CTL_FLTSRC 0x00010000 // Fault Condition Source
1579 #define PWM_X_CTL_DBFALLUPD_M 0x0000C000 // PWMnDBFALL Update Mode
1580 #define PWM_X_CTL_DBFALLUPD_I 0x00000000 // Immediate
1581 #define PWM_X_CTL_DBFALLUPD_LS 0x00008000 // Locally Synchronized
1582 #define PWM_X_CTL_DBFALLUPD_GS 0x0000C000 // Globally Synchronized
1583 #define PWM_X_CTL_DBRISEUPD_M 0x00003000 // PWMnDBRISE Update Mode
1584 #define PWM_X_CTL_DBRISEUPD_I 0x00000000 // Immediate
1585 #define PWM_X_CTL_DBRISEUPD_LS 0x00002000 // Locally Synchronized
1586 #define PWM_X_CTL_DBRISEUPD_GS 0x00003000 // Globally Synchronized
1587 #define PWM_X_CTL_DBCTLUPD_M 0x00000C00 // PWMnDBCTL Update Mode
1588 #define PWM_X_CTL_DBCTLUPD_I 0x00000000 // Immediate
1589 #define PWM_X_CTL_DBCTLUPD_LS 0x00000800 // Locally Synchronized
1590 #define PWM_X_CTL_DBCTLUPD_GS 0x00000C00 // Globally Synchronized
1591 #define PWM_X_CTL_GENBUPD_M 0x00000300 // PWMnGENB Update Mode
1592 #define PWM_X_CTL_GENBUPD_I 0x00000000 // Immediate
1593 #define PWM_X_CTL_GENBUPD_LS 0x00000200 // Locally Synchronized
1594 #define PWM_X_CTL_GENBUPD_GS 0x00000300 // Globally Synchronized
1595 #define PWM_X_CTL_GENAUPD_M 0x000000C0 // PWMnGENA Update Mode
1596 #define PWM_X_CTL_GENAUPD_I 0x00000000 // Immediate
1597 #define PWM_X_CTL_GENAUPD_LS 0x00000080 // Locally Synchronized
1598 #define PWM_X_CTL_GENAUPD_GS 0x000000C0 // Globally Synchronized
1599 #define PWM_X_CTL_CMPBUPD 0x00000020 // Comparator B Update Mode
1600 #define PWM_X_CTL_CMPAUPD 0x00000010 // Comparator A Update Mode
1601 #define PWM_X_CTL_LOADUPD 0x00000008 // Load Register Update Mode
1602 #define PWM_X_CTL_DEBUG 0x00000004 // Debug Mode
1603 #define PWM_X_CTL_MODE 0x00000002 // Counter Mode
1604 #define PWM_X_CTL_ENABLE 0x00000001 // PWM Block Enable
1605 
1606 //*****************************************************************************
1607 //
1608 // The following are defines for the bit fields in the PWM_O_X_INTEN register.
1609 //
1610 //*****************************************************************************
1611 #define PWM_X_INTEN_TRCMPBD 0x00002000 // Trigger for Counter=PWMnCMPB
1612  // Down
1613 #define PWM_X_INTEN_TRCMPBU 0x00001000 // Trigger for Counter=PWMnCMPB Up
1614 #define PWM_X_INTEN_TRCMPAD 0x00000800 // Trigger for Counter=PWMnCMPA
1615  // Down
1616 #define PWM_X_INTEN_TRCMPAU 0x00000400 // Trigger for Counter=PWMnCMPA Up
1617 #define PWM_X_INTEN_TRCNTLOAD 0x00000200 // Trigger for Counter=PWMnLOAD
1618 #define PWM_X_INTEN_TRCNTZERO 0x00000100 // Trigger for Counter=0
1619 #define PWM_X_INTEN_INTCMPBD 0x00000020 // Interrupt for Counter=PWMnCMPB
1620  // Down
1621 #define PWM_X_INTEN_INTCMPBU 0x00000010 // Interrupt for Counter=PWMnCMPB
1622  // Up
1623 #define PWM_X_INTEN_INTCMPAD 0x00000008 // Interrupt for Counter=PWMnCMPA
1624  // Down
1625 #define PWM_X_INTEN_INTCMPAU 0x00000004 // Interrupt for Counter=PWMnCMPA
1626  // Up
1627 #define PWM_X_INTEN_INTCNTLOAD 0x00000002 // Interrupt for Counter=PWMnLOAD
1628 #define PWM_X_INTEN_INTCNTZERO 0x00000001 // Interrupt for Counter=0
1629 
1630 //*****************************************************************************
1631 //
1632 // The following are defines for the bit fields in the PWM_O_X_RIS register.
1633 //
1634 //*****************************************************************************
1635 #define PWM_X_RIS_INTCMPBD 0x00000020 // Comparator B Down Interrupt
1636  // Status
1637 #define PWM_X_RIS_INTCMPBU 0x00000010 // Comparator B Up Interrupt Status
1638 #define PWM_X_RIS_INTCMPAD 0x00000008 // Comparator A Down Interrupt
1639  // Status
1640 #define PWM_X_RIS_INTCMPAU 0x00000004 // Comparator A Up Interrupt Status
1641 #define PWM_X_RIS_INTCNTLOAD 0x00000002 // Counter=Load Interrupt Status
1642 #define PWM_X_RIS_INTCNTZERO 0x00000001 // Counter=0 Interrupt Status
1643 
1644 //*****************************************************************************
1645 //
1646 // The following are defines for the bit fields in the PWM_O_X_ISC register.
1647 //
1648 //*****************************************************************************
1649 #define PWM_X_ISC_INTCMPBD 0x00000020 // Comparator B Down Interrupt
1650 #define PWM_X_ISC_INTCMPBU 0x00000010 // Comparator B Up Interrupt
1651 #define PWM_X_ISC_INTCMPAD 0x00000008 // Comparator A Down Interrupt
1652 #define PWM_X_ISC_INTCMPAU 0x00000004 // Comparator A Up Interrupt
1653 #define PWM_X_ISC_INTCNTLOAD 0x00000002 // Counter=Load Interrupt
1654 #define PWM_X_ISC_INTCNTZERO 0x00000001 // Counter=0 Interrupt
1655 
1656 //*****************************************************************************
1657 //
1658 // The following are defines for the bit fields in the PWM_O_X_LOAD register.
1659 //
1660 //*****************************************************************************
1661 #define PWM_X_LOAD_M 0x0000FFFF // Counter Load Value
1662 #define PWM_X_LOAD_S 0
1663 
1664 //*****************************************************************************
1665 //
1666 // The following are defines for the bit fields in the PWM_O_X_COUNT register.
1667 //
1668 //*****************************************************************************
1669 #define PWM_X_COUNT_M 0x0000FFFF // Counter Value
1670 #define PWM_X_COUNT_S 0
1671 
1672 //*****************************************************************************
1673 //
1674 // The following are defines for the bit fields in the PWM_O_X_CMPA register.
1675 //
1676 //*****************************************************************************
1677 #define PWM_X_CMPA_M 0x0000FFFF // Comparator A Value
1678 #define PWM_X_CMPA_S 0
1679 
1680 //*****************************************************************************
1681 //
1682 // The following are defines for the bit fields in the PWM_O_X_CMPB register.
1683 //
1684 //*****************************************************************************
1685 #define PWM_X_CMPB_M 0x0000FFFF // Comparator B Value
1686 #define PWM_X_CMPB_S 0
1687 
1688 //*****************************************************************************
1689 //
1690 // The following are defines for the bit fields in the PWM_O_X_GENA register.
1691 //
1692 //*****************************************************************************
1693 #define PWM_X_GENA_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down
1694 #define PWM_X_GENA_ACTCMPBD_NONE \
1695  0x00000000 // Do nothing
1696 #define PWM_X_GENA_ACTCMPBD_INV 0x00000400 // Invert pwmA
1697 #define PWM_X_GENA_ACTCMPBD_ZERO \
1698  0x00000800 // Drive pwmA Low
1699 #define PWM_X_GENA_ACTCMPBD_ONE 0x00000C00 // Drive pwmA High
1700 #define PWM_X_GENA_ACTCMPBU_M 0x00000300 // Action for Comparator B Up
1701 #define PWM_X_GENA_ACTCMPBU_NONE \
1702  0x00000000 // Do nothing
1703 #define PWM_X_GENA_ACTCMPBU_INV 0x00000100 // Invert pwmA
1704 #define PWM_X_GENA_ACTCMPBU_ZERO \
1705  0x00000200 // Drive pwmA Low
1706 #define PWM_X_GENA_ACTCMPBU_ONE 0x00000300 // Drive pwmA High
1707 #define PWM_X_GENA_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down
1708 #define PWM_X_GENA_ACTCMPAD_NONE \
1709  0x00000000 // Do nothing
1710 #define PWM_X_GENA_ACTCMPAD_INV 0x00000040 // Invert pwmA
1711 #define PWM_X_GENA_ACTCMPAD_ZERO \
1712  0x00000080 // Drive pwmA Low
1713 #define PWM_X_GENA_ACTCMPAD_ONE 0x000000C0 // Drive pwmA High
1714 #define PWM_X_GENA_ACTCMPAU_M 0x00000030 // Action for Comparator A Up
1715 #define PWM_X_GENA_ACTCMPAU_NONE \
1716  0x00000000 // Do nothing
1717 #define PWM_X_GENA_ACTCMPAU_INV 0x00000010 // Invert pwmA
1718 #define PWM_X_GENA_ACTCMPAU_ZERO \
1719  0x00000020 // Drive pwmA Low
1720 #define PWM_X_GENA_ACTCMPAU_ONE 0x00000030 // Drive pwmA High
1721 #define PWM_X_GENA_ACTLOAD_M 0x0000000C // Action for Counter=LOAD
1722 #define PWM_X_GENA_ACTLOAD_NONE 0x00000000 // Do nothing
1723 #define PWM_X_GENA_ACTLOAD_INV 0x00000004 // Invert pwmA
1724 #define PWM_X_GENA_ACTLOAD_ZERO 0x00000008 // Drive pwmA Low
1725 #define PWM_X_GENA_ACTLOAD_ONE 0x0000000C // Drive pwmA High
1726 #define PWM_X_GENA_ACTZERO_M 0x00000003 // Action for Counter=0
1727 #define PWM_X_GENA_ACTZERO_NONE 0x00000000 // Do nothing
1728 #define PWM_X_GENA_ACTZERO_INV 0x00000001 // Invert pwmA
1729 #define PWM_X_GENA_ACTZERO_ZERO 0x00000002 // Drive pwmA Low
1730 #define PWM_X_GENA_ACTZERO_ONE 0x00000003 // Drive pwmA High
1731 
1732 //*****************************************************************************
1733 //
1734 // The following are defines for the bit fields in the PWM_O_X_GENB register.
1735 //
1736 //*****************************************************************************
1737 #define PWM_X_GENB_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down
1738 #define PWM_X_GENB_ACTCMPBD_NONE \
1739  0x00000000 // Do nothing
1740 #define PWM_X_GENB_ACTCMPBD_INV 0x00000400 // Invert pwmB
1741 #define PWM_X_GENB_ACTCMPBD_ZERO \
1742  0x00000800 // Drive pwmB Low
1743 #define PWM_X_GENB_ACTCMPBD_ONE 0x00000C00 // Drive pwmB High
1744 #define PWM_X_GENB_ACTCMPBU_M 0x00000300 // Action for Comparator B Up
1745 #define PWM_X_GENB_ACTCMPBU_NONE \
1746  0x00000000 // Do nothing
1747 #define PWM_X_GENB_ACTCMPBU_INV 0x00000100 // Invert pwmB
1748 #define PWM_X_GENB_ACTCMPBU_ZERO \
1749  0x00000200 // Drive pwmB Low
1750 #define PWM_X_GENB_ACTCMPBU_ONE 0x00000300 // Drive pwmB High
1751 #define PWM_X_GENB_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down
1752 #define PWM_X_GENB_ACTCMPAD_NONE \
1753  0x00000000 // Do nothing
1754 #define PWM_X_GENB_ACTCMPAD_INV 0x00000040 // Invert pwmB
1755 #define PWM_X_GENB_ACTCMPAD_ZERO \
1756  0x00000080 // Drive pwmB Low
1757 #define PWM_X_GENB_ACTCMPAD_ONE 0x000000C0 // Drive pwmB High
1758 #define PWM_X_GENB_ACTCMPAU_M 0x00000030 // Action for Comparator A Up
1759 #define PWM_X_GENB_ACTCMPAU_NONE \
1760  0x00000000 // Do nothing
1761 #define PWM_X_GENB_ACTCMPAU_INV 0x00000010 // Invert pwmB
1762 #define PWM_X_GENB_ACTCMPAU_ZERO \
1763  0x00000020 // Drive pwmB Low
1764 #define PWM_X_GENB_ACTCMPAU_ONE 0x00000030 // Drive pwmB High
1765 #define PWM_X_GENB_ACTLOAD_M 0x0000000C // Action for Counter=LOAD
1766 #define PWM_X_GENB_ACTLOAD_NONE 0x00000000 // Do nothing
1767 #define PWM_X_GENB_ACTLOAD_INV 0x00000004 // Invert pwmB
1768 #define PWM_X_GENB_ACTLOAD_ZERO 0x00000008 // Drive pwmB Low
1769 #define PWM_X_GENB_ACTLOAD_ONE 0x0000000C // Drive pwmB High
1770 #define PWM_X_GENB_ACTZERO_M 0x00000003 // Action for Counter=0
1771 #define PWM_X_GENB_ACTZERO_NONE 0x00000000 // Do nothing
1772 #define PWM_X_GENB_ACTZERO_INV 0x00000001 // Invert pwmB
1773 #define PWM_X_GENB_ACTZERO_ZERO 0x00000002 // Drive pwmB Low
1774 #define PWM_X_GENB_ACTZERO_ONE 0x00000003 // Drive pwmB High
1775 
1776 //*****************************************************************************
1777 //
1778 // The following are defines for the bit fields in the PWM_O_X_DBCTL register.
1779 //
1780 //*****************************************************************************
1781 #define PWM_X_DBCTL_ENABLE 0x00000001 // Dead-Band Generator Enable
1782 
1783 //*****************************************************************************
1784 //
1785 // The following are defines for the bit fields in the PWM_O_X_DBRISE register.
1786 //
1787 //*****************************************************************************
1788 #define PWM_X_DBRISE_DELAY_M 0x00000FFF // Dead-Band Rise Delay
1789 #define PWM_X_DBRISE_DELAY_S 0
1790 
1791 //*****************************************************************************
1792 //
1793 // The following are defines for the bit fields in the PWM_O_X_DBFALL register.
1794 //
1795 //*****************************************************************************
1796 #define PWM_X_DBFALL_DELAY_M 0x00000FFF // Dead-Band Fall Delay
1797 #define PWM_X_DBFALL_DELAY_S 0
1798 
1799 //*****************************************************************************
1800 //
1801 // The following are defines for the bit fields in the PWM_O_X_FLTSRC0
1802 // register.
1803 //
1804 //*****************************************************************************
1805 #define PWM_X_FLTSRC0_FAULT3 0x00000008 // Fault3 Input
1806 #define PWM_X_FLTSRC0_FAULT2 0x00000004 // Fault2 Input
1807 #define PWM_X_FLTSRC0_FAULT1 0x00000002 // Fault1 Input
1808 #define PWM_X_FLTSRC0_FAULT0 0x00000001 // Fault0 Input
1809 
1810 //*****************************************************************************
1811 //
1812 // The following are defines for the bit fields in the PWM_O_X_FLTSRC1
1813 // register.
1814 //
1815 //*****************************************************************************
1816 #define PWM_X_FLTSRC1_DCMP7 0x00000080 // Digital Comparator 7
1817 #define PWM_X_FLTSRC1_DCMP6 0x00000040 // Digital Comparator 6
1818 #define PWM_X_FLTSRC1_DCMP5 0x00000020 // Digital Comparator 5
1819 #define PWM_X_FLTSRC1_DCMP4 0x00000010 // Digital Comparator 4
1820 #define PWM_X_FLTSRC1_DCMP3 0x00000008 // Digital Comparator 3
1821 #define PWM_X_FLTSRC1_DCMP2 0x00000004 // Digital Comparator 2
1822 #define PWM_X_FLTSRC1_DCMP1 0x00000002 // Digital Comparator 1
1823 #define PWM_X_FLTSRC1_DCMP0 0x00000001 // Digital Comparator 0
1824 
1825 //*****************************************************************************
1826 //
1827 // The following are defines for the bit fields in the PWM_O_X_MINFLTPER
1828 // register.
1829 //
1830 //*****************************************************************************
1831 #define PWM_X_MINFLTPER_M 0x0000FFFF // Minimum Fault Period
1832 #define PWM_X_MINFLTPER_S 0
1833 
1834 //*****************************************************************************
1835 //
1836 // The following are defines for the PWM Generator extended offsets.
1837 //
1838 //*****************************************************************************
1839 #define PWM_O_X_FLTSEN 0x00000000 // Fault logic sense
1840 #define PWM_O_X_FLTSTAT0 0x00000004 // Pin and comparator status
1841 #define PWM_O_X_FLTSTAT1 0x00000008 // Digital comparator status
1842 #define PWM_EXT_0_OFFSET 0x00000800 // PWM0 extended base
1843 #define PWM_EXT_1_OFFSET 0x00000880 // PWM1 extended base
1844 #define PWM_EXT_2_OFFSET 0x00000900 // PWM2 extended base
1845 #define PWM_EXT_3_OFFSET 0x00000980 // PWM3 extended base
1846 
1847 //*****************************************************************************
1848 //
1849 // The following are defines for the bit fields in the PWM_O_X_FLTSEN register.
1850 //
1851 //*****************************************************************************
1852 #define PWM_X_FLTSEN_FAULT3 0x00000008 // Fault3 Sense
1853 #define PWM_X_FLTSEN_FAULT2 0x00000004 // Fault2 Sense
1854 #define PWM_X_FLTSEN_FAULT1 0x00000002 // Fault1 Sense
1855 #define PWM_X_FLTSEN_FAULT0 0x00000001 // Fault0 Sense
1856 
1857 //*****************************************************************************
1858 //
1859 // The following are defines for the bit fields in the PWM_O_X_FLTSTAT0
1860 // register.
1861 //
1862 //*****************************************************************************
1863 #define PWM_X_FLTSTAT0_FAULT3 0x00000008 // Fault Input 3
1864 #define PWM_X_FLTSTAT0_FAULT2 0x00000004 // Fault Input 2
1865 #define PWM_X_FLTSTAT0_FAULT1 0x00000002 // Fault Input 1
1866 #define PWM_X_FLTSTAT0_FAULT0 0x00000001 // Fault Input 0
1867 
1868 //*****************************************************************************
1869 //
1870 // The following are defines for the bit fields in the PWM_O_X_FLTSTAT1
1871 // register.
1872 //
1873 //*****************************************************************************
1874 #define PWM_X_FLTSTAT1_DCMP7 0x00000080 // Digital Comparator 7 Trigger
1875 #define PWM_X_FLTSTAT1_DCMP6 0x00000040 // Digital Comparator 6 Trigger
1876 #define PWM_X_FLTSTAT1_DCMP5 0x00000020 // Digital Comparator 5 Trigger
1877 #define PWM_X_FLTSTAT1_DCMP4 0x00000010 // Digital Comparator 4 Trigger
1878 #define PWM_X_FLTSTAT1_DCMP3 0x00000008 // Digital Comparator 3 Trigger
1879 #define PWM_X_FLTSTAT1_DCMP2 0x00000004 // Digital Comparator 2 Trigger
1880 #define PWM_X_FLTSTAT1_DCMP1 0x00000002 // Digital Comparator 1 Trigger
1881 #define PWM_X_FLTSTAT1_DCMP0 0x00000001 // Digital Comparator 0 Trigger
1882 
1883 #endif // __HW_PWM_H__
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