MSP432E4 DriverLib API Guide  1.11.00.03
hw_lcd.h
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1 //*****************************************************************************
2 //
3 // hw_lcd.h - Defines and macros used when accessing the LCD controller.
4 //
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37 
38 #ifndef __HW_LCD_H__
39 #define __HW_LCD_H__
40 
41 //*****************************************************************************
42 //
43 // The following are defines for the LCD register offsets.
44 //
45 //*****************************************************************************
46 #define LCD_O_PID 0x00000000 // LCD PID Register Format
47 #define LCD_O_CTL 0x00000004 // LCD Control
48 #define LCD_O_LIDDCTL 0x0000000C // LCD LIDD Control
49 #define LCD_O_LIDDCS0CFG 0x00000010 // LCD LIDD CS0 Configuration
50 #define LCD_O_LIDDCS0ADDR 0x00000014 // LIDD CS0 Read/Write Address
51 #define LCD_O_LIDDCS0DATA 0x00000018 // LIDD CS0 Data Read/Write
52  // Initiation
53 #define LCD_O_LIDDCS1CFG 0x0000001C // LIDD CS1 Configuration
54 #define LCD_O_LIDDCS1ADDR 0x00000020 // LIDD CS1 Address Read/Write
55  // Initiation
56 #define LCD_O_LIDDCS1DATA 0x00000024 // LIDD CS1 Data Read/Write
57  // Initiation
58 #define LCD_O_RASTRCTL 0x00000028 // LCD Raster Control
59 #define LCD_O_RASTRTIM0 0x0000002C // LCD Raster Timing 0
60 #define LCD_O_RASTRTIM1 0x00000030 // LCD Raster Timing 1
61 #define LCD_O_RASTRTIM2 0x00000034 // LCD Raster Timing 2
62 #define LCD_O_RASTRSUBP1 0x00000038 // LCD Raster Subpanel Display 1
63 #define LCD_O_RASTRSUBP2 0x0000003C // LCD Raster Subpanel Display 2
64 #define LCD_O_DMACTL 0x00000040 // LCD DMA Control
65 #define LCD_O_DMABAFB0 0x00000044 // LCD DMA Frame Buffer 0 Base
66  // Address
67 #define LCD_O_DMACAFB0 0x00000048 // LCD DMA Frame Buffer 0 Ceiling
68  // Address
69 #define LCD_O_DMABAFB1 0x0000004C // LCD DMA Frame Buffer 1 Base
70  // Address
71 #define LCD_O_DMACAFB1 0x00000050 // LCD DMA Frame Buffer 1 Ceiling
72  // Address
73 #define LCD_O_SYSCFG 0x00000054 // LCD System Configuration
74  // Register
75 #define LCD_O_RISSET 0x00000058 // LCD Interrupt Raw Status and Set
76  // Register
77 #define LCD_O_MISCLR 0x0000005C // LCD Interrupt Status and Clear
78 #define LCD_O_IM 0x00000060 // LCD Interrupt Mask
79 #define LCD_O_IENC 0x00000064 // LCD Interrupt Enable Clear
80 #define LCD_O_CLKEN 0x0000006C // LCD Clock Enable
81 #define LCD_O_CLKRESET 0x00000070 // LCD Clock Resets
82 
83 //*****************************************************************************
84 //
85 // The following are defines for the bit fields in the LCD_O_PID register.
86 //
87 //*****************************************************************************
88 #define LCD_PID_MAJOR_M 0x00000700 // Major Release Number
89 #define LCD_PID_MINOR_M 0x0000003F // Minor Release Number
90 #define LCD_PID_MAJOR_S 8
91 #define LCD_PID_MINOR_S 0
92 
93 //*****************************************************************************
94 //
95 // The following are defines for the bit fields in the LCD_O_CTL register.
96 //
97 //*****************************************************************************
98 #define LCD_CTL_CLKDIV_M 0x0000FF00 // Clock Divisor
99 #define LCD_CTL_UFLOWRST 0x00000002 // Underflow Restart
100 #define LCD_CTL_LCDMODE 0x00000001 // LCD Mode Select
101 #define LCD_CTL_CLKDIV_S 8
102 
103 //*****************************************************************************
104 //
105 // The following are defines for the bit fields in the LCD_O_LIDDCTL register.
106 //
107 //*****************************************************************************
108 #define LCD_LIDDCTL_DMACS 0x00000200 // CS0/CS1 Select for LIDD DMA
109  // Writes
110 #define LCD_LIDDCTL_DMAEN 0x00000100 // LIDD DMA Enable
111 #define LCD_LIDDCTL_CS1E1 0x00000080 // Chip Select 1 (CS1)/Enable 1(E1)
112  // Polarity Control
113 #define LCD_LIDDCTL_CS0E0 0x00000040 // Chip Select 0 (CS0)/Enable 0
114  // (E0) Polarity Control
115 #define LCD_LIDDCTL_WRDIRINV 0x00000020 // Write Strobe (WR) /Direction
116  // (DIR) Polarity Control
117 #define LCD_LIDDCTL_RDEN 0x00000010 // Read Strobe (RD) /Direct Enable
118  // (EN) Polarity Control
119 #define LCD_LIDDCTL_ALE 0x00000008 // Address Latch Enable (ALE)
120  // Polarity Control
121 #define LCD_LIDDCTL_MODE_M 0x00000007 // LIDD Mode Select
122 #define LCD_LIDDCTL_MODE_SYNCM68 \
123  0x00000000 // Synchronous Motorola 6800 Mode
124 #define LCD_LIDDCTL_MODE_ASYNCM68 \
125  0x00000001 // Asynchronous Motorola 6800 Mode
126 #define LCD_LIDDCTL_MODE_SYNCM80 \
127  0x00000002 // Synchronous Intel 8080 mode
128 #define LCD_LIDDCTL_MODE_ASYNCM80 \
129  0x00000003 // Asynchronous Intel 8080 mode
130 #define LCD_LIDDCTL_MODE_ASYNCHIT \
131  0x00000004 // Asynchronous Hitachi mode
132 
133 //*****************************************************************************
134 //
135 // The following are defines for the bit fields in the LCD_O_LIDDCS0CFG
136 // register.
137 //
138 //*****************************************************************************
139 #define LCD_LIDDCS0CFG_WRSU_M 0xF8000000 // Write Strobe (WR) Set-Up Cycles
140 #define LCD_LIDDCS0CFG_WRDUR_M 0x07E00000 // Write Strobe (WR) Duration
141  // Cycles
142 #define LCD_LIDDCS0CFG_WRHOLD_M 0x001E0000 // Write Strobe (WR) Hold cycles
143 #define LCD_LIDDCS0CFG_RDSU_M 0x0001F000 // Read Strobe (RD) Set-Up cycles
144 #define LCD_LIDDCS0CFG_RDDUR_M 0x00000FC0 // Read Strobe (RD) Duration cycles
145 #define LCD_LIDDCS0CFG_RDHOLD_M 0x0000003C // Read Strobe (RD) Hold cycles
146 #define LCD_LIDDCS0CFG_GAP_M 0x00000003 // Field value defines the number
147  // of LCDMCLK cycles (GAP +1)
148  // between the end of one CS0
149  // (LCDAC) device access and the
150  // start of another CS0 (LCDAC)
151  // device access unless the two
152  // accesses are both reads
153 #define LCD_LIDDCS0CFG_WRSU_S 27
154 #define LCD_LIDDCS0CFG_WRDUR_S 21
155 #define LCD_LIDDCS0CFG_WRHOLD_S 17
156 #define LCD_LIDDCS0CFG_RDSU_S 12
157 #define LCD_LIDDCS0CFG_RDDUR_S 6
158 #define LCD_LIDDCS0CFG_RDHOLD_S 2
159 #define LCD_LIDDCS0CFG_GAP_S 0
160 
161 //*****************************************************************************
162 //
163 // The following are defines for the bit fields in the LCD_O_LIDDCS0ADDR
164 // register.
165 //
166 //*****************************************************************************
167 #define LCD_LIDDCS0ADDR_CS0ADDR_M \
168  0x0000FFFF // LCD Address
169 #define LCD_LIDDCS0ADDR_CS0ADDR_S \
170  0
171 
172 //*****************************************************************************
173 //
174 // The following are defines for the bit fields in the LCD_O_LIDDCS0DATA
175 // register.
176 //
177 //*****************************************************************************
178 #define LCD_LIDDCS0DATA_CS0DATA_M \
179  0x0000FFFF // LCD Data Read/Write
180 #define LCD_LIDDCS0DATA_CS0DATA_S \
181  0
182 
183 //*****************************************************************************
184 //
185 // The following are defines for the bit fields in the LCD_O_LIDDCS1CFG
186 // register.
187 //
188 //*****************************************************************************
189 #define LCD_LIDDCS1CFG_WRSU_M 0xF8000000 // Write Strobe (WR) Set-Up Cycles
190 #define LCD_LIDDCS1CFG_WRDUR_M 0x07E00000 // Write Strobe (WR) Duration
191  // Cycles
192 #define LCD_LIDDCS1CFG_WRHOLD_M 0x001E0000 // Write Strobe (WR) Hold cycles
193 #define LCD_LIDDCS1CFG_RDSU_M 0x0001F000 // Read Strobe (RD) Set-Up cycles
194 #define LCD_LIDDCS1CFG_RDDUR_M 0x00000FC0 // Read Strobe (RD) Duration cycles
195 #define LCD_LIDDCS1CFG_RDHOLD_M 0x0000003C // Read Strobe (RD) Hold cycles
196 #define LCD_LIDDCS1CFG_GAP_M 0x00000003 // Field value defines the number
197  // of LCDMCLK cycles (GAP + 1)
198  // between the end of one CS1
199  // (LCDAC) device access and the
200  // start of another CS0 (LCDAC)
201  // device access unless the two
202  // accesses are both reads
203 #define LCD_LIDDCS1CFG_WRSU_S 27
204 #define LCD_LIDDCS1CFG_WRDUR_S 21
205 #define LCD_LIDDCS1CFG_WRHOLD_S 17
206 #define LCD_LIDDCS1CFG_RDSU_S 12
207 #define LCD_LIDDCS1CFG_RDDUR_S 6
208 #define LCD_LIDDCS1CFG_RDHOLD_S 2
209 #define LCD_LIDDCS1CFG_GAP_S 0
210 
211 //*****************************************************************************
212 //
213 // The following are defines for the bit fields in the LCD_O_LIDDCS1ADDR
214 // register.
215 //
216 //*****************************************************************************
217 #define LCD_LIDDCS1ADDR_CS1ADDR_M \
218  0x0000FFFF // LCD Address Bus
219 #define LCD_LIDDCS1ADDR_CS1ADDR_S \
220  0
221 
222 //*****************************************************************************
223 //
224 // The following are defines for the bit fields in the LCD_O_LIDDCS1DATA
225 // register.
226 //
227 //*****************************************************************************
228 #define LCD_LIDDCS1DATA_CS0DATA_M \
229  0x0000FFFF // LCD Data Read/Write Initiation
230 #define LCD_LIDDCS1DATA_CS0DATA_S \
231  0
232 
233 //*****************************************************************************
234 //
235 // The following are defines for the bit fields in the LCD_O_RASTRCTL register.
236 //
237 //*****************************************************************************
238 #define LCD_RASTRCTL_TFT24UPCK 0x04000000 // 24-bit TFT Mode Packing
239 #define LCD_RASTRCTL_TFT24 0x02000000 // 24-Bit TFT Mode
240 #define LCD_RASTRCTL_FRMBUFSZ 0x01000000 // Frame Buffer Select
241 #define LCD_RASTRCTL_TFTMAP 0x00800000 // TFT Mode Alternate Signal
242  // Mapping for Palettized
243  // Framebuffer
244 #define LCD_RASTRCTL_NIBMODE 0x00400000 // Nibble Mode
245 #define LCD_RASTRCTL_PALMODE_M 0x00300000 // Pallette Loading Mode
246 #define LCD_RASTRCTL_PALMODE_PALDAT \
247  0x00000000 // Palette and data loading, reset
248  // value
249 #define LCD_RASTRCTL_PALMODE_PAL \
250  0x00100000 // Palette loading only
251 #define LCD_RASTRCTL_PALMODE_DAT \
252  0x00200000 // Data loading only
253 #define LCD_RASTRCTL_REQDLY_M 0x000FF000 // Palette Loading Delay
254 #define LCD_RASTRCTL_MONO8B 0x00000200 // Mono 8-Bit
255 #define LCD_RASTRCTL_RDORDER 0x00000100 // Raster Data Order Select
256 #define LCD_RASTRCTL_LCDTFT 0x00000080 // LCD TFT
257 #define LCD_RASTRCTL_LCDBW 0x00000002 // LCD Monochrome
258 #define LCD_RASTRCTL_LCDEN 0x00000001 // LCD Controller Enable for Raster
259  // Operations
260 #define LCD_RASTRCTL_REQDLY_S 12
261 
262 //*****************************************************************************
263 //
264 // The following are defines for the bit fields in the LCD_O_RASTRTIM0
265 // register.
266 //
267 //*****************************************************************************
268 #define LCD_RASTRTIM0_HBP_M 0xFF000000 // Horizontal Back Porch Lowbits
269 #define LCD_RASTRTIM0_HFP_M 0x00FF0000 // Horizontal Front Porch Lowbits
270 #define LCD_RASTRTIM0_HSW_M 0x0000FC00 // Horizontal Sync Pulse Width
271  // Lowbits
272 #define LCD_RASTRTIM0_PPL_M 0x000003F0 // Pixels-per-line LSB[9:4]
273 #define LCD_RASTRTIM0_MSBPPL 0x00000008 // Pixels-per-line MSB[10]
274 #define LCD_RASTRTIM0_HBP_S 24
275 #define LCD_RASTRTIM0_HFP_S 16
276 #define LCD_RASTRTIM0_HSW_S 10
277 #define LCD_RASTRTIM0_PPL_S 4
278 #define LCD_RASTRTIM0_MSBPPL_S 3
279 
280 //*****************************************************************************
281 //
282 // The following are defines for the bit fields in the LCD_O_RASTRTIM1
283 // register.
284 //
285 //*****************************************************************************
286 #define LCD_RASTRTIM1_VBP_M 0xFF000000 // Vertical Back Porch
287 #define LCD_RASTRTIM1_VFP_M 0x00FF0000 // Vertical Front Porch
288 #define LCD_RASTRTIM1_VSW_M 0x0000FC00 // Vertical Sync Width Pulse
289 #define LCD_RASTRTIM1_LPP_M 0x000003FF // Lines Per Panel
290 #define LCD_RASTRTIM1_VBP_S 24
291 #define LCD_RASTRTIM1_VFP_S 16
292 #define LCD_RASTRTIM1_VSW_S 10
293 #define LCD_RASTRTIM1_LPP_S 0
294 
295 //*****************************************************************************
296 //
297 // The following are defines for the bit fields in the LCD_O_RASTRTIM2
298 // register.
299 //
300 //*****************************************************************************
301 #define LCD_RASTRTIM2_HSW_M 0x78000000 // Bits 9:6 of the horizontal sync
302  // width field
303 #define LCD_RASTRTIM2_MSBLPP 0x04000000 // MSB of Lines Per Panel
304 #define LCD_RASTRTIM2_PXLCLKCTL 0x02000000 // Hsync/Vsync Pixel Clock Control
305  // On/Off
306 #define LCD_RASTRTIM2_PSYNCRF 0x01000000 // Program HSYNC/VSYNC Rise or Fall
307 #define LCD_RASTRTIM2_INVOE 0x00800000 // Invert Output Enable
308 #define LCD_RASTRTIM2_INVPXLCLK 0x00400000 // Invert Pixel Clock
309 #define LCD_RASTRTIM2_IHS 0x00200000 // Invert Hysync
310 #define LCD_RASTRTIM2_IVS 0x00100000 // Invert Vsync
311 #define LCD_RASTRTIM2_ACBI_M 0x000F0000 // AC Bias Pins Transitions per
312  // Interrupt
313 #define LCD_RASTRTIM2_ACBF_M 0x0000FF00 // AC Bias Pin Frequency
314 #define LCD_RASTRTIM2_MSBHBP_M 0x00000030 // Bits 9:8 of the horizontal back
315  // porch field
316 #define LCD_RASTRTIM2_MSBHFP_M 0x00000003 // Bits 9:8 of the horizontal front
317  // porch field
318 #define LCD_RASTRTIM2_HSW_S 27
319 #define LCD_RASTRTIM2_MSBLPP_S 26
320 #define LCD_RASTRTIM2_ACBI_S 16
321 #define LCD_RASTRTIM2_ACBF_S 8
322 #define LCD_RASTRTIM2_MSBHBP_S 4
323 #define LCD_RASTRTIM2_MSBHFP_S 0
324 
325 //*****************************************************************************
326 //
327 // The following are defines for the bit fields in the LCD_O_RASTRSUBP1
328 // register.
329 //
330 //*****************************************************************************
331 #define LCD_RASTRSUBP1_SPEN 0x80000000 // Sub Panel Enable
332 #define LCD_RASTRSUBP1_HOLS 0x20000000 // High or Low Signal
333 #define LCD_RASTRSUBP1_LPPT_M 0x03FF0000 // Line Per Panel Threshold
334 #define LCD_RASTRSUBP1_DPDLSB_M 0x0000FFFF // Default Pixel Data LSB[15:0]
335 #define LCD_RASTRSUBP1_LPPT_S 16
336 #define LCD_RASTRSUBP1_DPDLSB_S 0
337 
338 //*****************************************************************************
339 //
340 // The following are defines for the bit fields in the LCD_O_RASTRSUBP2
341 // register.
342 //
343 //*****************************************************************************
344 #define LCD_RASTRSUBP2_LPPTMSB 0x00000100 // Lines Per Panel Threshold Bit 10
345 #define LCD_RASTRSUBP2_DPDMSB_M 0x000000FF // Default Pixel Data MSB [23:16]
346 #define LCD_RASTRSUBP2_DPDMSB_S 0
347 
348 //*****************************************************************************
349 //
350 // The following are defines for the bit fields in the LCD_O_DMACTL register.
351 //
352 //*****************************************************************************
353 #define LCD_DMACTL_FIFORDY_M 0x00000700 // DMA FIFO threshold
354 #define LCD_DMACTL_FIFORDY_8 0x00000000 // 8 words
355 #define LCD_DMACTL_FIFORDY_16 0x00000100 // 16 words
356 #define LCD_DMACTL_FIFORDY_32 0x00000200 // 32 words
357 #define LCD_DMACTL_FIFORDY_64 0x00000300 // 64 words
358 #define LCD_DMACTL_FIFORDY_128 0x00000400 // 128 words
359 #define LCD_DMACTL_FIFORDY_256 0x00000500 // 256 words
360 #define LCD_DMACTL_FIFORDY_512 0x00000600 // 512 words
361 #define LCD_DMACTL_BURSTSZ_M 0x00000070 // Burst Size setting for DMA
362  // transfers (all DMA transfers are
363  // 32 bits wide):
364 #define LCD_DMACTL_BURSTSZ_4 0x00000020 // burst size of 4
365 #define LCD_DMACTL_BURSTSZ_8 0x00000030 // burst size of 8
366 #define LCD_DMACTL_BURSTSZ_16 0x00000040 // burst size of 16
367 #define LCD_DMACTL_BYTESWAP 0x00000008 // This bit controls the bytelane
368  // ordering of the data on the
369  // output of the DMA module
370 #define LCD_DMACTL_BIGDEND 0x00000002 // Big Endian Enable
371 #define LCD_DMACTL_FMODE 0x00000001 // Frame Mode
372 
373 //*****************************************************************************
374 //
375 // The following are defines for the bit fields in the LCD_O_DMABAFB0 register.
376 //
377 //*****************************************************************************
378 #define LCD_DMABAFB0_FB0BA_M 0xFFFFFFFC // Frame Buffer 0 Base Address
379  // pointer
380 #define LCD_DMABAFB0_FB0BA_S 2
381 
382 //*****************************************************************************
383 //
384 // The following are defines for the bit fields in the LCD_O_DMACAFB0 register.
385 //
386 //*****************************************************************************
387 #define LCD_DMACAFB0_FB0CA_M 0xFFFFFFFC // Frame Buffer 0 Ceiling Address
388  // pointer
389 #define LCD_DMACAFB0_FB0CA_S 2
390 
391 //*****************************************************************************
392 //
393 // The following are defines for the bit fields in the LCD_O_DMABAFB1 register.
394 //
395 //*****************************************************************************
396 #define LCD_DMABAFB1_FB1BA_M 0xFFFFFFFC // Frame Buffer 1 Base Address
397  // pointer
398 #define LCD_DMABAFB1_FB1BA_S 2
399 
400 //*****************************************************************************
401 //
402 // The following are defines for the bit fields in the LCD_O_DMACAFB1 register.
403 //
404 //*****************************************************************************
405 #define LCD_DMACAFB1_FB1CA_M 0xFFFFFFFC // Frame Buffer 1 Ceiling Address
406  // pointer
407 #define LCD_DMACAFB1_FB1CA_S 2
408 
409 //*****************************************************************************
410 //
411 // The following are defines for the bit fields in the LCD_O_SYSCFG register.
412 //
413 //*****************************************************************************
414 #define LCD_SYSCFG_STDBY_M 0x00000030 // Standby Mode
415 #define LCD_SYSCFG_STDBY_FORCE 0x00000000 // Force-standby mode: local
416  // initiator is unconditionally
417  // placed in standby state. Backup
418  // mode, for debug only
419 #define LCD_SYSCFG_STDBY_NONE 0x00000010 // No-standby mode: local initiator
420  // is unconditionally placed out of
421  // standby state. Backup mode, for
422  // debug only
423 #define LCD_SYSCFG_STDBY_SMART 0x00000020 // Smart-standby mode: local
424  // initiator standby status depends
425  // on local conditions, that is,
426  // the module's functional
427  // requirement from the initiator.
428  // IP module shall not generate
429  // (initiator-related) wakeup
430  // events
431 #define LCD_SYSCFG_IDLEMODE_M 0x0000000C // Idle Mode
432 #define LCD_SYSCFG_IDLEMODE_FORCE \
433  0x00000000 // Force-idle mode: local target's
434  // idle state follows
435  // (acknowledges) the system's idle
436  // requests unconditionally, that
437  // is, regardless of the IP
438  // module's internal requirements.
439  // Backup mode, for debug only
440 #define LCD_SYSCFG_IDLEMODE_NONE \
441  0x00000004 // No-idle mode: local target never
442  // enters idle state. Backup mode,
443  // for debug only
444 #define LCD_SYSCFG_IDLEMODE_SMART \
445  0x00000008 // Smart-idle mode: local target's
446  // idle state eventually follows
447  // (acknowledges) the system's idle
448  // requests, depending on the IP
449  // module's internal requirements.
450  // IP module shall not generate
451  // (IRQ- or DMA-requestrelated)
452  // wakeup events
453 
454 //*****************************************************************************
455 //
456 // The following are defines for the bit fields in the LCD_O_RISSET register.
457 //
458 //*****************************************************************************
459 #define LCD_RISSET_EOF1 0x00000200 // DMA End-of-Frame 1 Raw Interrupt
460  // Status and Set
461 #define LCD_RISSET_EOF0 0x00000100 // DMA End-of-Frame 0 Raw Interrupt
462  // Status and Set
463 #define LCD_RISSET_PALLOAD 0x00000040 // DMA Palette Loaded Raw Interrupt
464  // Status and Set
465 #define LCD_RISSET_FIFOU 0x00000020 // DMA FIFO Underflow Raw Interrupt
466  // Status and Set
467 #define LCD_RISSET_ACBS 0x00000008 // AC Bias Count Raw Interrupt
468  // Status and Set
469 #define LCD_RISSET_SYNCS 0x00000004 // Frame Synchronization Lost Raw
470  // Interrupt Status and Set
471 #define LCD_RISSET_RRASTRDONE 0x00000002 // Raster Mode Frame Done interrupt
472 #define LCD_RISSET_DONE 0x00000001 // Raster or LIDD Frame Done
473  // (shared, depends on whether
474  // Raster or LIDD mode enabled) Raw
475  // Interrupt Status and Set
476 
477 //*****************************************************************************
478 //
479 // The following are defines for the bit fields in the LCD_O_MISCLR register.
480 //
481 //*****************************************************************************
482 #define LCD_MISCLR_EOF1 0x00000200 // DMA End-of-Frame 1 Enabled
483  // Interrupt and Clear
484 #define LCD_MISCLR_EOF0 0x00000100 // DMA End-of-Frame 0 Raw Interrupt
485  // and Clear
486 #define LCD_MISCLR_PALLOAD 0x00000040 // DMA Palette Loaded Enabled
487  // Interrupt and Clear
488 #define LCD_MISCLR_FIFOU 0x00000020 // DMA FIFO Underflow Enabled
489  // Interrupt and Clear
490 #define LCD_MISCLR_ACBS 0x00000008 // AC Bias Count Enabled Interrupt
491  // and Clear
492 #define LCD_MISCLR_SYNCS 0x00000004 // Frame Synchronization Lost
493  // Enabled Interrupt and Clear
494 #define LCD_MISCLR_RRASTRDONE 0x00000002 // Raster Mode Frame Done interrupt
495 #define LCD_MISCLR_DONE 0x00000001 // Raster or LIDD Frame Done
496  // (shared, depends on whether
497  // Raster or LIDD mode enabled)
498  // Enabled Interrupt and Clear
499 
500 //*****************************************************************************
501 //
502 // The following are defines for the bit fields in the LCD_O_IM register.
503 //
504 //*****************************************************************************
505 #define LCD_IM_EOF1 0x00000200 // DMA End-of-Frame 1 Interrupt
506  // Enable Set
507 #define LCD_IM_EOF0 0x00000100 // DMA End-of-Frame 0 Interrupt
508  // Enable Set
509 #define LCD_IM_PALLOAD 0x00000040 // DMA Palette Loaded Interrupt
510  // Enable Set
511 #define LCD_IM_FIFOU 0x00000020 // DMA FIFO Underflow Interrupt
512  // Enable Set
513 #define LCD_IM_ACBS 0x00000008 // AC Bias Count Interrupt Enable
514  // Set
515 #define LCD_IM_SYNCS 0x00000004 // Frame Synchronization Lost
516  // Interrupt Enable Set
517 #define LCD_IM_RRASTRDONE 0x00000002 // Raster Mode Frame Done Interrupt
518  // Enable Set
519 #define LCD_IM_DONE 0x00000001 // Raster or LIDD Frame Done
520  // (shared, depends on whether
521  // Raster or LIDD mode enabled)
522  // Interrupt Enable Set
523 
524 //*****************************************************************************
525 //
526 // The following are defines for the bit fields in the LCD_O_IENC register.
527 //
528 //*****************************************************************************
529 #define LCD_IENC_EOF1 0x00000200 // DMA End-of-Frame 1 Interrupt
530  // Enable Clear
531 #define LCD_IENC_EOF0 0x00000100 // DMA End-of-Frame 0 Interrupt
532  // Enable Clear
533 #define LCD_IENC_PALLOAD 0x00000040 // DMA Palette Loaded Interrupt
534  // Enable Clear
535 #define LCD_IENC_FIFOU 0x00000020 // DMA FIFO Underflow Interrupt
536  // Enable Clear
537 #define LCD_IENC_ACBS 0x00000008 // AC Bias Count Interrupt Enable
538  // Clear
539 #define LCD_IENC_SYNCS 0x00000004 // Frame Synchronization Lost
540  // Interrupt Enable Clear
541 #define LCD_IENC_RRASTRDONE 0x00000002 // Raster Mode Frame Done Interrupt
542  // Enable Clear
543 #define LCD_IENC_DONE 0x00000001 // Raster or LIDD Frame Done
544  // (shared, depends on whether
545  // Raster or LIDD mode enabled)
546  // Interrupt Enable Clear
547 
548 //*****************************************************************************
549 //
550 // The following are defines for the bit fields in the LCD_O_CLKEN register.
551 //
552 //*****************************************************************************
553 #define LCD_CLKEN_DMA 0x00000004 // DMA Clock Enable
554 #define LCD_CLKEN_LIDD 0x00000002 // LIDD Submodule Clock Enable
555 #define LCD_CLKEN_CORE 0x00000001 // LCD Core Clock Enable
556 
557 //*****************************************************************************
558 //
559 // The following are defines for the bit fields in the LCD_O_CLKRESET register.
560 //
561 //*****************************************************************************
562 #define LCD_CLKRESET_MAIN 0x00000008 // Software Reset for the entire
563  // LCD module
564 #define LCD_CLKRESET_DMA 0x00000004 // Software Reset for the DMA
565  // submodule
566 #define LCD_CLKRESET_LIDD 0x00000002 // Software Reset for the LIDD
567  // submodule (character displays)
568 #define LCD_CLKRESET_CORE 0x00000001 // Software Reset for the Core,
569  // which encompasses the Raster
570  // Active Matrix and Passive Matrix
571  // logic
572 
573 #endif // __HW_LCD_H__
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