MSP432E4 DriverLib API Guide  1.11.00.03
udma.h
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1 //*****************************************************************************
2 //
3 // udma.h - Prototypes and macros for the uDMA controller.
4 //
5 // Copyright (c) 2007-2017 Texas Instruments Incorporated. All rights reserved.
6 // Software License Agreement
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36 //*****************************************************************************
37 
38 #ifndef __DRIVERLIB_UDMA_H__
39 #define __DRIVERLIB_UDMA_H__
40 
41 #include <stdint.h>
42 #include <stdbool.h>
43 
44 //*****************************************************************************
45 //
46 // If building with a C++ compiler, make all of the definitions in this header
47 // have a C binding.
48 //
49 //*****************************************************************************
50 #ifdef __cplusplus
51 extern "C"
52 {
53 #endif
54 
55 //*****************************************************************************
56 //
59 //
60 //*****************************************************************************
61 
62 //*****************************************************************************
63 //
64 // A structure that defines an entry in the channel control table. These
65 // fields are used by the uDMA controller and normally it is not necessary for
66 // software to directly read or write fields in the table.
67 //
68 //*****************************************************************************
69 typedef struct
70 {
71  //
72  // The ending source address of the data transfer.
73  //
74  volatile void *pvSrcEndAddr;
75 
76  //
77  // The ending destination address of the data transfer.
78  //
79  volatile void *pvDstEndAddr;
80 
81  //
82  // The channel control mode.
83  //
84  volatile uint32_t ui32Control;
85 
86  //
87  // An unused location.
88  //
89  volatile uint32_t ui32Spare;
90 }
92 
93 //*****************************************************************************
94 //
160 //
161 //*****************************************************************************
162 #define uDMATaskStructEntry(ui32TransferCount, \
163  ui32ItemSize, \
164  ui32SrcIncrement, \
165  pvSrcAddr, \
166  ui32DstIncrement, \
167  pvDstAddr, \
168  ui32ArbSize, \
169  ui32Mode) \
170  { \
171  (((ui32SrcIncrement) == UDMA_SRC_INC_NONE) ? (void *)(pvSrcAddr) : \
172  ((void *)(&((uint8_t *)(pvSrcAddr))[((ui32TransferCount) << \
173  ((ui32SrcIncrement) >> 26)) - 1]))), \
174  (((ui32DstIncrement) == UDMA_DST_INC_NONE) ? (void *)(pvDstAddr) :\
175  ((void *)(&((uint8_t *)(pvDstAddr))[((ui32TransferCount) << \
176  ((ui32DstIncrement) >> 30)) - 1]))), \
177  (ui32SrcIncrement) | (ui32DstIncrement) | (ui32ItemSize) | \
178  (ui32ArbSize) | \
179  (((ui32TransferCount) - 1) << 4) | \
180  ((((ui32Mode) == UDMA_MODE_MEM_SCATTER_GATHER) || \
181  ((ui32Mode) == UDMA_MODE_PER_SCATTER_GATHER)) ? \
182  (ui32Mode) | UDMA_MODE_ALT_SELECT : (ui32Mode)), 0 \
183  }
184 
185 //*****************************************************************************
186 //
187 // Close the Doxygen group.
189 //
190 //*****************************************************************************
191 
192 //*****************************************************************************
193 //
194 // Flags that can be passed to uDMAChannelAttributeEnable(),
195 // uDMAChannelAttributeDisable(), and returned from uDMAChannelAttributeGet().
196 //
197 //*****************************************************************************
198 #define UDMA_ATTR_USEBURST 0x00000001
199 #define UDMA_ATTR_ALTSELECT 0x00000002
200 #define UDMA_ATTR_HIGH_PRIORITY 0x00000004
201 #define UDMA_ATTR_REQMASK 0x00000008
202 #define UDMA_ATTR_ALL 0x0000000F
203 
204 //*****************************************************************************
205 //
206 // DMA control modes that can be passed to uDMAModeSet() and returned
207 // uDMAModeGet().
208 //
209 //*****************************************************************************
210 #define UDMA_MODE_STOP 0x00000000
211 #define UDMA_MODE_BASIC 0x00000001
212 #define UDMA_MODE_AUTO 0x00000002
213 #define UDMA_MODE_PINGPONG 0x00000003
214 #define UDMA_MODE_MEM_SCATTER_GATHER \
215  0x00000004
216 #define UDMA_MODE_PER_SCATTER_GATHER \
217  0x00000006
218 #define UDMA_MODE_ALT_SELECT 0x00000001
219 
220 //*****************************************************************************
221 //
222 // Channel configuration values that can be passed to uDMAControlSet().
223 //
224 //*****************************************************************************
225 #define UDMA_DST_INC_8 0x00000000
226 #define UDMA_DST_INC_16 0x40000000
227 #define UDMA_DST_INC_32 0x80000000
228 #define UDMA_DST_INC_NONE 0xc0000000
229 #define UDMA_SRC_INC_8 0x00000000
230 #define UDMA_SRC_INC_16 0x04000000
231 #define UDMA_SRC_INC_32 0x08000000
232 #define UDMA_SRC_INC_NONE 0x0c000000
233 #define UDMA_SIZE_8 0x00000000
234 #define UDMA_SIZE_16 0x11000000
235 #define UDMA_SIZE_32 0x22000000
236 #define UDMA_DST_PROT_PRIV 0x00200000
237 #define UDMA_SRC_PROT_PRIV 0x00040000
238 #define UDMA_ARB_1 0x00000000
239 #define UDMA_ARB_2 0x00004000
240 #define UDMA_ARB_4 0x00008000
241 #define UDMA_ARB_8 0x0000c000
242 #define UDMA_ARB_16 0x00010000
243 #define UDMA_ARB_32 0x00014000
244 #define UDMA_ARB_64 0x00018000
245 #define UDMA_ARB_128 0x0001c000
246 #define UDMA_ARB_256 0x00020000
247 #define UDMA_ARB_512 0x00024000
248 #define UDMA_ARB_1024 0x00028000
249 #define UDMA_NEXT_USEBURST 0x00000008
250 
251 //*****************************************************************************
252 //
253 // Flags to be OR'd with the channel ID to indicate if the primary or alternate
254 // control structure should be used.
255 //
256 //*****************************************************************************
257 #define UDMA_PRI_SELECT 0x00000000
258 #define UDMA_ALT_SELECT 0x00000020
259 
260 //*****************************************************************************
261 //
262 // Values that can be passed to uDMAChannelAssign() to select peripheral
263 // mapping for each channel.
264 //
265 //*****************************************************************************
266 //
267 // Channel 0
268 //
269 #define UDMA_CH0_RESERVED0 0x00000000
270 #define UDMA_CH0_UART2RX 0x00010000
271 #define UDMA_CH0_RESERVED2 0x00020000
272 #define UDMA_CH0_TIMER4A 0x00030000
273 #define UDMA_CH0_RESERVED4 0x00040000
274 #define UDMA_CH0_RESERVED5 0x00050000
275 #define UDMA_CH0_I2C0RX 0x00060000
276 #define UDMA_CH0_RESERVED7 0x00070000
277 #define UDMA_CH0_RESERVED8 0x00080000
278 
279 //
280 // Channel 1
281 //
282 #define UDMA_CH1_RESERVED0 0x00000001
283 #define UDMA_CH1_UART2TX 0x00010001
284 #define UDMA_CH1_RESERVED2 0x00020001
285 #define UDMA_CH1_TIMER4B 0x00030001
286 #define UDMA_CH1_RESERVED4 0x00040001
287 #define UDMA_CH1_RESERVED5 0x00050001
288 #define UDMA_CH1_I2C0TX 0x00060001
289 #define UDMA_CH1_RESERVED7 0x00070001
290 #define UDMA_CH1_RESERVED8 0x00080001
291 
292 //
293 // Channel 2
294 //
295 #define UDMA_CH2_RESERVED0 0x00000002
296 #define UDMA_CH2_TIMER3A 0x00010002
297 #define UDMA_CH2_RESERVED2 0x00020002
298 #define UDMA_CH2_RESERVED3 0x00030002
299 #define UDMA_CH2_RESERVED4 0x00040002
300 #define UDMA_CH2_RESERVED5 0x00050002
301 #define UDMA_CH2_I2C1RX 0x00060002
302 #define UDMA_CH2_RESERVED7 0x00070002
303 #define UDMA_CH2_RESERVED8 0x00080002
304 
305 //
306 // Channel 3
307 //
308 #define UDMA_CH3_RESERVED0 0x00000003
309 #define UDMA_CH3_TIMER3B 0x00010003
310 #define UDMA_CH3_RESERVED2 0x00020003
311 #define UDMA_CH3_RESERVED3 0x00030003
312 #define UDMA_CH3_RESERVED4 0x00040003
313 #define UDMA_CH3_RESERVED5 0x00050003
314 #define UDMA_CH3_I2C1TX 0x00060003
315 #define UDMA_CH3_RESERVED7 0x00070003
316 #define UDMA_CH3_RESERVED8 0x00080003
317 
318 //
319 // Channel 4
320 //
321 #define UDMA_CH4_RESERVED0 0x00000004
322 #define UDMA_CH4_TIMER2A 0x00010004
323 #define UDMA_CH4_RESERVED2 0x00020004
324 #define UDMA_CH4_GPIOA 0x00030004
325 #define UDMA_CH4_RESERVED4 0x00040004
326 #define UDMA_CH4_SHAMD50CIN 0x00050004
327 #define UDMA_CH4_I2C2RX 0x00060004
328 #define UDMA_CH4_RESERVED7 0x00070004
329 #define UDMA_CH4_RESERVED8 0x00080004
330 
331 //
332 // Channel 5
333 //
334 #define UDMA_CH5_RESERVED0 0x00000005
335 #define UDMA_CH5_TIMER2B 0x00010005
336 #define UDMA_CH5_RESERVED2 0x00020005
337 #define UDMA_CH5_GPIOB 0x00030005
338 #define UDMA_CH5_RESERVED4 0x00040005
339 #define UDMA_CH5_SHAMD50DIN 0x00050005
340 #define UDMA_CH5_I2C2TX 0x00060005
341 #define UDMA_CH5_RESERVED7 0x00070005
342 #define UDMA_CH5_RESERVED8 0x00080005
343 
344 //
345 // Channel 6
346 //
347 #define UDMA_CH6_RESERVED0 0x00000006
348 #define UDMA_CH6_TIMER2A 0x00010006
349 #define UDMA_CH6_UART5RX 0x00020006
350 #define UDMA_CH6_GPIOC 0x00030006
351 #define UDMA_CH6_I2C0RX 0x00040006
352 #define UDMA_CH6_SHAMD50COUT 0x00050006
353 #define UDMA_CH6_RESERVED6 0x00060006
354 #define UDMA_CH6_RESERVED7 0x00070006
355 #define UDMA_CH6_RESERVED8 0x00080006
356 
357 //
358 // Channel 7
359 //
360 #define UDMA_CH7_RESERVED0 0x00000007
361 #define UDMA_CH7_TIMER2B 0x00010007
362 #define UDMA_CH7_UART5TX 0x00020007
363 #define UDMA_CH7_GPIOD 0x00030007
364 #define UDMA_CH7_I2C0TX 0x00040007
365 #define UDMA_CH7_RESERVED5 0x00050007
366 #define UDMA_CH7_RESERVED6 0x00060007
367 #define UDMA_CH7_RESERVED7 0x00070007
368 #define UDMA_CH7_RESERVED8 0x00080007
369 
370 //
371 // Channel 8
372 //
373 #define UDMA_CH8_UART0RX 0x00000008
374 #define UDMA_CH8_UART1RX 0x00010008
375 #define UDMA_CH8_RESERVED2 0x00020008
376 #define UDMA_CH8_TIMER5A 0x00030008
377 #define UDMA_CH8_I2C1RX 0x00040008
378 #define UDMA_CH8_RESERVED5 0x00050008
379 #define UDMA_CH8_RESERVED6 0x00060008
380 #define UDMA_CH8_RESERVED7 0x00070008
381 #define UDMA_CH8_RESERVED8 0x00080008
382 
383 //
384 // Channel 9
385 //
386 #define UDMA_CH9_UART0TX 0x00000009
387 #define UDMA_CH9_UART1TX 0x00010009
388 #define UDMA_CH9_RESERVED2 0x00020009
389 #define UDMA_CH9_TIMER5B 0x00030009
390 #define UDMA_CH9_I2C1TX 0x00040009
391 #define UDMA_CH9_RESERVED5 0x00050009
392 #define UDMA_CH9_RESERVED6 0x00060009
393 #define UDMA_CH9_RESERVED7 0x00070009
394 #define UDMA_CH9_RESERVED8 0x00080009
395 
396 //
397 // Channel 10
398 //
399 #define UDMA_CH10_SSI0RX 0x0000000A
400 #define UDMA_CH10_SSI1RX 0x0001000A
401 #define UDMA_CH10_UART6RX 0x0002000A
402 #define UDMA_CH10_RESERVED3 0x0003000A
403 #define UDMA_CH10_I2C2RX 0x0004000A
404 #define UDMA_CH10_RESERVED5 0x0005000A
405 #define UDMA_CH10_RESERVED6 0x0006000A
406 #define UDMA_CH10_TIMER6A 0x0007000A
407 #define UDMA_CH10_RESERVED8 0x0008000A
408 
409 //
410 // Channel 11
411 //
412 #define UDMA_CH11_SSI0TX 0x0000000B
413 #define UDMA_CH11_SSI1TX 0x0001000B
414 #define UDMA_CH11_UART6TX 0x0002000B
415 #define UDMA_CH11_RESERVED3 0x0003000B
416 #define UDMA_CH11_I2C2TX 0x0004000B
417 #define UDMA_CH11_RESERVED5 0x0005000B
418 #define UDMA_CH11_RESERVED6 0x0006000B
419 #define UDMA_CH11_TIMER6B 0x0007000B
420 #define UDMA_CH11_RESERVED8 0x0008000B
421 
422 //
423 // Channel 12
424 //
425 #define UDMA_CH12_RESERVED0 0x0000000C
426 #define UDMA_CH12_UART2RX 0x0001000C
427 #define UDMA_CH12_SSI2RX 0x0002000C
428 #define UDMA_CH12_RESERVED3 0x0003000C
429 #define UDMA_CH12_GPIOK 0x0004000C
430 #define UDMA_CH12_AES0CIN 0x0005000C
431 #define UDMA_CH12_RESERVED6 0x0006000C
432 #define UDMA_CH12_TIMER7A 0x0007000C
433 #define UDMA_CH12_RESERVED8 0x0008000C
434 
435 //
436 // Channel 13
437 //
438 #define UDMA_CH13_RESERVED0 0x0000000D
439 #define UDMA_CH13_UART2TX 0x0001000D
440 #define UDMA_CH13_SSI2TX 0x0002000D
441 #define UDMA_CH13_RESERVED3 0x0003000D
442 #define UDMA_CH13_GPIOL 0x0004000D
443 #define UDMA_CH13_AES0COUT 0x0005000D
444 #define UDMA_CH13_RESERVED6 0x0006000D
445 #define UDMA_CH13_TIMER7B 0x0007000D
446 #define UDMA_CH13_RESERVED8 0x0008000D
447 
448 //
449 // Channel 14
450 //
451 #define UDMA_CH14_ADC0_0 0x0000000E
452 #define UDMA_CH14_TIMER2A 0x0001000E
453 #define UDMA_CH14_SSI3RX 0x0002000E
454 #define UDMA_CH14_GPIOE 0x0003000E
455 #define UDMA_CH14_GPIOM 0x0004000E
456 #define UDMA_CH14_AES0DIN 0x0005000E
457 #define UDMA_CH14_RESERVED6 0x0006000E
458 #define UDMA_CH14_RESERVED7 0x0007000E
459 #define UDMA_CH14_RESERVED8 0x0008000E
460 
461 //
462 // Channel 15
463 //
464 #define UDMA_CH15_ADC0_1 0x0000000F
465 #define UDMA_CH15_TIMER2B 0x0001000F
466 #define UDMA_CH15_SSI3TX 0x0002000F
467 #define UDMA_CH15_GPIOF 0x0003000F
468 #define UDMA_CH15_GPION 0x0004000F
469 #define UDMA_CH15_AES0DOUT 0x0005000F
470 #define UDMA_CH15_RESERVED6 0x0006000F
471 #define UDMA_CH15_RESERVED7 0x0007000F
472 #define UDMA_CH15_RESERVED8 0x0008000F
473 
474 //
475 // Channel 16
476 //
477 #define UDMA_CH16_ADC0_2 0x00000010
478 #define UDMA_CH16_RESERVED1 0x00010010
479 #define UDMA_CH16_UART3RX 0x00020010
480 #define UDMA_CH16_RESERVED3 0x00030010
481 #define UDMA_CH16_GPIOP 0x00040010
482 #define UDMA_CH16_RESERVED5 0x00050010
483 #define UDMA_CH16_RESERVED6 0x00060010
484 #define UDMA_CH16_RESERVED7 0x00070010
485 #define UDMA_CH16_RESERVED8 0x00080010
486 
487 //
488 // Channel 17
489 //
490 #define UDMA_CH17_ADC0_3 0x00000011
491 #define UDMA_CH17_RESERVED1 0x00010011
492 #define UDMA_CH17_UART3TX 0x00020011
493 #define UDMA_CH17_RESERVED3 0x00030011
494 #define UDMA_CH17_RESERVED4 0x00040011
495 #define UDMA_CH17_RESERVED5 0x00050011
496 #define UDMA_CH17_RESERVED6 0x00060011
497 #define UDMA_CH17_RESERVED7 0x00070011
498 #define UDMA_CH17_RESERVED8 0x00080011
499 
500 //
501 // Channel 18
502 //
503 #define UDMA_CH18_TIMER0A 0x00000012
504 #define UDMA_CH18_TIMER1A 0x00010012
505 #define UDMA_CH18_UART4RX 0x00020012
506 #define UDMA_CH18_GPIOB 0x00030012
507 #define UDMA_CH18_I2C3RX 0x00040012
508 #define UDMA_CH18_RESERVED5 0x00050012
509 #define UDMA_CH18_RESERVED6 0x00060012
510 #define UDMA_CH18_RESERVED7 0x00070012
511 #define UDMA_CH18_RESERVED8 0x00080012
512 
513 //
514 // Channel 19
515 //
516 #define UDMA_CH19_TIMER0B 0x00000013
517 #define UDMA_CH19_TIMER1B 0x00010013
518 #define UDMA_CH19_UART4TX 0x00020013
519 #define UDMA_CH19_GPIOG 0x00030013
520 #define UDMA_CH19_I2C3TX 0x00040013
521 #define UDMA_CH19_RESERVED5 0x00050013
522 #define UDMA_CH19_RESERVED6 0x00060013
523 #define UDMA_CH19_RESERVED7 0x00070013
524 #define UDMA_CH19_RESERVED8 0x00080013
525 
526 //
527 // Channel 20
528 //
529 #define UDMA_CH20_TIMER1A 0x00000014
530 #define UDMA_CH20_EPI0RX 0x00010014
531 #define UDMA_CH20_UART7RX 0x00020014
532 #define UDMA_CH20_GPIOH 0x00030014
533 #define UDMA_CH20_I2C4RX 0x00040014
534 #define UDMA_CH20_DES0CIN 0x00050014
535 #define UDMA_CH20_RESERVED6 0x00060014
536 #define UDMA_CH20_RESERVED7 0x00070014
537 #define UDMA_CH20_RESERVED8 0x00080014
538 
539 //
540 // Channel 21
541 //
542 #define UDMA_CH21_TIMER1B 0x00000015
543 #define UDMA_CH21_EPI0TX 0x00010015
544 #define UDMA_CH21_UART7TX 0x00020015
545 #define UDMA_CH21_GPIOJ 0x00030015
546 #define UDMA_CH21_I2C4TX 0x00040015
547 #define UDMA_CH21_DES0DIN 0x00050015
548 #define UDMA_CH21_RESERVED6 0x00060015
549 #define UDMA_CH21_RESERVED7 0x00070015
550 #define UDMA_CH21_RESERVED8 0x00080015
551 
552 //
553 // Channel 22
554 //
555 #define UDMA_CH22_UART1RX 0x00000016
556 #define UDMA_CH22_RESERVED1 0x00010016
557 #define UDMA_CH22_RESERVED2 0x00020016
558 #define UDMA_CH22_RESERVED3 0x00030016
559 #define UDMA_CH22_I2C5RX 0x00040016
560 #define UDMA_CH22_DES0DOUT 0x00050016
561 #define UDMA_CH22_RESERVED6 0x00060016
562 #define UDMA_CH22_RESERVED7 0x00070016
563 #define UDMA_CH22_I2C8RX 0x00080016
564 
565 //
566 // Channel 23
567 //
568 #define UDMA_CH23_UART1TX 0x00000017
569 #define UDMA_CH23_RESERVED1 0x00010017
570 #define UDMA_CH23_RESERVED2 0x00020017
571 #define UDMA_CH23_RESERVED3 0x00030017
572 #define UDMA_CH23_I2C5TX 0x00040017
573 #define UDMA_CH23_RESERVED5 0x00050017
574 #define UDMA_CH23_RESERVED6 0x00060017
575 #define UDMA_CH23_RESERVED7 0x00070017
576 #define UDMA_CH23_I2C8TX 0x00080017
577 
578 //
579 // Channel 24
580 //
581 #define UDMA_CH24_SSI1RX 0x00000018
582 #define UDMA_CH24_ADC1_0 0x00010018
583 #define UDMA_CH24_RESERVED2 0x00020018
584 #define UDMA_CH24_RESERVED3 0x00030018
585 #define UDMA_CH24_GPIOQ 0x00040018
586 #define UDMA_CH24_RESERVED5 0x00050018
587 #define UDMA_CH24_RESERVED6 0x00060018
588 #define UDMA_CH24_RESERVED7 0x00070018
589 #define UDMA_CH24_I2C9RX 0x00080018
590 
591 //
592 // Channel 25
593 //
594 #define UDMA_CH25_SSI1TX 0x00000019
595 #define UDMA_CH25_ADC1_1 0x00010019
596 #define UDMA_CH25_RESERVED2 0x00020019
597 #define UDMA_CH25_RESERVED3 0x00030019
598 #define UDMA_CH25_GPIOR 0x00040019
599 #define UDMA_CH25_RESERVED5 0x00050019
600 #define UDMA_CH25_RESERVED6 0x00060019
601 #define UDMA_CH25_RESERVED7 0x00070019
602 #define UDMA_CH25_I2C9TX 0x00080019
603 
604 //
605 // Channel 26
606 //
607 #define UDMA_CH26_RESERVED0 0x0000001A
608 #define UDMA_CH26_ADC1_2 0x0001001A
609 #define UDMA_CH26_RESERVED2 0x0002001A
610 #define UDMA_CH26_RESERVED3 0x0003001A
611 #define UDMA_CH26_GPIOS 0x0004001A
612 #define UDMA_CH26_RESERVED5 0x0005001A
613 #define UDMA_CH26_RESERVED6 0x0006001A
614 #define UDMA_CH26_RESERVED7 0x0007001A
615 #define UDMA_CH26_I2C6RX 0x0008001A
616 
617 //
618 // Channel 27
619 //
620 #define UDMA_CH27_RESERVED0 0x0000001B
621 #define UDMA_CH27_ADC1_3 0x0001001B
622 #define UDMA_CH27_RESERVED2 0x0002001B
623 #define UDMA_CH27_RESERVED3 0x0003001B
624 #define UDMA_CH27_RESERVED4 0x0004001B
625 #define UDMA_CH27_RESERVED5 0x0005001B
626 #define UDMA_CH27_GPIOT 0x0006001B
627 #define UDMA_CH27_RESERVED7 0x0007001B
628 #define UDMA_CH27_I2C6TX 0x0008001B
629 
630 //
631 // Channel 28
632 //
633 #define UDMA_CH28_RESERVED0 0x0000001C
634 #define UDMA_CH28_RESERVED1 0x0001001C
635 #define UDMA_CH28_RESERVED2 0x0002001C
636 #define UDMA_CH28_RESERVED3 0x0003001C
637 #define UDMA_CH28_RESERVED4 0x0004001C
638 #define UDMA_CH28_RESERVED5 0x0005001C
639 #define UDMA_CH28_RESERVED6 0x0006001C
640 #define UDMA_CH28_RESERVED7 0x0007001C
641 #define UDMA_CH28_I2C7RX 0x0008001C
642 
643 //
644 // Channel 29
645 //
646 #define UDMA_CH29_RESERVED0 0x0000001D
647 #define UDMA_CH29_RESERVED1 0x0001001D
648 #define UDMA_CH29_RESERVED2 0x0002001D
649 #define UDMA_CH29_RESERVED3 0x0003001D
650 #define UDMA_CH29_RESERVED4 0x0004001D
651 #define UDMA_CH29_RESERVED5 0x0005001D
652 #define UDMA_CH29_RESERVED6 0x0006001D
653 #define UDMA_CH29_RESERVED7 0x0007001D
654 #define UDMA_CH29_I2C7TX 0x0008001D
655 
656 //
657 // Channel 30
658 //
659 #define UDMA_CH30_SW 0x0000001E
660 #define UDMA_CH30_RESERVED1 0x0001001E
661 #define UDMA_CH30_RESERVED2 0x0002001E
662 #define UDMA_CH30_RESERVED3 0x0003001E
663 #define UDMA_CH30_RESERVED4 0x0004001E
664 #define UDMA_CH30_RESERVED5 0x0005001E
665 #define UDMA_CH30_RESERVED6 0x0006001E
666 #define UDMA_CH30_EPI0RX 0x0007001E
667 #define UDMA_CH30_1WIRE0 0x0008001E
668 
669 //
670 // Channel 31
671 //
672 #define UDMA_CH31_RESERVED0 0x0000001F
673 #define UDMA_CH31_RESERVED1 0x0001001F
674 #define UDMA_CH31_RESERVED2 0x0002001F
675 #define UDMA_CH31_RESERVED3 0x0003001F
676 #define UDMA_CH31_RESERVED4 0x0004001F
677 #define UDMA_CH31_RESERVED5 0x0005001F
678 #define UDMA_CH31_RESERVED6 0x0006001F
679 #define UDMA_CH31_EPI0RX 0x0007001F
680 #define UDMA_CH31_RESERVED8 0x0008001F
681 
682 //*****************************************************************************
683 //
684 // API Function prototypes
685 //
686 //*****************************************************************************
687 extern void uDMAInit(void);
688 extern void uDMAEnable(void);
689 extern void uDMADisable(void);
690 extern uint32_t uDMAErrorStatusGet(void);
691 extern void uDMAErrorStatusClear(void);
692 extern void uDMAChannelEnable(uint32_t ui32ChannelNum);
693 extern void uDMAChannelDisable(uint32_t ui32ChannelNum);
694 extern bool uDMAChannelIsEnabled(uint32_t ui32ChannelNum);
695 extern void uDMAControlBaseSet(void *pControlTable);
696 extern void *uDMAControlBaseGet(void);
697 extern void *uDMAControlAlternateBaseGet(void);
698 extern void uDMAChannelRequest(uint32_t ui32ChannelNum);
699 extern void uDMAChannelAttributeEnable(uint32_t ui32ChannelNum,
700  uint32_t ui32Attr);
701 extern void uDMAChannelAttributeDisable(uint32_t ui32ChannelNum,
702  uint32_t ui32Attr);
703 extern uint32_t uDMAChannelAttributeGet(uint32_t ui32ChannelNum);
704 extern void uDMAChannelControlSet(uint32_t ui32ChannelStructIndex,
705  uint32_t ui32Control);
706 extern void uDMAChannelTransferSet(uint32_t ui32ChannelStructIndex,
707  uint32_t ui32Mode, void *pvSrcAddr,
708  void *pvDstAddr, uint32_t ui32TransferSize);
709 extern void uDMAChannelScatterGatherSet(uint32_t ui32ChannelNum,
710  uint32_t ui32TaskCount,
711  void *pvTaskList,
712  uint32_t ui32IsPeriphSG);
713 extern uint32_t uDMAChannelSizeGet(uint32_t ui32ChannelStructIndex);
714 extern uint32_t uDMAChannelModeGet(uint32_t ui32ChannelStructIndex);
715 extern void uDMAIntRegister(uint32_t ui32IntChannel, void (*pfnHandler)(void));
716 extern void uDMAIntUnregister(uint32_t ui32IntChannel);
717 extern void uDMAChannelAssign(uint32_t ui32Mapping);
718 
719 //*****************************************************************************
720 //
721 // Mark the end of the C bindings section for C++ compilers.
722 //
723 //*****************************************************************************
724 #ifdef __cplusplus
725 }
726 #endif
727 
728 #endif // __DRIVERLIB_UDMA_H__
uint32_t uDMAChannelModeGet(uint32_t ui32ChannelStructIndex)
Definition: udma.c:1037
volatile void * pvSrcEndAddr
Definition: udma.h:74
void uDMAEnable(void)
Definition: udma.c:86
void uDMAChannelAssign(uint32_t ui32Mapping)
Definition: udma.c:1180
uint32_t uDMAChannelSizeGet(uint32_t ui32ChannelStructIndex)
Definition: udma.c:967
void uDMAIntUnregister(uint32_t ui32IntChannel)
Definition: udma.c:1147
void uDMAChannelTransferSet(uint32_t ui32ChannelStructIndex, uint32_t ui32Mode, void *pvSrcAddr, void *pvDstAddr, uint32_t ui32TransferSize)
Definition: udma.c:729
void uDMAChannelAttributeEnable(uint32_t ui32ChannelNum, uint32_t ui32Attr)
Definition: udma.c:375
void uDMAChannelControlSet(uint32_t ui32ChannelStructIndex, uint32_t ui32Control)
Definition: udma.c:622
bool uDMAChannelIsEnabled(uint32_t ui32ChannelNum)
Definition: udma.c:225
volatile uint32_t ui32Spare
Definition: udma.h:89
uint32_t uDMAChannelAttributeGet(uint32_t ui32ChannelNum)
Definition: udma.c:519
void * uDMAControlAlternateBaseGet(void)
Definition: udma.c:309
void uDMAChannelRequest(uint32_t ui32ChannelNum)
Definition: udma.c:339
void uDMAChannelScatterGatherSet(uint32_t ui32ChannelNum, uint32_t ui32TaskCount, void *pvTaskList, uint32_t ui32IsPeriphSG)
Definition: udma.c:880
void uDMAChannelAttributeDisable(uint32_t ui32ChannelNum, uint32_t ui32Attr)
Definition: udma.c:448
volatile uint32_t ui32Control
Definition: udma.h:84
volatile void * pvDstEndAddr
Definition: udma.h:79
void uDMADisable(void)
Definition: udma.c:105
void uDMAChannelDisable(uint32_t ui32ChannelNum)
Definition: udma.c:198
Definition: udma.h:69
void * uDMAControlBaseGet(void)
Definition: udma.c:288
void uDMAIntRegister(uint32_t ui32IntChannel, void(*pfnHandler)(void))
Definition: udma.c:1111
uint32_t uDMAErrorStatusGet(void)
Definition: udma.c:125
void uDMAInit(void)
Definition: udma.c:67
void uDMAErrorStatusClear(void)
Definition: udma.c:145
void uDMAControlBaseSet(void *pControlTable)
Definition: udma.c:261
void uDMAChannelEnable(uint32_t ui32ChannelNum)
Definition: udma.c:171
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