48 #ifndef ti_drivers_uart_UARTMSP432E4__include 49 #define ti_drivers_uart_UARTMSP432E4__include 55 #include <ti/devices/msp432e4/inc/msp432.h> 57 #include <ti/devices/msp432e4/driverlib/gpio.h> 58 #include <ti/devices/msp432e4/driverlib/pin_map.h> 60 #include <ti/drivers/dpl/ClockP.h> 61 #include <ti/drivers/dpl/HwiP.h> 62 #include <ti/drivers/dpl/SemaphoreP.h> 78 #define UARTMSP432E4_PIN_UNASSIGNED 0xFFFFFFFF 83 #define UARTMSP432E4_FLOWCTRL_NONE 0 88 #define UARTMSP432E4_FLOWCTRL_HARDWARE 1 93 #define UARTMSP432E4_PA0_U0RX GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTA, 0, GPIO_PA0_U0RX) 98 #define UARTMSP432E4_PA1_U0TX GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTA, 1, GPIO_PA1_U0TX) 103 #define UARTMSP432E4_PH1_U0CTS GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTH, 1, GPIO_PH1_U0CTS) 108 #define UARTMSP432E4_PM4_U0CTS GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTM, 4, GPIO_PM4_U0CTS) 113 #define UARTMSP432E4_PB4_U0CTS GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTB, 4, GPIO_PB4_U0CTS) 118 #define UARTMSP432E4_PE6_U0CTS GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTE, 6, GPIO_PE6_U0CTS) 123 #define UARTMSP432E4_PG4_U0CTS GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTG, 4, GPIO_PG4_U0CTS) 128 #define UARTMSP432E4_PH0_U0RTS GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTH, 0, GPIO_PH0_U0RTS) 133 #define UARTMSP432E4_PB5_U0RTS GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTB, 5, GPIO_PB5_U0RTS) 138 #define UARTMSP432E4_PE7_U0RTS GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTE, 7, GPIO_PE7_U0RTS) 143 #define UARTMSP432E4_PG5_U0RTS GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTG, 5, GPIO_PG5_U0RTS) 149 #define UARTMSP432E4_PB0_U1RX GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTB, 0, GPIO_PB0_U1RX) 154 #define UARTMSP432E4_PQ4_U1RX GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTQ, 4, GPIO_PQ4_U1RX) 159 #define UARTMSP432E4_PR5_U1RX GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTR, 5, GPIO_PR5_U1RX) 164 #define UARTMSP432E4_PB1_U1TX GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTB, 1, GPIO_PB1_U1TX) 169 #define UARTMSP432E4_PQ5_U1TX GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTQ, 5, GPIO_PQ5_U1TX) 174 #define UARTMSP432E4_PR6_U1TX GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTR, 6, GPIO_PR6_U1TX) 179 #define UARTMSP432E4_PP3_U1CTS GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTP, 3, GPIO_PP3_U1CTS) 184 #define UARTMSP432E4_PN1_U1CTS GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTN, 1, GPIO_PN1_U1CTS) 189 #define UARTMSP432E4_PE0_U1RTS GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTE, 0, GPIO_PE0_U1RTS) 194 #define UARTMSP432E4_PN0_U1RTS GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTN, 0, GPIO_PN0_U1RTS) 199 #define UARTMSP432E4_PN7_U1RTS GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTN, 7, GPIO_PN7_U1RTS) 205 #define UARTMSP432E4_PA6_U2RX GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTA, 6, GPIO_PA6_U2RX) 210 #define UARTMSP432E4_PD4_U2RX GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTD, 4, GPIO_PD4_U2RX) 215 #define UARTMSP432E4_PA7_U2TX GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTA, 7, GPIO_PA7_U2TX) 220 #define UARTMSP432E4_PD5_U2TX GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTD, 5, GPIO_PD5_U2TX) 225 #define UARTMSP432E4_PN3_U2CTS GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTN, 3, GPIO_PN3_U2CTS) 230 #define UARTMSP432E4_PD7_U2CTS GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTD, 7, GPIO_PD7_U2CTS) 235 #define UARTMSP432E4_PJ3_U2CTS GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTJ, 3, GPIO_PJ3_U2CTS) 240 #define UARTMSP432E4_PN2_U2RTS GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTN, 2, GPIO_PN2_U2RTS) 245 #define UARTMSP432E4_PD6_U2RTS GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTD, 6, GPIO_PD6_U2RTS) 250 #define UARTMSP432E4_PJ2_U2RTS GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTJ, 2, GPIO_PJ2_U2RTS) 256 #define UARTMSP432E4_PA4_U3RX GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTA, 4, GPIO_PA4_U3RX) 261 #define UARTMSP432E4_PJ0_U3RX GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTJ, 0, GPIO_PJ0_U3RX) 266 #define UARTMSP432E4_PA5_U3TX GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTA, 5, GPIO_PA5_U3TX) 271 #define UARTMSP432E4_PJ1_U3TX GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTJ, 1, GPIO_PJ1_U3TX) 276 #define UARTMSP432E4_PP5_U3CTS GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTP, 5, GPIO_PP5_U3CTS) 281 #define UARTMSP432E4_PN5_U3CTS GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTN, 5, GPIO_PN5_U3CTS) 286 #define UARTMSP432E4_PJ5_U3CTS GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTJ, 5, GPIO_PJ5_U3CTS) 291 #define UARTMSP432E4_PP4_U3RTS GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTP, 4, GPIO_PP4_U3RTS) 296 #define UARTMSP432E4_PN4_U3RTS GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTN, 4, GPIO_PN4_U3RTS) 301 #define UARTMSP432E4_PJ4_U3RTS GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTJ, 4, GPIO_PJ4_U3RTS) 307 #define UARTMSP432E4_PA2_U4RX GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTA, 2, GPIO_PA2_U4RX) 312 #define UARTMSP432E4_PK0_U4RX GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTK, 0, GPIO_PK0_U4RX) 317 #define UARTMSP432E4_PR1_U4RX GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTR, 1, GPIO_PR1_U4RX) 322 #define UARTMSP432E4_PA3_U4TX GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTA, 3, GPIO_PA3_U4TX) 327 #define UARTMSP432E4_PK1_U4TX GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTK, 1, GPIO_PK1_U4TX) 332 #define UARTMSP432E4_PR0_U4TX GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTR, 0, GPIO_PR0_U4TX) 337 #define UARTMSP432E4_PK3_U4CTS GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTK, 3, GPIO_PK3_U4CTS) 342 #define UARTMSP432E4_PJ7_U4CTS GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTJ, 7, GPIO_PJ7_U4CTS) 347 #define UARTMSP432E4_PN7_U4CTS GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTN, 7, GPIO_PN7_U4CTS) 352 #define UARTMSP432E4_PK2_U4RTS GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTK, 2, GPIO_PK2_U4RTS) 357 #define UARTMSP432E4_PJ6_U4RTS GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTJ, 6, GPIO_PJ6_U4RTS) 362 #define UARTMSP432E4_PN6_U4RTS GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTN, 6, GPIO_PN6_U4RTS) 368 #define UARTMSP432E4_PC6_U5RX GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTC, 6, GPIO_PC6_U5RX) 373 #define UARTMSP432E4_PH6_U5RX GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTH, 6, GPIO_PH6_U5RX) 378 #define UARTMSP432E4_PC7_U5TX GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTC, 7, GPIO_PC7_U5TX) 383 #define UARTMSP432E4_PH7_U5TX GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTH, 7, GPIO_PH7_U5TX) 389 #define UARTMSP432E4_PP0_U6RX GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTP, 0, GPIO_PP0_U6RX) 394 #define UARTMSP432E4_PP1_U6TX GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTP, 1, GPIO_PP1_U6TX) 400 #define UARTMSP432E4_PC4_U7RX GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTC, 4, GPIO_PC4_U7RX) 405 #define UARTMSP432E4_PH6_U7RX GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTH, 6, GPIO_PH6_U7RX) 410 #define UARTMSP432E4_PC5_U7TX GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTC, 5, GPIO_PC5_U7TX) 415 #define UARTMSP432E4_PH7_U7TX GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTH, 7, GPIO_PH7_U7TX) 575 bool inReadCallback:1;
576 volatile bool readCallbackPending:1;
UART_Callback readCallback
Definition: UARTMSP432E4.h:594
void(* UARTMSP432E4_ErrorCallback)(UART_Handle handle, uint32_t error)
The definition of an optional callback function used by the UART driver to notify the application whe...
Definition: UARTMSP432E4.h:432
UART_STOP
UART stop bit settings.
Definition: UART.h:523
uint32_t txPin
Definition: UARTMSP432E4.h:532
size_t readSize
Definition: UARTMSP432E4.h:590
RingBuf_Object ringBuffer
Definition: UARTMSP432E4.h:586
uint32_t intNum
Definition: UARTMSP432E4.h:520
UARTMSP432E4 Hardware attributes.
Definition: UARTMSP432E4.h:516
uint32_t rtsPin
Definition: UARTMSP432E4.h:536
uint32_t flowControl
Definition: UARTMSP432E4.h:524
The definition of a UART function table that contains the required set of functions to control a spec...
Definition: UART.h:635
HwiP_Handle hwi
Definition: UARTMSP432E4.h:604
UARTMSP432E4 Object.
Definition: UARTMSP432E4.h:546
UART_PAR
UART parity type settings.
Definition: UART.h:533
UART_Mode
UART mode settings.
Definition: UART.h:428
uint32_t ctsPin
Definition: UARTMSP432E4.h:534
unsigned int readTimeout
Definition: UARTMSP432E4.h:593
UART_DataMode
UART data mode settings.
Definition: UART.h:483
UART_ReturnMode
UART return mode settings.
Definition: UART.h:461
UART_Echo
UART echo settings.
Definition: UART.h:501
UART Global configuration.
Definition: UART.h:678
UART_LEN dataLength
Definition: UARTMSP432E4.h:581
size_t writeCount
Definition: UARTMSP432E4.h:599
unsigned char * ringBufPtr
Definition: UARTMSP432E4.h:526
const unsigned char * writeBuf
Definition: UARTMSP432E4.h:597
UART_STOP stopBits
Definition: UARTMSP432E4.h:582
UARTMSP432E4_FxnSet readFxns
Definition: UARTMSP432E4.h:588
UART_Callback writeCallback
Definition: UARTMSP432E4.h:602
struct UARTMSP432E4_Object * UARTMSP432E4_Handle
size_t writeSize
Definition: UARTMSP432E4.h:598
SemaphoreP_Handle writeSem
Definition: UARTMSP432E4.h:600
size_t readCount
Definition: UARTMSP432E4.h:591
UARTMSP432E4_ErrorCallback errorFxn
Definition: UARTMSP432E4.h:538
Universal Asynchronous Receiver-Transmitter (UART) Driver.
UART_PAR parityType
Definition: UARTMSP432E4.h:583
uint32_t baseAddr
Definition: UARTMSP432E4.h:518
ClockP_Handle timeoutClk
Definition: UARTMSP432E4.h:579
UART_LEN
UART data length settings.
Definition: UART.h:511
const UART_FxnTable UARTMSP432E4_fxnTable
SemaphoreP_Handle readSem
Definition: UARTMSP432E4.h:592
uint32_t baudRate
Definition: UARTMSP432E4.h:580
uint32_t rxPin
Definition: UARTMSP432E4.h:530
size_t ringBufSize
Definition: UARTMSP432E4.h:528
unsigned char * readBuf
Definition: UARTMSP432E4.h:589
uint32_t intPriority
Definition: UARTMSP432E4.h:522
unsigned int writeTimeout
Definition: UARTMSP432E4.h:601
Complement set of read functions to be used by the UART ISR and UARTMSP432E4_read(). Internal use only.
Definition: UARTMSP432E4.h:456
void(* UART_Callback)(UART_Handle handle, void *buf, size_t count)
The definition of a callback function used by the UART driver when used in UART_MODE_CALLBACK The cal...
Definition: UART.h:421