TI Cortex-M4 Timing Benchmarks

Target Platform: ti.platforms.simplelink:CC3200:1

Tool Chain Version: 18.1.4

BIOS Version: bios_6_75_00_12_eng_keystone3

XDCTools Version: xdctools_3_51_00_13_core_eng

Benchmark	Cycles
Interrupt Latency	129
Hwi_restore()	10
Hwi_disable()	14
Hwi dispatcher prolog	114
Hwi dispatcher epilog	235
Hwi dispatcher	344
Hardware Interrupt to Blocked Task	563
Hardware Interrupt to Software Interrupt	402
Swi_enable()	81
Swi_disable()	15
Post Software Interrupt Again	40
Post Software Interrupt without Context Switch	110
Post Software Interrupt with Context Switch	228
Create a New Task without Context Switch	2835
Set a Task Priority without a Context Switch	183
Task_yield()	224
Post Semaphore No Waiting Task	104
Post Semaphore No Task Switch	205
Post Semaphore with Task Switch	277
Pend on Semaphore No Context Switch	87
Pend on Semaphore with Task Switch	310
Clock_getTicks()	12
POSIX Create a New Task without Context Switch	5175
POSIX Set a Task Priority without a Context Switch	251
POSIX Post Semaphore No Waiting Task	117
POSIX Post Semaphore No Task Switch	220
POSIX Post Semaphore with Task Switch	292
POSIX Pend on Semaphore No Context Switch	98
POSIX Pend on Semaphore with Task Switch	330

The benchmark application was built using BIOS.LibType_Custom with the following BIOS.customCCOpts settings: “–endian=little -mv7M4 –float_support=vfplib –abi=eabi -q -ms –opt_for_speed=2 –program_level_compile -o3”.

To minimize the effects of wait states, the performance measurements are collected at optimal CPU clock speeds on MSP432 and Tiva devices.

See the SYS/BIOS User’s Guide for more information regarding how interrupt latency is calculated.