IAR Cortex-M4 Timing Benchmarks

Target Platform: ti.platforms.simplelink:CC3200:1

Tool Chain Version: 8.20.2.58

BIOS Version: bios_6_75_00_12_eng_keystone3

XDCTools Version: xdctools_3_51_00_13_core_eng

Benchmark	Cycles
Interrupt Latency	144
Hwi_restore()	14
Hwi_disable()	17
Hwi dispatcher prolog	121
Hwi dispatcher epilog	257
Hwi dispatcher	368
Hardware Interrupt to Blocked Task	591
Hardware Interrupt to Software Interrupt	397
Swi_enable()	78
Swi_disable()	18
Post Software Interrupt Again	26
Post Software Interrupt without Context Switch	105
Post Software Interrupt with Context Switch	209
Create a New Task without Context Switch	2658
Set a Task Priority without a Context Switch	195
Task_yield()	239
Post Semaphore No Waiting Task	84
Post Semaphore No Task Switch	206
Post Semaphore with Task Switch	277
Pend on Semaphore No Context Switch	78
Pend on Semaphore with Task Switch	315
Clock_getTicks()	14
POSIX Create a New Task without Context Switch	4728
POSIX Set a Task Priority without a Context Switch	247
POSIX Post Semaphore No Waiting Task	104
POSIX Post Semaphore No Task Switch	228
POSIX Post Semaphore with Task Switch	296
POSIX Pend on Semaphore No Context Switch	63
POSIX Pend on Semaphore with Task Switch	316

The M4 target also supports zero latency interrupts. See ti.sysbios.family.arm.m3.Hwi CDOCs for details.

See the SYS/BIOS User’s Guide for more information regarding how interrupt latency is calculated.