IAR Cortex-M4 with hard FP Timing Benchmarks

Target Platform: ti.platforms.tiva:TM4C123GH6PM:1

Tool Chain Version: 8.20.2.58

BIOS Version: bios_6_75_00_12_eng_keystone3

XDCTools Version: xdctools_3_51_00_13_core_eng

Benchmark	Cycles
Interrupt Latency	141
Hwi_restore()	7
Hwi_disable()	9
Hwi dispatcher prolog	119
Hwi dispatcher epilog	222
Hwi dispatcher	331
Hardware Interrupt to Blocked Task	516
Hardware Interrupt to Software Interrupt	334
Swi_enable()	58
Swi_disable()	11
Post Software Interrupt Again	20
Post Software Interrupt without Context Switch	81
Post Software Interrupt with Context Switch	165
Create a New Task without Context Switch	2034
Set a Task Priority without a Context Switch	148
Task_yield()	219
Post Semaphore No Waiting Task	66
Post Semaphore No Task Switch	161
Post Semaphore with Task Switch	251
Pend on Semaphore No Context Switch	58
Pend on Semaphore with Task Switch	276
Clock_getTicks()	9
POSIX Create a New Task without Context Switch	3550
POSIX Set a Task Priority without a Context Switch	189
POSIX Post Semaphore No Waiting Task	79
POSIX Post Semaphore No Task Switch	173
POSIX Post Semaphore with Task Switch	258
POSIX Pend on Semaphore No Context Switch	47
POSIX Pend on Semaphore with Task Switch	279

The M4F target also supports zero latency interrupts. See ti.sysbios.family.arm.m3.Hwi cdocs for details.

See the SYS/BIOS User’s Guide for more information regarding how interrupt latency is calculated.