38 #ifndef __DRIVERLIB_EPI_H__ 39 #define __DRIVERLIB_EPI_H__ 60 #define EPI_MODE_GENERAL 0x00000010 61 #define EPI_MODE_SDRAM 0x00000011 62 #define EPI_MODE_HB8 0x00000012 63 #define EPI_MODE_HB16 0x00000013 64 #define EPI_MODE_DISABLE 0x00000000 71 #define EPI_SDRAM_CORE_FREQ_0_15 \ 73 #define EPI_SDRAM_CORE_FREQ_15_30 \ 75 #define EPI_SDRAM_CORE_FREQ_30_50 \ 77 #define EPI_SDRAM_CORE_FREQ_50_100 \ 79 #define EPI_SDRAM_LOW_POWER 0x00000200 80 #define EPI_SDRAM_FULL_POWER 0x00000000 81 #define EPI_SDRAM_SIZE_64MBIT 0x00000000 82 #define EPI_SDRAM_SIZE_128MBIT 0x00000001 83 #define EPI_SDRAM_SIZE_256MBIT 0x00000002 84 #define EPI_SDRAM_SIZE_512MBIT 0x00000003 91 #define EPI_GPMODE_CLKPIN 0x80000000 92 #define EPI_GPMODE_CLKGATE 0x40000000 93 #define EPI_GPMODE_FRAME50 0x04000000 94 #define EPI_GPMODE_WRITE2CYCLE 0x00080000 95 #define EPI_GPMODE_ASIZE_NONE 0x00000000 96 #define EPI_GPMODE_ASIZE_4 0x00000010 97 #define EPI_GPMODE_ASIZE_12 0x00000020 98 #define EPI_GPMODE_ASIZE_20 0x00000030 99 #define EPI_GPMODE_DSIZE_8 0x00000000 100 #define EPI_GPMODE_DSIZE_16 0x00000001 101 #define EPI_GPMODE_DSIZE_24 0x00000002 102 #define EPI_GPMODE_DSIZE_32 0x00000003 109 #define EPI_HB8_USE_TXEMPTY 0x00800000 110 #define EPI_HB8_USE_RXFULL 0x00400000 111 #define EPI_HB8_WRHIGH 0x00200000 112 #define EPI_HB8_RDHIGH 0x00100000 113 #define EPI_HB8_ALE_HIGH 0x00080000 114 #define EPI_HB8_ALE_LOW 0x00000000 115 #define EPI_HB8_WRWAIT_0 0x00000000 116 #define EPI_HB8_WRWAIT_1 0x00000040 117 #define EPI_HB8_WRWAIT_2 0x00000080 118 #define EPI_HB8_WRWAIT_3 0x000000C0 119 #define EPI_HB8_RDWAIT_0 0x00000000 120 #define EPI_HB8_RDWAIT_1 0x00000010 121 #define EPI_HB8_RDWAIT_2 0x00000020 122 #define EPI_HB8_RDWAIT_3 0x00000030 123 #define EPI_HB8_MODE_ADMUX 0x00000000 124 #define EPI_HB8_MODE_ADDEMUX 0x00000001 125 #define EPI_HB8_MODE_SRAM 0x00000002 126 #define EPI_HB8_MODE_FIFO 0x00000003 127 #define EPI_HB8_CSCFG_ALE 0x00000000 128 #define EPI_HB8_CSCFG_CS 0x00000200 129 #define EPI_HB8_CSCFG_DUAL_CS 0x00000400 130 #define EPI_HB8_CSCFG_ALE_DUAL_CS \ 132 #define EPI_HB8_CSCFG_ALE_SINGLE_CS \ 134 #define EPI_HB8_CSCFG_QUAD_CS 0x00001200 135 #define EPI_HB8_CSCFG_ALE_QUAD_CS \ 137 #define EPI_HB8_CSBAUD 0x00000800 138 #define EPI_HB8_CLOCK_GATE 0x80000000 139 #define EPI_HB8_CLOCK_GATE_IDLE \ 141 #define EPI_HB8_CLOCK_INVERT 0x20000000 142 #define EPI_HB8_IN_READY_EN 0x10000000 143 #define EPI_HB8_IN_READY_EN_INVERT \ 145 #define EPI_HB8_CSCFG_MASK 0x00001600 152 #define EPI_HB16_USE_TXEMPTY 0x00800000 153 #define EPI_HB16_USE_RXFULL 0x00400000 154 #define EPI_HB16_WRHIGH 0x00200000 155 #define EPI_HB16_RDHIGH 0x00100000 156 #define EPI_HB16_WRWAIT_0 0x00000000 157 #define EPI_HB16_WRWAIT_1 0x00000040 158 #define EPI_HB16_WRWAIT_2 0x00000080 159 #define EPI_HB16_WRWAIT_3 0x000000C0 160 #define EPI_HB16_RDWAIT_0 0x00000000 161 #define EPI_HB16_RDWAIT_1 0x00000010 162 #define EPI_HB16_RDWAIT_2 0x00000020 163 #define EPI_HB16_RDWAIT_3 0x00000030 164 #define EPI_HB16_MODE_ADMUX 0x00000000 165 #define EPI_HB16_MODE_ADDEMUX 0x00000001 166 #define EPI_HB16_MODE_SRAM 0x00000002 167 #define EPI_HB16_MODE_FIFO 0x00000003 168 #define EPI_HB16_BSEL 0x00000004 169 #define EPI_HB16_CSCFG_ALE 0x00000000 170 #define EPI_HB16_CSCFG_CS 0x00000200 171 #define EPI_HB16_CSCFG_DUAL_CS 0x00000400 172 #define EPI_HB16_CSCFG_ALE_DUAL_CS \ 174 #define EPI_HB16_CSCFG_ALE_SINGLE_CS \ 176 #define EPI_HB16_CSCFG_QUAD_CS 0x00001200 177 #define EPI_HB16_CSCFG_ALE_QUAD_CS \ 179 #define EPI_HB16_CLOCK_GATE 0x80000000 180 #define EPI_HB16_CLOCK_GATE_IDLE \ 182 #define EPI_HB16_CLOCK_INVERT 0x20000000 183 #define EPI_HB16_IN_READY_EN 0x10000000 184 #define EPI_HB16_IN_READY_EN_INVERTED \ 186 #define EPI_HB16_ALE_HIGH 0x00080000 187 #define EPI_HB16_ALE_LOW 0x00000000 188 #define EPI_HB16_BURST_TRAFFIC 0x00010000 189 #define EPI_HB16_CSBAUD 0x00000800 190 #define EPI_HB16_CSCFG_MASK 0x00001600 197 #define EPI_HB8_IN_READY_DELAY_1 \ 199 #define EPI_HB8_IN_READY_DELAY_2 \ 201 #define EPI_HB8_IN_READY_DELAY_3 \ 203 #define EPI_HB8_CAP_WIDTH_1 0x00001000 204 #define EPI_HB8_CAP_WIDTH_2 0x00002000 205 #define EPI_HB8_WRWAIT_MINUS_DISABLE \ 207 #define EPI_HB8_WRWAIT_MINUS_ENABLE \ 209 #define EPI_HB8_RDWAIT_MINUS_DISABLE \ 211 #define EPI_HB8_RDWAIT_MINUS_ENABLE \ 219 #define EPI_HB16_IN_READY_DELAY_1 \ 221 #define EPI_HB16_IN_READY_DELAY_2 \ 223 #define EPI_HB16_IN_READY_DELAY_3 \ 225 #define EPI_HB16_PSRAM_NO_LIMIT 0x00000000 226 #define EPI_HB16_PSRAM_128 0x00010000 227 #define EPI_HB16_PSRAM_256 0x00020000 228 #define EPI_HB16_PSRAM_512 0x00030000 229 #define EPI_HB16_PSRAM_1024 0x00040000 230 #define EPI_HB16_PSRAM_2048 0x00050000 231 #define EPI_HB16_PSRAM_4096 0x00060000 232 #define EPI_HB16_PSRAM_8192 0x00070000 233 #define EPI_HB16_CAP_WIDTH_1 0x00001000 234 #define EPI_HB16_CAP_WIDTH_2 0x00002000 235 #define EPI_HB16_WRWAIT_MINUS_DISABLE \ 237 #define EPI_HB16_WRWAIT_MINUS_ENABLE \ 239 #define EPI_HB16_RDWAIT_MINUS_DISABLE \ 241 #define EPI_HB16_RDWAIT_MINUS_ENABLE \ 249 #define EPI_ADDR_PER_SIZE_256B 0x00000000 250 #define EPI_ADDR_PER_SIZE_64KB 0x00000040 251 #define EPI_ADDR_PER_SIZE_16MB 0x00000080 252 #define EPI_ADDR_PER_SIZE_256MB 0x000000C0 253 #define EPI_ADDR_PER_BASE_NONE 0x00000000 254 #define EPI_ADDR_PER_BASE_A 0x00000010 255 #define EPI_ADDR_PER_BASE_C 0x00000020 256 #define EPI_ADDR_RAM_SIZE_256B 0x00000000 257 #define EPI_ADDR_RAM_SIZE_64KB 0x00000004 258 #define EPI_ADDR_RAM_SIZE_16MB 0x00000008 259 #define EPI_ADDR_RAM_SIZE_256MB 0x0000000C 260 #define EPI_ADDR_RAM_BASE_NONE 0x00000000 261 #define EPI_ADDR_RAM_BASE_6 0x00000001 262 #define EPI_ADDR_RAM_BASE_8 0x00000002 263 #define EPI_ADDR_QUAD_MODE 0x00000033 264 #define EPI_ADDR_CODE_SIZE_256B 0x00000000 265 #define EPI_ADDR_CODE_SIZE_64KB 0x00000400 266 #define EPI_ADDR_CODE_SIZE_16MB 0x00000800 267 #define EPI_ADDR_CODE_SIZE_256MB \ 269 #define EPI_ADDR_CODE_BASE_NONE 0x00000000 270 #define EPI_ADDR_CODE_BASE_1 0x00000100 277 #define EPI_NBCONFIG_SIZE_8 1 278 #define EPI_NBCONFIG_SIZE_16 2 279 #define EPI_NBCONFIG_SIZE_32 3 286 #define EPI_FIFO_CONFIG_WTFULLERR \ 288 #define EPI_FIFO_CONFIG_RSTALLERR \ 290 #define EPI_FIFO_CONFIG_TX_EMPTY \ 292 #define EPI_FIFO_CONFIG_TX_1_4 0x00000020 293 #define EPI_FIFO_CONFIG_TX_1_2 0x00000030 294 #define EPI_FIFO_CONFIG_TX_3_4 0x00000040 295 #define EPI_FIFO_CONFIG_RX_1_8 0x00000001 296 #define EPI_FIFO_CONFIG_RX_1_4 0x00000002 297 #define EPI_FIFO_CONFIG_RX_1_2 0x00000003 298 #define EPI_FIFO_CONFIG_RX_3_4 0x00000004 299 #define EPI_FIFO_CONFIG_RX_7_8 0x00000005 300 #define EPI_FIFO_CONFIG_RX_FULL 0x00000006 308 #define EPI_INT_DMA_TX_DONE 0x00000010 309 #define EPI_INT_DMA_RX_DONE 0x00000008 310 #define EPI_INT_TXREQ 0x00000004 311 #define EPI_INT_RXREQ 0x00000002 312 #define EPI_INT_ERR 0x00000001 320 #define EPI_INT_ERR_DMAWRIC 0x00000010 321 #define EPI_INT_ERR_DMARDIC 0x00000008 322 #define EPI_INT_ERR_WTFULL 0x00000004 323 #define EPI_INT_ERR_RSTALL 0x00000002 324 #define EPI_INT_ERR_TIMEOUT 0x00000001 335 uint32_t ui32Scratch;
348 STR ui32Value, [pui32Addr]
354 LDR ui32Scratch, [__current_sp()]
361 uint32_t ui32Value, ui32Scratch;
374 LDR ui32Value, [pui32Addr]
380 LDR ui32Scratch, [__current_sp()]
389 uint32_t ui32Scratch;
402 STRH ui16Value, [pui16Addr]
408 LDR ui32Scratch, [__current_sp()]
415 uint32_t ui32Scratch;
429 LDRH ui16Value, [pui16Addr]
435 LDR ui32Scratch, [__current_sp()]
444 uint32_t ui32Scratch;
457 STRB ui8Value, [pui8Addr]
463 LDR ui32Scratch, [__current_sp()]
470 uint32_t ui32Scratch;
484 LDRB ui8Value, [pui8Addr]
490 LDR ui32Scratch, [__current_sp()]
513 #if (defined __GNUC__) || (defined __ICCARM__) || (defined sourcerygxx) || \ 523 volatile register uint32_t ui32Scratch;
531 " STR %[value],[%[addr]]\n" 532 " LDR %[scratch],[sp]\n" 533 : [scratch]
"=r" (ui32Scratch)
534 : [addr]
"r" (pui32Addr), [value]
"r" (ui32Value)
540 ui32Scratch = ui32Scratch;
546 volatile register uint32_t ui32Data, ui32Scratch;
559 " LDR %[ret],[%[addr]]\n" 560 " LDR %[scratch],[sp]\n" 561 : [ret]
"=r" (ui32Data),
562 [scratch]
"=r" (ui32Scratch)
563 : [addr]
"r" (pui32Addr)
570 ui32Scratch = ui32Scratch;
578 volatile register uint32_t ui32Scratch;
586 " STRH %[value],[%[addr]]\n" 587 " LDR %[scratch],[sp]\n" 588 : [scratch]
"=r" (ui32Scratch)
589 : [addr]
"r" (pui16Addr), [value]
"r" (ui16Value)
596 ui32Scratch = ui32Scratch;
602 register uint16_t ui16Data;
603 register uint32_t ui32Scratch;
616 " LDRH %[ret],[%[addr]]\n" 617 " LDR %[scratch],[sp]\n" 618 : [ret]
"=r" (ui16Data),
619 [scratch]
"=r" (ui32Scratch)
620 : [addr]
"r" (pui16Addr)
626 ui32Scratch = ui32Scratch;
634 volatile register uint32_t ui32Scratch;
642 " STRB %[value],[%[addr]]\n" 643 " LDR %[scratch],[sp]\n" 644 : [scratch]
"=r" (ui32Scratch)
645 : [addr]
"r" (pui8Addr), [value]
"r" (ui8Value)
651 ui32Scratch = ui32Scratch;
657 register uint8_t ui8Data;
658 register uint32_t ui32Scratch;
671 " LDRB %[ret],[%[addr]]\n" 672 " LDR %[scratch],[sp]\n" 673 : [ret]
"=r" (ui8Data),
674 [scratch]
"=r" (ui32Scratch)
675 : [addr]
"r" (pui8Addr)
681 ui32Scratch = ui32Scratch;
692 extern void EPIModeSet(uint32_t ui32Base, uint32_t ui32Mode);
693 extern void EPIDividerSet(uint32_t ui32Base, uint32_t ui32Divider);
695 uint32_t ui32Divider);
696 extern void EPIDMATxCount(uint32_t ui32Base, uint32_t ui32Count);
698 uint32_t ui32FrameCount, uint32_t ui32MaxWait);
700 uint32_t ui32MaxWait);
702 uint32_t ui32MaxWait);
704 uint32_t ui32Config);
706 uint32_t ui32Config);
708 uint32_t ui32Config);
710 uint32_t ui32Config);
719 uint32_t ui32Refresh);
722 uint32_t ui32Channel,
723 uint32_t ui32DataSize,
724 uint32_t ui32Address);
726 uint32_t ui32Channel,
729 uint32_t ui32Channel);
731 uint32_t ui32Channel);
742 extern void EPIFIFOConfig(uint32_t ui32Base, uint32_t ui32Config);
744 extern void EPIIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags);
745 extern void EPIIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags);
746 extern uint32_t
EPIIntStatus(uint32_t ui32Base,
bool bMasked);
749 extern void EPIIntRegister(uint32_t ui32Base,
void (*pfnHandler)(
void));
761 #endif // __DRIVERLIB_EPI_H__ uint32_t EPINonBlockingReadGet8(uint32_t ui32Base, uint32_t ui32Count, uint8_t *pui8Buf)
Definition: epi.c:1694
void EPINonBlockingReadStart(uint32_t ui32Base, uint32_t ui32Channel, uint32_t ui32Count)
Definition: epi.c:1444
void EPIDMATxCount(uint32_t ui32Base, uint32_t ui32Count)
Definition: epi.c:380
void EPIConfigHB8Set(uint32_t ui32Base, uint32_t ui32Config, uint32_t ui32MaxWait)
Definition: epi.c:549
void EPIWorkaroundByteWrite(uint8_t *pui8Addr, uint8_t ui8Value)
void EPIModeSet(uint32_t ui32Base, uint32_t ui32Mode)
Definition: epi.c:249
void EPIConfigHB8TimingSet(uint32_t ui32Base, uint32_t ui32CS, uint32_t ui32Config)
Definition: epi.c:914
void EPINonBlockingReadConfigure(uint32_t ui32Base, uint32_t ui32Channel, uint32_t ui32DataSize, uint32_t ui32Address)
Definition: epi.c:1392
void EPIConfigHB16TimingSet(uint32_t ui32Base, uint32_t ui32CS, uint32_t ui32Config)
Definition: epi.c:985
uint32_t EPINonBlockingReadGet16(uint32_t ui32Base, uint32_t ui32Count, uint16_t *pui16Buf)
Definition: epi.c:1639
void EPIWorkaroundWordWrite(uint32_t *pui32Addr, uint32_t ui32Value)
uint32_t EPINonBlockingReadCount(uint32_t ui32Base, uint32_t ui32Channel)
Definition: epi.c:1516
void EPIConfigHB16Set(uint32_t ui32Base, uint32_t ui32Config, uint32_t ui32MaxWait)
Definition: epi.c:680
void EPIPSRAMConfigRegSet(uint32_t ui32Base, uint32_t ui32CS, uint32_t ui32CR)
Definition: epi.c:1020
uint32_t EPIWorkaroundWordRead(uint32_t *pui32Addr)
void EPIWorkaroundHWordWrite(uint16_t *pui16Addr, uint16_t ui16Value)
uint32_t EPIPSRAMConfigRegGet(uint32_t ui32Base, uint32_t ui32CS)
Definition: epi.c:1194
void EPIIntErrorClear(uint32_t ui32Base, uint32_t ui32ErrFlags)
Definition: epi.c:1974
uint32_t EPINonBlockingReadAvail(uint32_t ui32Base)
Definition: epi.c:1552
void EPINonBlockingReadStop(uint32_t ui32Base, uint32_t ui32Channel)
Definition: epi.c:1481
void EPIConfigGPModeSet(uint32_t ui32Base, uint32_t ui32Config, uint32_t ui32FrameCount, uint32_t ui32MaxWait)
Definition: epi.c:1271
void EPIFIFOConfig(uint32_t ui32Base, uint32_t ui32Config)
Definition: epi.c:1762
uint32_t EPIIntErrorStatus(uint32_t ui32Base)
Definition: epi.c:1937
void EPIDividerCSSet(uint32_t ui32Base, uint32_t ui32CS, uint32_t ui32Divider)
Definition: epi.c:332
bool EPIPSRAMConfigRegGetNonBlocking(uint32_t ui32Base, uint32_t ui32CS, uint32_t *pui32CR)
Definition: epi.c:1128
void EPIIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags)
Definition: epi.c:1824
void EPIConfigSDRAMSet(uint32_t ui32Base, uint32_t ui32Config, uint32_t ui32Refresh)
Definition: epi.c:433
void EPIConfigHB8CSSet(uint32_t ui32Base, uint32_t ui32CS, uint32_t ui32Config)
Definition: epi.c:754
uint32_t EPINonBlockingReadGet32(uint32_t ui32Base, uint32_t ui32Count, uint32_t *pui32Buf)
Definition: epi.c:1584
uint16_t EPIWorkaroundHWordRead(uint16_t *pui16Addr)
void EPIAddressMapSet(uint32_t ui32Base, uint32_t ui32Map)
Definition: epi.c:1347
void EPIIntUnregister(uint32_t ui32Base)
Definition: epi.c:2079
void EPIIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags)
Definition: epi.c:1859
uint8_t EPIWorkaroundByteRead(uint8_t *pui8Addr)
void EPIDividerSet(uint32_t ui32Base, uint32_t ui32Divider)
Definition: epi.c:295
uint32_t EPIWriteFIFOCountGet(uint32_t ui32Base)
Definition: epi.c:1790
void EPIIntRegister(uint32_t ui32Base, void(*pfnHandler)(void))
Definition: epi.c:2035
uint32_t EPIIntStatus(uint32_t ui32Base, bool bMasked)
Definition: epi.c:1895
void EPIConfigHB16CSSet(uint32_t ui32Base, uint32_t ui32CS, uint32_t ui32Config)
Definition: epi.c:837
void EPIPSRAMConfigRegRead(uint32_t ui32Base, uint32_t ui32CS)
Definition: epi.c:1075