hw_adc.h
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1 //*****************************************************************************
2 //
3 // hw_adc.h - Macros used when accessing the ADC hardware.
4 //
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37 
38 #ifndef __HW_ADC_H__
39 #define __HW_ADC_H__
40 
41 //*****************************************************************************
42 //
43 // The following are defines for the ADC register offsets.
44 //
45 //*****************************************************************************
46 #define ADC_O_ACTSS 0x00000000 // ADC Active Sample Sequencer
47 #define ADC_O_RIS 0x00000004 // ADC Raw Interrupt Status
48 #define ADC_O_IM 0x00000008 // ADC Interrupt Mask
49 #define ADC_O_ISC 0x0000000C // ADC Interrupt Status and Clear
50 #define ADC_O_OSTAT 0x00000010 // ADC Overflow Status
51 #define ADC_O_EMUX 0x00000014 // ADC Event Multiplexer Select
52 #define ADC_O_USTAT 0x00000018 // ADC Underflow Status
53 #define ADC_O_TSSEL 0x0000001C // ADC Trigger Source Select
54 #define ADC_O_SSPRI 0x00000020 // ADC Sample Sequencer Priority
55 #define ADC_O_SPC 0x00000024 // ADC Sample Phase Control
56 #define ADC_O_PSSI 0x00000028 // ADC Processor Sample Sequence
57  // Initiate
58 #define ADC_O_SAC 0x00000030 // ADC Sample Averaging Control
59 #define ADC_O_DCISC 0x00000034 // ADC Digital Comparator Interrupt
60  // Status and Clear
61 #define ADC_O_CTL 0x00000038 // ADC Control
62 #define ADC_O_SSMUX0 0x00000040 // ADC Sample Sequence Input
63  // Multiplexer Select 0
64 #define ADC_O_SSCTL0 0x00000044 // ADC Sample Sequence Control 0
65 #define ADC_O_SSFIFO0 0x00000048 // ADC Sample Sequence Result FIFO
66  // 0
67 #define ADC_O_SSFSTAT0 0x0000004C // ADC Sample Sequence FIFO 0
68  // Status
69 #define ADC_O_SSOP0 0x00000050 // ADC Sample Sequence 0 Operation
70 #define ADC_O_SSDC0 0x00000054 // ADC Sample Sequence 0 Digital
71  // Comparator Select
72 #define ADC_O_SSEMUX0 0x00000058 // ADC Sample Sequence Extended
73  // Input Multiplexer Select 0
74 #define ADC_O_SSTSH0 0x0000005C // ADC Sample Sequence 0 Sample and
75  // Hold Time
76 #define ADC_O_SSMUX1 0x00000060 // ADC Sample Sequence Input
77  // Multiplexer Select 1
78 #define ADC_O_SSCTL1 0x00000064 // ADC Sample Sequence Control 1
79 #define ADC_O_SSFIFO1 0x00000068 // ADC Sample Sequence Result FIFO
80  // 1
81 #define ADC_O_SSFSTAT1 0x0000006C // ADC Sample Sequence FIFO 1
82  // Status
83 #define ADC_O_SSOP1 0x00000070 // ADC Sample Sequence 1 Operation
84 #define ADC_O_SSDC1 0x00000074 // ADC Sample Sequence 1 Digital
85  // Comparator Select
86 #define ADC_O_SSEMUX1 0x00000078 // ADC Sample Sequence Extended
87  // Input Multiplexer Select 1
88 #define ADC_O_SSTSH1 0x0000007C // ADC Sample Sequence 1 Sample and
89  // Hold Time
90 #define ADC_O_SSMUX2 0x00000080 // ADC Sample Sequence Input
91  // Multiplexer Select 2
92 #define ADC_O_SSCTL2 0x00000084 // ADC Sample Sequence Control 2
93 #define ADC_O_SSFIFO2 0x00000088 // ADC Sample Sequence Result FIFO
94  // 2
95 #define ADC_O_SSFSTAT2 0x0000008C // ADC Sample Sequence FIFO 2
96  // Status
97 #define ADC_O_SSOP2 0x00000090 // ADC Sample Sequence 2 Operation
98 #define ADC_O_SSDC2 0x00000094 // ADC Sample Sequence 2 Digital
99  // Comparator Select
100 #define ADC_O_SSEMUX2 0x00000098 // ADC Sample Sequence Extended
101  // Input Multiplexer Select 2
102 #define ADC_O_SSTSH2 0x0000009C // ADC Sample Sequence 2 Sample and
103  // Hold Time
104 #define ADC_O_SSMUX3 0x000000A0 // ADC Sample Sequence Input
105  // Multiplexer Select 3
106 #define ADC_O_SSCTL3 0x000000A4 // ADC Sample Sequence Control 3
107 #define ADC_O_SSFIFO3 0x000000A8 // ADC Sample Sequence Result FIFO
108  // 3
109 #define ADC_O_SSFSTAT3 0x000000AC // ADC Sample Sequence FIFO 3
110  // Status
111 #define ADC_O_SSOP3 0x000000B0 // ADC Sample Sequence 3 Operation
112 #define ADC_O_SSDC3 0x000000B4 // ADC Sample Sequence 3 Digital
113  // Comparator Select
114 #define ADC_O_SSEMUX3 0x000000B8 // ADC Sample Sequence Extended
115  // Input Multiplexer Select 3
116 #define ADC_O_SSTSH3 0x000000BC // ADC Sample Sequence 3 Sample and
117  // Hold Time
118 #define ADC_O_DCRIC 0x00000D00 // ADC Digital Comparator Reset
119  // Initial Conditions
120 #define ADC_O_DCCTL0 0x00000E00 // ADC Digital Comparator Control 0
121 #define ADC_O_DCCTL1 0x00000E04 // ADC Digital Comparator Control 1
122 #define ADC_O_DCCTL2 0x00000E08 // ADC Digital Comparator Control 2
123 #define ADC_O_DCCTL3 0x00000E0C // ADC Digital Comparator Control 3
124 #define ADC_O_DCCTL4 0x00000E10 // ADC Digital Comparator Control 4
125 #define ADC_O_DCCTL5 0x00000E14 // ADC Digital Comparator Control 5
126 #define ADC_O_DCCTL6 0x00000E18 // ADC Digital Comparator Control 6
127 #define ADC_O_DCCTL7 0x00000E1C // ADC Digital Comparator Control 7
128 #define ADC_O_DCCMP0 0x00000E40 // ADC Digital Comparator Range 0
129 #define ADC_O_DCCMP1 0x00000E44 // ADC Digital Comparator Range 1
130 #define ADC_O_DCCMP2 0x00000E48 // ADC Digital Comparator Range 2
131 #define ADC_O_DCCMP3 0x00000E4C // ADC Digital Comparator Range 3
132 #define ADC_O_DCCMP4 0x00000E50 // ADC Digital Comparator Range 4
133 #define ADC_O_DCCMP5 0x00000E54 // ADC Digital Comparator Range 5
134 #define ADC_O_DCCMP6 0x00000E58 // ADC Digital Comparator Range 6
135 #define ADC_O_DCCMP7 0x00000E5C // ADC Digital Comparator Range 7
136 #define ADC_O_PP 0x00000FC0 // ADC Peripheral Properties
137 #define ADC_O_PC 0x00000FC4 // ADC Peripheral Configuration
138 #define ADC_O_CC 0x00000FC8 // ADC Clock Configuration
139 
140 //*****************************************************************************
141 //
142 // The following are defines for the bit fields in the ADC_O_ACTSS register.
143 //
144 //*****************************************************************************
145 #define ADC_ACTSS_BUSY 0x00010000 // ADC Busy
146 #define ADC_ACTSS_ADEN3 0x00000800 // ADC SS3 DMA Enable
147 #define ADC_ACTSS_ADEN2 0x00000400 // ADC SS2 DMA Enable
148 #define ADC_ACTSS_ADEN1 0x00000200 // ADC SS1 DMA Enable
149 #define ADC_ACTSS_ADEN0 0x00000100 // ADC SS1 DMA Enable
150 #define ADC_ACTSS_ASEN3 0x00000008 // ADC SS3 Enable
151 #define ADC_ACTSS_ASEN2 0x00000004 // ADC SS2 Enable
152 #define ADC_ACTSS_ASEN1 0x00000002 // ADC SS1 Enable
153 #define ADC_ACTSS_ASEN0 0x00000001 // ADC SS0 Enable
154 
155 //*****************************************************************************
156 //
157 // The following are defines for the bit fields in the ADC_O_RIS register.
158 //
159 //*****************************************************************************
160 #define ADC_RIS_INRDC 0x00010000 // Digital Comparator Raw Interrupt
161  // Status
162 #define ADC_RIS_DMAINR3 0x00000800 // SS3 DMA Raw Interrupt Status
163 #define ADC_RIS_DMAINR2 0x00000400 // SS2 DMA Raw Interrupt Status
164 #define ADC_RIS_DMAINR1 0x00000200 // SS1 DMA Raw Interrupt Status
165 #define ADC_RIS_DMAINR0 0x00000100 // SS0 DMA Raw Interrupt Status
166 #define ADC_RIS_INR3 0x00000008 // SS3 Raw Interrupt Status
167 #define ADC_RIS_INR2 0x00000004 // SS2 Raw Interrupt Status
168 #define ADC_RIS_INR1 0x00000002 // SS1 Raw Interrupt Status
169 #define ADC_RIS_INR0 0x00000001 // SS0 Raw Interrupt Status
170 
171 //*****************************************************************************
172 //
173 // The following are defines for the bit fields in the ADC_O_IM register.
174 //
175 //*****************************************************************************
176 #define ADC_IM_DCONSS3 0x00080000 // Digital Comparator Interrupt on
177  // SS3
178 #define ADC_IM_DCONSS2 0x00040000 // Digital Comparator Interrupt on
179  // SS2
180 #define ADC_IM_DCONSS1 0x00020000 // Digital Comparator Interrupt on
181  // SS1
182 #define ADC_IM_DCONSS0 0x00010000 // Digital Comparator Interrupt on
183  // SS0
184 #define ADC_IM_DMAMASK3 0x00000800 // SS3 DMA Interrupt Mask
185 #define ADC_IM_DMAMASK2 0x00000400 // SS2 DMA Interrupt Mask
186 #define ADC_IM_DMAMASK1 0x00000200 // SS1 DMA Interrupt Mask
187 #define ADC_IM_DMAMASK0 0x00000100 // SS0 DMA Interrupt Mask
188 #define ADC_IM_MASK3 0x00000008 // SS3 Interrupt Mask
189 #define ADC_IM_MASK2 0x00000004 // SS2 Interrupt Mask
190 #define ADC_IM_MASK1 0x00000002 // SS1 Interrupt Mask
191 #define ADC_IM_MASK0 0x00000001 // SS0 Interrupt Mask
192 
193 //*****************************************************************************
194 //
195 // The following are defines for the bit fields in the ADC_O_ISC register.
196 //
197 //*****************************************************************************
198 #define ADC_ISC_DCINSS3 0x00080000 // Digital Comparator Interrupt
199  // Status on SS3
200 #define ADC_ISC_DCINSS2 0x00040000 // Digital Comparator Interrupt
201  // Status on SS2
202 #define ADC_ISC_DCINSS1 0x00020000 // Digital Comparator Interrupt
203  // Status on SS1
204 #define ADC_ISC_DCINSS0 0x00010000 // Digital Comparator Interrupt
205  // Status on SS0
206 #define ADC_ISC_DMAIN3 0x00000800 // SS3 DMA Interrupt Status and
207  // Clear
208 #define ADC_ISC_DMAIN2 0x00000400 // SS2 DMA Interrupt Status and
209  // Clear
210 #define ADC_ISC_DMAIN1 0x00000200 // SS1 DMA Interrupt Status and
211  // Clear
212 #define ADC_ISC_DMAIN0 0x00000100 // SS0 DMA Interrupt Status and
213  // Clear
214 #define ADC_ISC_IN3 0x00000008 // SS3 Interrupt Status and Clear
215 #define ADC_ISC_IN2 0x00000004 // SS2 Interrupt Status and Clear
216 #define ADC_ISC_IN1 0x00000002 // SS1 Interrupt Status and Clear
217 #define ADC_ISC_IN0 0x00000001 // SS0 Interrupt Status and Clear
218 
219 //*****************************************************************************
220 //
221 // The following are defines for the bit fields in the ADC_O_OSTAT register.
222 //
223 //*****************************************************************************
224 #define ADC_OSTAT_OV3 0x00000008 // SS3 FIFO Overflow
225 #define ADC_OSTAT_OV2 0x00000004 // SS2 FIFO Overflow
226 #define ADC_OSTAT_OV1 0x00000002 // SS1 FIFO Overflow
227 #define ADC_OSTAT_OV0 0x00000001 // SS0 FIFO Overflow
228 
229 //*****************************************************************************
230 //
231 // The following are defines for the bit fields in the ADC_O_EMUX register.
232 //
233 //*****************************************************************************
234 #define ADC_EMUX_EM3_M 0x0000F000 // SS3 Trigger Select
235 #define ADC_EMUX_EM3_PROCESSOR 0x00000000 // Processor (default)
236 #define ADC_EMUX_EM3_COMP0 0x00001000 // Analog Comparator 0
237 #define ADC_EMUX_EM3_COMP1 0x00002000 // Analog Comparator 1
238 #define ADC_EMUX_EM3_COMP2 0x00003000 // Analog Comparator 2
239 #define ADC_EMUX_EM3_EXTERNAL 0x00004000 // External (GPIO Pins)
240 #define ADC_EMUX_EM3_TIMER 0x00005000 // Timer
241 #define ADC_EMUX_EM3_PWM0 0x00006000 // PWM generator 0
242 #define ADC_EMUX_EM3_PWM1 0x00007000 // PWM generator 1
243 #define ADC_EMUX_EM3_PWM2 0x00008000 // PWM generator 2
244 #define ADC_EMUX_EM3_PWM3 0x00009000 // PWM generator 3
245 #define ADC_EMUX_EM3_NEVER 0x0000E000 // Never Trigger
246 #define ADC_EMUX_EM3_ALWAYS 0x0000F000 // Always (continuously sample)
247 #define ADC_EMUX_EM2_M 0x00000F00 // SS2 Trigger Select
248 #define ADC_EMUX_EM2_PROCESSOR 0x00000000 // Processor (default)
249 #define ADC_EMUX_EM2_COMP0 0x00000100 // Analog Comparator 0
250 #define ADC_EMUX_EM2_COMP1 0x00000200 // Analog Comparator 1
251 #define ADC_EMUX_EM2_COMP2 0x00000300 // Analog Comparator 2
252 #define ADC_EMUX_EM2_EXTERNAL 0x00000400 // External (GPIO Pins)
253 #define ADC_EMUX_EM2_TIMER 0x00000500 // Timer
254 #define ADC_EMUX_EM2_PWM0 0x00000600 // PWM generator 0
255 #define ADC_EMUX_EM2_PWM1 0x00000700 // PWM generator 1
256 #define ADC_EMUX_EM2_PWM2 0x00000800 // PWM generator 2
257 #define ADC_EMUX_EM2_PWM3 0x00000900 // PWM generator 3
258 #define ADC_EMUX_EM2_NEVER 0x00000E00 // Never Trigger
259 #define ADC_EMUX_EM2_ALWAYS 0x00000F00 // Always (continuously sample)
260 #define ADC_EMUX_EM1_M 0x000000F0 // SS1 Trigger Select
261 #define ADC_EMUX_EM1_PROCESSOR 0x00000000 // Processor (default)
262 #define ADC_EMUX_EM1_COMP0 0x00000010 // Analog Comparator 0
263 #define ADC_EMUX_EM1_COMP1 0x00000020 // Analog Comparator 1
264 #define ADC_EMUX_EM1_COMP2 0x00000030 // Analog Comparator 2
265 #define ADC_EMUX_EM1_EXTERNAL 0x00000040 // External (GPIO Pins)
266 #define ADC_EMUX_EM1_TIMER 0x00000050 // Timer
267 #define ADC_EMUX_EM1_PWM0 0x00000060 // PWM generator 0
268 #define ADC_EMUX_EM1_PWM1 0x00000070 // PWM generator 1
269 #define ADC_EMUX_EM1_PWM2 0x00000080 // PWM generator 2
270 #define ADC_EMUX_EM1_PWM3 0x00000090 // PWM generator 3
271 #define ADC_EMUX_EM1_NEVER 0x000000E0 // Never Trigger
272 #define ADC_EMUX_EM1_ALWAYS 0x000000F0 // Always (continuously sample)
273 #define ADC_EMUX_EM0_M 0x0000000F // SS0 Trigger Select
274 #define ADC_EMUX_EM0_PROCESSOR 0x00000000 // Processor (default)
275 #define ADC_EMUX_EM0_COMP0 0x00000001 // Analog Comparator 0
276 #define ADC_EMUX_EM0_COMP1 0x00000002 // Analog Comparator 1
277 #define ADC_EMUX_EM0_COMP2 0x00000003 // Analog Comparator 2
278 #define ADC_EMUX_EM0_EXTERNAL 0x00000004 // External (GPIO Pins)
279 #define ADC_EMUX_EM0_TIMER 0x00000005 // Timer
280 #define ADC_EMUX_EM0_PWM0 0x00000006 // PWM generator 0
281 #define ADC_EMUX_EM0_PWM1 0x00000007 // PWM generator 1
282 #define ADC_EMUX_EM0_PWM2 0x00000008 // PWM generator 2
283 #define ADC_EMUX_EM0_PWM3 0x00000009 // PWM generator 3
284 #define ADC_EMUX_EM0_NEVER 0x0000000E // Never Trigger
285 #define ADC_EMUX_EM0_ALWAYS 0x0000000F // Always (continuously sample)
286 
287 //*****************************************************************************
288 //
289 // The following are defines for the bit fields in the ADC_O_USTAT register.
290 //
291 //*****************************************************************************
292 #define ADC_USTAT_UV3 0x00000008 // SS3 FIFO Underflow
293 #define ADC_USTAT_UV2 0x00000004 // SS2 FIFO Underflow
294 #define ADC_USTAT_UV1 0x00000002 // SS1 FIFO Underflow
295 #define ADC_USTAT_UV0 0x00000001 // SS0 FIFO Underflow
296 
297 //*****************************************************************************
298 //
299 // The following are defines for the bit fields in the ADC_O_TSSEL register.
300 //
301 //*****************************************************************************
302 #define ADC_TSSEL_PS3_M 0x30000000 // Generator 3 PWM Module Trigger
303  // Select
304 #define ADC_TSSEL_PS3_0 0x00000000 // Use Generator 3 (and its
305  // trigger) in PWM module 0
306 #define ADC_TSSEL_PS2_M 0x00300000 // Generator 2 PWM Module Trigger
307  // Select
308 #define ADC_TSSEL_PS2_0 0x00000000 // Use Generator 2 (and its
309  // trigger) in PWM module 0
310 #define ADC_TSSEL_PS1_M 0x00003000 // Generator 1 PWM Module Trigger
311  // Select
312 #define ADC_TSSEL_PS1_0 0x00000000 // Use Generator 1 (and its
313  // trigger) in PWM module 0
314 #define ADC_TSSEL_PS0_M 0x00000030 // Generator 0 PWM Module Trigger
315  // Select
316 #define ADC_TSSEL_PS0_0 0x00000000 // Use Generator 0 (and its
317  // trigger) in PWM module 0
318 
319 //*****************************************************************************
320 //
321 // The following are defines for the bit fields in the ADC_O_SSPRI register.
322 //
323 //*****************************************************************************
324 #define ADC_SSPRI_SS3_M 0x00003000 // SS3 Priority
325 #define ADC_SSPRI_SS2_M 0x00000300 // SS2 Priority
326 #define ADC_SSPRI_SS1_M 0x00000030 // SS1 Priority
327 #define ADC_SSPRI_SS0_M 0x00000003 // SS0 Priority
328 
329 //*****************************************************************************
330 //
331 // The following are defines for the bit fields in the ADC_O_SPC register.
332 //
333 //*****************************************************************************
334 #define ADC_SPC_PHASE_M 0x0000000F // Phase Difference
335 #define ADC_SPC_PHASE_0 0x00000000 // ADC sample lags by 0.0
336 #define ADC_SPC_PHASE_22_5 0x00000001 // ADC sample lags by 22.5
337 #define ADC_SPC_PHASE_45 0x00000002 // ADC sample lags by 45.0
338 #define ADC_SPC_PHASE_67_5 0x00000003 // ADC sample lags by 67.5
339 #define ADC_SPC_PHASE_90 0x00000004 // ADC sample lags by 90.0
340 #define ADC_SPC_PHASE_112_5 0x00000005 // ADC sample lags by 112.5
341 #define ADC_SPC_PHASE_135 0x00000006 // ADC sample lags by 135.0
342 #define ADC_SPC_PHASE_157_5 0x00000007 // ADC sample lags by 157.5
343 #define ADC_SPC_PHASE_180 0x00000008 // ADC sample lags by 180.0
344 #define ADC_SPC_PHASE_202_5 0x00000009 // ADC sample lags by 202.5
345 #define ADC_SPC_PHASE_225 0x0000000A // ADC sample lags by 225.0
346 #define ADC_SPC_PHASE_247_5 0x0000000B // ADC sample lags by 247.5
347 #define ADC_SPC_PHASE_270 0x0000000C // ADC sample lags by 270.0
348 #define ADC_SPC_PHASE_292_5 0x0000000D // ADC sample lags by 292.5
349 #define ADC_SPC_PHASE_315 0x0000000E // ADC sample lags by 315.0
350 #define ADC_SPC_PHASE_337_5 0x0000000F // ADC sample lags by 337.5
351 
352 //*****************************************************************************
353 //
354 // The following are defines for the bit fields in the ADC_O_PSSI register.
355 //
356 //*****************************************************************************
357 #define ADC_PSSI_GSYNC 0x80000000 // Global Synchronize
358 #define ADC_PSSI_SYNCWAIT 0x08000000 // Synchronize Wait
359 #define ADC_PSSI_SS3 0x00000008 // SS3 Initiate
360 #define ADC_PSSI_SS2 0x00000004 // SS2 Initiate
361 #define ADC_PSSI_SS1 0x00000002 // SS1 Initiate
362 #define ADC_PSSI_SS0 0x00000001 // SS0 Initiate
363 
364 //*****************************************************************************
365 //
366 // The following are defines for the bit fields in the ADC_O_SAC register.
367 //
368 //*****************************************************************************
369 #define ADC_SAC_AVG_M 0x00000007 // Hardware Averaging Control
370 #define ADC_SAC_AVG_OFF 0x00000000 // No hardware oversampling
371 #define ADC_SAC_AVG_2X 0x00000001 // 2x hardware oversampling
372 #define ADC_SAC_AVG_4X 0x00000002 // 4x hardware oversampling
373 #define ADC_SAC_AVG_8X 0x00000003 // 8x hardware oversampling
374 #define ADC_SAC_AVG_16X 0x00000004 // 16x hardware oversampling
375 #define ADC_SAC_AVG_32X 0x00000005 // 32x hardware oversampling
376 #define ADC_SAC_AVG_64X 0x00000006 // 64x hardware oversampling
377 
378 //*****************************************************************************
379 //
380 // The following are defines for the bit fields in the ADC_O_DCISC register.
381 //
382 //*****************************************************************************
383 #define ADC_DCISC_DCINT7 0x00000080 // Digital Comparator 7 Interrupt
384  // Status and Clear
385 #define ADC_DCISC_DCINT6 0x00000040 // Digital Comparator 6 Interrupt
386  // Status and Clear
387 #define ADC_DCISC_DCINT5 0x00000020 // Digital Comparator 5 Interrupt
388  // Status and Clear
389 #define ADC_DCISC_DCINT4 0x00000010 // Digital Comparator 4 Interrupt
390  // Status and Clear
391 #define ADC_DCISC_DCINT3 0x00000008 // Digital Comparator 3 Interrupt
392  // Status and Clear
393 #define ADC_DCISC_DCINT2 0x00000004 // Digital Comparator 2 Interrupt
394  // Status and Clear
395 #define ADC_DCISC_DCINT1 0x00000002 // Digital Comparator 1 Interrupt
396  // Status and Clear
397 #define ADC_DCISC_DCINT0 0x00000001 // Digital Comparator 0 Interrupt
398  // Status and Clear
399 
400 //*****************************************************************************
401 //
402 // The following are defines for the bit fields in the ADC_O_CTL register.
403 //
404 //*****************************************************************************
405 #define ADC_CTL_VREF_M 0x00000001 // Voltage Reference Select
406 #define ADC_CTL_VREF_INTERNAL 0x00000000 // VDDA and GNDA are the voltage
407  // references
408 #define ADC_CTL_VREF_EXT_3V 0x00000001 // The external VREFA+ and VREFA-
409  // inputs are the voltage
410  // references
411 
412 //*****************************************************************************
413 //
414 // The following are defines for the bit fields in the ADC_O_SSMUX0 register.
415 //
416 //*****************************************************************************
417 #define ADC_SSMUX0_MUX7_M 0xF0000000 // 8th Sample Input Select
418 #define ADC_SSMUX0_MUX6_M 0x0F000000 // 7th Sample Input Select
419 #define ADC_SSMUX0_MUX5_M 0x00F00000 // 6th Sample Input Select
420 #define ADC_SSMUX0_MUX4_M 0x000F0000 // 5th Sample Input Select
421 #define ADC_SSMUX0_MUX3_M 0x0000F000 // 4th Sample Input Select
422 #define ADC_SSMUX0_MUX2_M 0x00000F00 // 3rd Sample Input Select
423 #define ADC_SSMUX0_MUX1_M 0x000000F0 // 2nd Sample Input Select
424 #define ADC_SSMUX0_MUX0_M 0x0000000F // 1st Sample Input Select
425 #define ADC_SSMUX0_MUX7_S 28
426 #define ADC_SSMUX0_MUX6_S 24
427 #define ADC_SSMUX0_MUX5_S 20
428 #define ADC_SSMUX0_MUX4_S 16
429 #define ADC_SSMUX0_MUX3_S 12
430 #define ADC_SSMUX0_MUX2_S 8
431 #define ADC_SSMUX0_MUX1_S 4
432 #define ADC_SSMUX0_MUX0_S 0
433 
434 //*****************************************************************************
435 //
436 // The following are defines for the bit fields in the ADC_O_SSCTL0 register.
437 //
438 //*****************************************************************************
439 #define ADC_SSCTL0_TS7 0x80000000 // 8th Sample Temp Sensor Select
440 #define ADC_SSCTL0_IE7 0x40000000 // 8th Sample Interrupt Enable
441 #define ADC_SSCTL0_END7 0x20000000 // 8th Sample is End of Sequence
442 #define ADC_SSCTL0_D7 0x10000000 // 8th Sample Differential Input
443  // Select
444 #define ADC_SSCTL0_TS6 0x08000000 // 7th Sample Temp Sensor Select
445 #define ADC_SSCTL0_IE6 0x04000000 // 7th Sample Interrupt Enable
446 #define ADC_SSCTL0_END6 0x02000000 // 7th Sample is End of Sequence
447 #define ADC_SSCTL0_D6 0x01000000 // 7th Sample Differential Input
448  // Select
449 #define ADC_SSCTL0_TS5 0x00800000 // 6th Sample Temp Sensor Select
450 #define ADC_SSCTL0_IE5 0x00400000 // 6th Sample Interrupt Enable
451 #define ADC_SSCTL0_END5 0x00200000 // 6th Sample is End of Sequence
452 #define ADC_SSCTL0_D5 0x00100000 // 6th Sample Differential Input
453  // Select
454 #define ADC_SSCTL0_TS4 0x00080000 // 5th Sample Temp Sensor Select
455 #define ADC_SSCTL0_IE4 0x00040000 // 5th Sample Interrupt Enable
456 #define ADC_SSCTL0_END4 0x00020000 // 5th Sample is End of Sequence
457 #define ADC_SSCTL0_D4 0x00010000 // 5th Sample Differential Input
458  // Select
459 #define ADC_SSCTL0_TS3 0x00008000 // 4th Sample Temp Sensor Select
460 #define ADC_SSCTL0_IE3 0x00004000 // 4th Sample Interrupt Enable
461 #define ADC_SSCTL0_END3 0x00002000 // 4th Sample is End of Sequence
462 #define ADC_SSCTL0_D3 0x00001000 // 4th Sample Differential Input
463  // Select
464 #define ADC_SSCTL0_TS2 0x00000800 // 3rd Sample Temp Sensor Select
465 #define ADC_SSCTL0_IE2 0x00000400 // 3rd Sample Interrupt Enable
466 #define ADC_SSCTL0_END2 0x00000200 // 3rd Sample is End of Sequence
467 #define ADC_SSCTL0_D2 0x00000100 // 3rd Sample Differential Input
468  // Select
469 #define ADC_SSCTL0_TS1 0x00000080 // 2nd Sample Temp Sensor Select
470 #define ADC_SSCTL0_IE1 0x00000040 // 2nd Sample Interrupt Enable
471 #define ADC_SSCTL0_END1 0x00000020 // 2nd Sample is End of Sequence
472 #define ADC_SSCTL0_D1 0x00000010 // 2nd Sample Differential Input
473  // Select
474 #define ADC_SSCTL0_TS0 0x00000008 // 1st Sample Temp Sensor Select
475 #define ADC_SSCTL0_IE0 0x00000004 // 1st Sample Interrupt Enable
476 #define ADC_SSCTL0_END0 0x00000002 // 1st Sample is End of Sequence
477 #define ADC_SSCTL0_D0 0x00000001 // 1st Sample Differential Input
478  // Select
479 
480 //*****************************************************************************
481 //
482 // The following are defines for the bit fields in the ADC_O_SSFIFO0 register.
483 //
484 //*****************************************************************************
485 #define ADC_SSFIFO0_DATA_M 0x00000FFF // Conversion Result Data
486 #define ADC_SSFIFO0_DATA_S 0
487 
488 //*****************************************************************************
489 //
490 // The following are defines for the bit fields in the ADC_O_SSFSTAT0 register.
491 //
492 //*****************************************************************************
493 #define ADC_SSFSTAT0_FULL 0x00001000 // FIFO Full
494 #define ADC_SSFSTAT0_EMPTY 0x00000100 // FIFO Empty
495 #define ADC_SSFSTAT0_HPTR_M 0x000000F0 // FIFO Head Pointer
496 #define ADC_SSFSTAT0_TPTR_M 0x0000000F // FIFO Tail Pointer
497 #define ADC_SSFSTAT0_HPTR_S 4
498 #define ADC_SSFSTAT0_TPTR_S 0
499 
500 //*****************************************************************************
501 //
502 // The following are defines for the bit fields in the ADC_O_SSOP0 register.
503 //
504 //*****************************************************************************
505 #define ADC_SSOP0_S7DCOP 0x10000000 // Sample 7 Digital Comparator
506  // Operation
507 #define ADC_SSOP0_S6DCOP 0x01000000 // Sample 6 Digital Comparator
508  // Operation
509 #define ADC_SSOP0_S5DCOP 0x00100000 // Sample 5 Digital Comparator
510  // Operation
511 #define ADC_SSOP0_S4DCOP 0x00010000 // Sample 4 Digital Comparator
512  // Operation
513 #define ADC_SSOP0_S3DCOP 0x00001000 // Sample 3 Digital Comparator
514  // Operation
515 #define ADC_SSOP0_S2DCOP 0x00000100 // Sample 2 Digital Comparator
516  // Operation
517 #define ADC_SSOP0_S1DCOP 0x00000010 // Sample 1 Digital Comparator
518  // Operation
519 #define ADC_SSOP0_S0DCOP 0x00000001 // Sample 0 Digital Comparator
520  // Operation
521 
522 //*****************************************************************************
523 //
524 // The following are defines for the bit fields in the ADC_O_SSDC0 register.
525 //
526 //*****************************************************************************
527 #define ADC_SSDC0_S7DCSEL_M 0xF0000000 // Sample 7 Digital Comparator
528  // Select
529 #define ADC_SSDC0_S6DCSEL_M 0x0F000000 // Sample 6 Digital Comparator
530  // Select
531 #define ADC_SSDC0_S5DCSEL_M 0x00F00000 // Sample 5 Digital Comparator
532  // Select
533 #define ADC_SSDC0_S4DCSEL_M 0x000F0000 // Sample 4 Digital Comparator
534  // Select
535 #define ADC_SSDC0_S3DCSEL_M 0x0000F000 // Sample 3 Digital Comparator
536  // Select
537 #define ADC_SSDC0_S2DCSEL_M 0x00000F00 // Sample 2 Digital Comparator
538  // Select
539 #define ADC_SSDC0_S1DCSEL_M 0x000000F0 // Sample 1 Digital Comparator
540  // Select
541 #define ADC_SSDC0_S0DCSEL_M 0x0000000F // Sample 0 Digital Comparator
542  // Select
543 #define ADC_SSDC0_S6DCSEL_S 24
544 #define ADC_SSDC0_S5DCSEL_S 20
545 #define ADC_SSDC0_S4DCSEL_S 16
546 #define ADC_SSDC0_S3DCSEL_S 12
547 #define ADC_SSDC0_S2DCSEL_S 8
548 #define ADC_SSDC0_S1DCSEL_S 4
549 #define ADC_SSDC0_S0DCSEL_S 0
550 
551 //*****************************************************************************
552 //
553 // The following are defines for the bit fields in the ADC_O_SSEMUX0 register.
554 //
555 //*****************************************************************************
556 #define ADC_SSEMUX0_EMUX7 0x10000000 // 8th Sample Input Select (Upper
557  // Bit)
558 #define ADC_SSEMUX0_EMUX6 0x01000000 // 7th Sample Input Select (Upper
559  // Bit)
560 #define ADC_SSEMUX0_EMUX5 0x00100000 // 6th Sample Input Select (Upper
561  // Bit)
562 #define ADC_SSEMUX0_EMUX4 0x00010000 // 5th Sample Input Select (Upper
563  // Bit)
564 #define ADC_SSEMUX0_EMUX3 0x00001000 // 4th Sample Input Select (Upper
565  // Bit)
566 #define ADC_SSEMUX0_EMUX2 0x00000100 // 3rd Sample Input Select (Upper
567  // Bit)
568 #define ADC_SSEMUX0_EMUX1 0x00000010 // 2th Sample Input Select (Upper
569  // Bit)
570 #define ADC_SSEMUX0_EMUX0 0x00000001 // 1st Sample Input Select (Upper
571  // Bit)
572 
573 //*****************************************************************************
574 //
575 // The following are defines for the bit fields in the ADC_O_SSTSH0 register.
576 //
577 //*****************************************************************************
578 #define ADC_SSTSH0_TSH7_M 0xF0000000 // 8th Sample and Hold Period
579  // Select
580 #define ADC_SSTSH0_TSH6_M 0x0F000000 // 7th Sample and Hold Period
581  // Select
582 #define ADC_SSTSH0_TSH5_M 0x00F00000 // 6th Sample and Hold Period
583  // Select
584 #define ADC_SSTSH0_TSH4_M 0x000F0000 // 5th Sample and Hold Period
585  // Select
586 #define ADC_SSTSH0_TSH3_M 0x0000F000 // 4th Sample and Hold Period
587  // Select
588 #define ADC_SSTSH0_TSH2_M 0x00000F00 // 3rd Sample and Hold Period
589  // Select
590 #define ADC_SSTSH0_TSH1_M 0x000000F0 // 2nd Sample and Hold Period
591  // Select
592 #define ADC_SSTSH0_TSH0_M 0x0000000F // 1st Sample and Hold Period
593  // Select
594 #define ADC_SSTSH0_TSH7_S 28
595 #define ADC_SSTSH0_TSH6_S 24
596 #define ADC_SSTSH0_TSH5_S 20
597 #define ADC_SSTSH0_TSH4_S 16
598 #define ADC_SSTSH0_TSH3_S 12
599 #define ADC_SSTSH0_TSH2_S 8
600 #define ADC_SSTSH0_TSH1_S 4
601 #define ADC_SSTSH0_TSH0_S 0
602 
603 //*****************************************************************************
604 //
605 // The following are defines for the bit fields in the ADC_O_SSMUX1 register.
606 //
607 //*****************************************************************************
608 #define ADC_SSMUX1_MUX3_M 0x0000F000 // 4th Sample Input Select
609 #define ADC_SSMUX1_MUX2_M 0x00000F00 // 3rd Sample Input Select
610 #define ADC_SSMUX1_MUX1_M 0x000000F0 // 2nd Sample Input Select
611 #define ADC_SSMUX1_MUX0_M 0x0000000F // 1st Sample Input Select
612 #define ADC_SSMUX1_MUX3_S 12
613 #define ADC_SSMUX1_MUX2_S 8
614 #define ADC_SSMUX1_MUX1_S 4
615 #define ADC_SSMUX1_MUX0_S 0
616 
617 //*****************************************************************************
618 //
619 // The following are defines for the bit fields in the ADC_O_SSCTL1 register.
620 //
621 //*****************************************************************************
622 #define ADC_SSCTL1_TS3 0x00008000 // 4th Sample Temp Sensor Select
623 #define ADC_SSCTL1_IE3 0x00004000 // 4th Sample Interrupt Enable
624 #define ADC_SSCTL1_END3 0x00002000 // 4th Sample is End of Sequence
625 #define ADC_SSCTL1_D3 0x00001000 // 4th Sample Differential Input
626  // Select
627 #define ADC_SSCTL1_TS2 0x00000800 // 3rd Sample Temp Sensor Select
628 #define ADC_SSCTL1_IE2 0x00000400 // 3rd Sample Interrupt Enable
629 #define ADC_SSCTL1_END2 0x00000200 // 3rd Sample is End of Sequence
630 #define ADC_SSCTL1_D2 0x00000100 // 3rd Sample Differential Input
631  // Select
632 #define ADC_SSCTL1_TS1 0x00000080 // 2nd Sample Temp Sensor Select
633 #define ADC_SSCTL1_IE1 0x00000040 // 2nd Sample Interrupt Enable
634 #define ADC_SSCTL1_END1 0x00000020 // 2nd Sample is End of Sequence
635 #define ADC_SSCTL1_D1 0x00000010 // 2nd Sample Differential Input
636  // Select
637 #define ADC_SSCTL1_TS0 0x00000008 // 1st Sample Temp Sensor Select
638 #define ADC_SSCTL1_IE0 0x00000004 // 1st Sample Interrupt Enable
639 #define ADC_SSCTL1_END0 0x00000002 // 1st Sample is End of Sequence
640 #define ADC_SSCTL1_D0 0x00000001 // 1st Sample Differential Input
641  // Select
642 
643 //*****************************************************************************
644 //
645 // The following are defines for the bit fields in the ADC_O_SSFIFO1 register.
646 //
647 //*****************************************************************************
648 #define ADC_SSFIFO1_DATA_M 0x00000FFF // Conversion Result Data
649 #define ADC_SSFIFO1_DATA_S 0
650 
651 //*****************************************************************************
652 //
653 // The following are defines for the bit fields in the ADC_O_SSFSTAT1 register.
654 //
655 //*****************************************************************************
656 #define ADC_SSFSTAT1_FULL 0x00001000 // FIFO Full
657 #define ADC_SSFSTAT1_EMPTY 0x00000100 // FIFO Empty
658 #define ADC_SSFSTAT1_HPTR_M 0x000000F0 // FIFO Head Pointer
659 #define ADC_SSFSTAT1_TPTR_M 0x0000000F // FIFO Tail Pointer
660 #define ADC_SSFSTAT1_HPTR_S 4
661 #define ADC_SSFSTAT1_TPTR_S 0
662 
663 //*****************************************************************************
664 //
665 // The following are defines for the bit fields in the ADC_O_SSOP1 register.
666 //
667 //*****************************************************************************
668 #define ADC_SSOP1_S3DCOP 0x00001000 // Sample 3 Digital Comparator
669  // Operation
670 #define ADC_SSOP1_S2DCOP 0x00000100 // Sample 2 Digital Comparator
671  // Operation
672 #define ADC_SSOP1_S1DCOP 0x00000010 // Sample 1 Digital Comparator
673  // Operation
674 #define ADC_SSOP1_S0DCOP 0x00000001 // Sample 0 Digital Comparator
675  // Operation
676 
677 //*****************************************************************************
678 //
679 // The following are defines for the bit fields in the ADC_O_SSDC1 register.
680 //
681 //*****************************************************************************
682 #define ADC_SSDC1_S3DCSEL_M 0x0000F000 // Sample 3 Digital Comparator
683  // Select
684 #define ADC_SSDC1_S2DCSEL_M 0x00000F00 // Sample 2 Digital Comparator
685  // Select
686 #define ADC_SSDC1_S1DCSEL_M 0x000000F0 // Sample 1 Digital Comparator
687  // Select
688 #define ADC_SSDC1_S0DCSEL_M 0x0000000F // Sample 0 Digital Comparator
689  // Select
690 #define ADC_SSDC1_S2DCSEL_S 8
691 #define ADC_SSDC1_S1DCSEL_S 4
692 #define ADC_SSDC1_S0DCSEL_S 0
693 
694 //*****************************************************************************
695 //
696 // The following are defines for the bit fields in the ADC_O_SSEMUX1 register.
697 //
698 //*****************************************************************************
699 #define ADC_SSEMUX1_EMUX3 0x00001000 // 4th Sample Input Select (Upper
700  // Bit)
701 #define ADC_SSEMUX1_EMUX2 0x00000100 // 3rd Sample Input Select (Upper
702  // Bit)
703 #define ADC_SSEMUX1_EMUX1 0x00000010 // 2th Sample Input Select (Upper
704  // Bit)
705 #define ADC_SSEMUX1_EMUX0 0x00000001 // 1st Sample Input Select (Upper
706  // Bit)
707 
708 //*****************************************************************************
709 //
710 // The following are defines for the bit fields in the ADC_O_SSTSH1 register.
711 //
712 //*****************************************************************************
713 #define ADC_SSTSH1_TSH3_M 0x0000F000 // 4th Sample and Hold Period
714  // Select
715 #define ADC_SSTSH1_TSH2_M 0x00000F00 // 3rd Sample and Hold Period
716  // Select
717 #define ADC_SSTSH1_TSH1_M 0x000000F0 // 2nd Sample and Hold Period
718  // Select
719 #define ADC_SSTSH1_TSH0_M 0x0000000F // 1st Sample and Hold Period
720  // Select
721 #define ADC_SSTSH1_TSH3_S 12
722 #define ADC_SSTSH1_TSH2_S 8
723 #define ADC_SSTSH1_TSH1_S 4
724 #define ADC_SSTSH1_TSH0_S 0
725 
726 //*****************************************************************************
727 //
728 // The following are defines for the bit fields in the ADC_O_SSMUX2 register.
729 //
730 //*****************************************************************************
731 #define ADC_SSMUX2_MUX3_M 0x0000F000 // 4th Sample Input Select
732 #define ADC_SSMUX2_MUX2_M 0x00000F00 // 3rd Sample Input Select
733 #define ADC_SSMUX2_MUX1_M 0x000000F0 // 2nd Sample Input Select
734 #define ADC_SSMUX2_MUX0_M 0x0000000F // 1st Sample Input Select
735 #define ADC_SSMUX2_MUX3_S 12
736 #define ADC_SSMUX2_MUX2_S 8
737 #define ADC_SSMUX2_MUX1_S 4
738 #define ADC_SSMUX2_MUX0_S 0
739 
740 //*****************************************************************************
741 //
742 // The following are defines for the bit fields in the ADC_O_SSCTL2 register.
743 //
744 //*****************************************************************************
745 #define ADC_SSCTL2_TS3 0x00008000 // 4th Sample Temp Sensor Select
746 #define ADC_SSCTL2_IE3 0x00004000 // 4th Sample Interrupt Enable
747 #define ADC_SSCTL2_END3 0x00002000 // 4th Sample is End of Sequence
748 #define ADC_SSCTL2_D3 0x00001000 // 4th Sample Differential Input
749  // Select
750 #define ADC_SSCTL2_TS2 0x00000800 // 3rd Sample Temp Sensor Select
751 #define ADC_SSCTL2_IE2 0x00000400 // 3rd Sample Interrupt Enable
752 #define ADC_SSCTL2_END2 0x00000200 // 3rd Sample is End of Sequence
753 #define ADC_SSCTL2_D2 0x00000100 // 3rd Sample Differential Input
754  // Select
755 #define ADC_SSCTL2_TS1 0x00000080 // 2nd Sample Temp Sensor Select
756 #define ADC_SSCTL2_IE1 0x00000040 // 2nd Sample Interrupt Enable
757 #define ADC_SSCTL2_END1 0x00000020 // 2nd Sample is End of Sequence
758 #define ADC_SSCTL2_D1 0x00000010 // 2nd Sample Differential Input
759  // Select
760 #define ADC_SSCTL2_TS0 0x00000008 // 1st Sample Temp Sensor Select
761 #define ADC_SSCTL2_IE0 0x00000004 // 1st Sample Interrupt Enable
762 #define ADC_SSCTL2_END0 0x00000002 // 1st Sample is End of Sequence
763 #define ADC_SSCTL2_D0 0x00000001 // 1st Sample Differential Input
764  // Select
765 
766 //*****************************************************************************
767 //
768 // The following are defines for the bit fields in the ADC_O_SSFIFO2 register.
769 //
770 //*****************************************************************************
771 #define ADC_SSFIFO2_DATA_M 0x00000FFF // Conversion Result Data
772 #define ADC_SSFIFO2_DATA_S 0
773 
774 //*****************************************************************************
775 //
776 // The following are defines for the bit fields in the ADC_O_SSFSTAT2 register.
777 //
778 //*****************************************************************************
779 #define ADC_SSFSTAT2_FULL 0x00001000 // FIFO Full
780 #define ADC_SSFSTAT2_EMPTY 0x00000100 // FIFO Empty
781 #define ADC_SSFSTAT2_HPTR_M 0x000000F0 // FIFO Head Pointer
782 #define ADC_SSFSTAT2_TPTR_M 0x0000000F // FIFO Tail Pointer
783 #define ADC_SSFSTAT2_HPTR_S 4
784 #define ADC_SSFSTAT2_TPTR_S 0
785 
786 //*****************************************************************************
787 //
788 // The following are defines for the bit fields in the ADC_O_SSOP2 register.
789 //
790 //*****************************************************************************
791 #define ADC_SSOP2_S3DCOP 0x00001000 // Sample 3 Digital Comparator
792  // Operation
793 #define ADC_SSOP2_S2DCOP 0x00000100 // Sample 2 Digital Comparator
794  // Operation
795 #define ADC_SSOP2_S1DCOP 0x00000010 // Sample 1 Digital Comparator
796  // Operation
797 #define ADC_SSOP2_S0DCOP 0x00000001 // Sample 0 Digital Comparator
798  // Operation
799 
800 //*****************************************************************************
801 //
802 // The following are defines for the bit fields in the ADC_O_SSDC2 register.
803 //
804 //*****************************************************************************
805 #define ADC_SSDC2_S3DCSEL_M 0x0000F000 // Sample 3 Digital Comparator
806  // Select
807 #define ADC_SSDC2_S2DCSEL_M 0x00000F00 // Sample 2 Digital Comparator
808  // Select
809 #define ADC_SSDC2_S1DCSEL_M 0x000000F0 // Sample 1 Digital Comparator
810  // Select
811 #define ADC_SSDC2_S0DCSEL_M 0x0000000F // Sample 0 Digital Comparator
812  // Select
813 #define ADC_SSDC2_S2DCSEL_S 8
814 #define ADC_SSDC2_S1DCSEL_S 4
815 #define ADC_SSDC2_S0DCSEL_S 0
816 
817 //*****************************************************************************
818 //
819 // The following are defines for the bit fields in the ADC_O_SSEMUX2 register.
820 //
821 //*****************************************************************************
822 #define ADC_SSEMUX2_EMUX3 0x00001000 // 4th Sample Input Select (Upper
823  // Bit)
824 #define ADC_SSEMUX2_EMUX2 0x00000100 // 3rd Sample Input Select (Upper
825  // Bit)
826 #define ADC_SSEMUX2_EMUX1 0x00000010 // 2th Sample Input Select (Upper
827  // Bit)
828 #define ADC_SSEMUX2_EMUX0 0x00000001 // 1st Sample Input Select (Upper
829  // Bit)
830 
831 //*****************************************************************************
832 //
833 // The following are defines for the bit fields in the ADC_O_SSTSH2 register.
834 //
835 //*****************************************************************************
836 #define ADC_SSTSH2_TSH3_M 0x0000F000 // 4th Sample and Hold Period
837  // Select
838 #define ADC_SSTSH2_TSH2_M 0x00000F00 // 3rd Sample and Hold Period
839  // Select
840 #define ADC_SSTSH2_TSH1_M 0x000000F0 // 2nd Sample and Hold Period
841  // Select
842 #define ADC_SSTSH2_TSH0_M 0x0000000F // 1st Sample and Hold Period
843  // Select
844 #define ADC_SSTSH2_TSH3_S 12
845 #define ADC_SSTSH2_TSH2_S 8
846 #define ADC_SSTSH2_TSH1_S 4
847 #define ADC_SSTSH2_TSH0_S 0
848 
849 //*****************************************************************************
850 //
851 // The following are defines for the bit fields in the ADC_O_SSMUX3 register.
852 //
853 //*****************************************************************************
854 #define ADC_SSMUX3_MUX0_M 0x0000000F // 1st Sample Input Select
855 #define ADC_SSMUX3_MUX0_S 0
856 
857 //*****************************************************************************
858 //
859 // The following are defines for the bit fields in the ADC_O_SSCTL3 register.
860 //
861 //*****************************************************************************
862 #define ADC_SSCTL3_TS0 0x00000008 // 1st Sample Temp Sensor Select
863 #define ADC_SSCTL3_IE0 0x00000004 // Sample Interrupt Enable
864 #define ADC_SSCTL3_END0 0x00000002 // End of Sequence
865 #define ADC_SSCTL3_D0 0x00000001 // Sample Differential Input Select
866 
867 //*****************************************************************************
868 //
869 // The following are defines for the bit fields in the ADC_O_SSFIFO3 register.
870 //
871 //*****************************************************************************
872 #define ADC_SSFIFO3_DATA_M 0x00000FFF // Conversion Result Data
873 #define ADC_SSFIFO3_DATA_S 0
874 
875 //*****************************************************************************
876 //
877 // The following are defines for the bit fields in the ADC_O_SSFSTAT3 register.
878 //
879 //*****************************************************************************
880 #define ADC_SSFSTAT3_FULL 0x00001000 // FIFO Full
881 #define ADC_SSFSTAT3_EMPTY 0x00000100 // FIFO Empty
882 #define ADC_SSFSTAT3_HPTR_M 0x000000F0 // FIFO Head Pointer
883 #define ADC_SSFSTAT3_TPTR_M 0x0000000F // FIFO Tail Pointer
884 #define ADC_SSFSTAT3_HPTR_S 4
885 #define ADC_SSFSTAT3_TPTR_S 0
886 
887 //*****************************************************************************
888 //
889 // The following are defines for the bit fields in the ADC_O_SSOP3 register.
890 //
891 //*****************************************************************************
892 #define ADC_SSOP3_S0DCOP 0x00000001 // Sample 0 Digital Comparator
893  // Operation
894 
895 //*****************************************************************************
896 //
897 // The following are defines for the bit fields in the ADC_O_SSDC3 register.
898 //
899 //*****************************************************************************
900 #define ADC_SSDC3_S0DCSEL_M 0x0000000F // Sample 0 Digital Comparator
901  // Select
902 
903 //*****************************************************************************
904 //
905 // The following are defines for the bit fields in the ADC_O_SSEMUX3 register.
906 //
907 //*****************************************************************************
908 #define ADC_SSEMUX3_EMUX0 0x00000001 // 1st Sample Input Select (Upper
909  // Bit)
910 
911 //*****************************************************************************
912 //
913 // The following are defines for the bit fields in the ADC_O_SSTSH3 register.
914 //
915 //*****************************************************************************
916 #define ADC_SSTSH3_TSH0_M 0x0000000F // 1st Sample and Hold Period
917  // Select
918 #define ADC_SSTSH3_TSH0_S 0
919 
920 //*****************************************************************************
921 //
922 // The following are defines for the bit fields in the ADC_O_DCRIC register.
923 //
924 //*****************************************************************************
925 #define ADC_DCRIC_DCTRIG7 0x00800000 // Digital Comparator Trigger 7
926 #define ADC_DCRIC_DCTRIG6 0x00400000 // Digital Comparator Trigger 6
927 #define ADC_DCRIC_DCTRIG5 0x00200000 // Digital Comparator Trigger 5
928 #define ADC_DCRIC_DCTRIG4 0x00100000 // Digital Comparator Trigger 4
929 #define ADC_DCRIC_DCTRIG3 0x00080000 // Digital Comparator Trigger 3
930 #define ADC_DCRIC_DCTRIG2 0x00040000 // Digital Comparator Trigger 2
931 #define ADC_DCRIC_DCTRIG1 0x00020000 // Digital Comparator Trigger 1
932 #define ADC_DCRIC_DCTRIG0 0x00010000 // Digital Comparator Trigger 0
933 #define ADC_DCRIC_DCINT7 0x00000080 // Digital Comparator Interrupt 7
934 #define ADC_DCRIC_DCINT6 0x00000040 // Digital Comparator Interrupt 6
935 #define ADC_DCRIC_DCINT5 0x00000020 // Digital Comparator Interrupt 5
936 #define ADC_DCRIC_DCINT4 0x00000010 // Digital Comparator Interrupt 4
937 #define ADC_DCRIC_DCINT3 0x00000008 // Digital Comparator Interrupt 3
938 #define ADC_DCRIC_DCINT2 0x00000004 // Digital Comparator Interrupt 2
939 #define ADC_DCRIC_DCINT1 0x00000002 // Digital Comparator Interrupt 1
940 #define ADC_DCRIC_DCINT0 0x00000001 // Digital Comparator Interrupt 0
941 
942 //*****************************************************************************
943 //
944 // The following are defines for the bit fields in the ADC_O_DCCTL0 register.
945 //
946 //*****************************************************************************
947 #define ADC_DCCTL0_CTE 0x00001000 // Comparison Trigger Enable
948 #define ADC_DCCTL0_CTC_M 0x00000C00 // Comparison Trigger Condition
949 #define ADC_DCCTL0_CTC_LOW 0x00000000 // Low Band
950 #define ADC_DCCTL0_CTC_MID 0x00000400 // Mid Band
951 #define ADC_DCCTL0_CTC_HIGH 0x00000C00 // High Band
952 #define ADC_DCCTL0_CTM_M 0x00000300 // Comparison Trigger Mode
953 #define ADC_DCCTL0_CTM_ALWAYS 0x00000000 // Always
954 #define ADC_DCCTL0_CTM_ONCE 0x00000100 // Once
955 #define ADC_DCCTL0_CTM_HALWAYS 0x00000200 // Hysteresis Always
956 #define ADC_DCCTL0_CTM_HONCE 0x00000300 // Hysteresis Once
957 #define ADC_DCCTL0_CIE 0x00000010 // Comparison Interrupt Enable
958 #define ADC_DCCTL0_CIC_M 0x0000000C // Comparison Interrupt Condition
959 #define ADC_DCCTL0_CIC_LOW 0x00000000 // Low Band
960 #define ADC_DCCTL0_CIC_MID 0x00000004 // Mid Band
961 #define ADC_DCCTL0_CIC_HIGH 0x0000000C // High Band
962 #define ADC_DCCTL0_CIM_M 0x00000003 // Comparison Interrupt Mode
963 #define ADC_DCCTL0_CIM_ALWAYS 0x00000000 // Always
964 #define ADC_DCCTL0_CIM_ONCE 0x00000001 // Once
965 #define ADC_DCCTL0_CIM_HALWAYS 0x00000002 // Hysteresis Always
966 #define ADC_DCCTL0_CIM_HONCE 0x00000003 // Hysteresis Once
967 
968 //*****************************************************************************
969 //
970 // The following are defines for the bit fields in the ADC_O_DCCTL1 register.
971 //
972 //*****************************************************************************
973 #define ADC_DCCTL1_CTE 0x00001000 // Comparison Trigger Enable
974 #define ADC_DCCTL1_CTC_M 0x00000C00 // Comparison Trigger Condition
975 #define ADC_DCCTL1_CTC_LOW 0x00000000 // Low Band
976 #define ADC_DCCTL1_CTC_MID 0x00000400 // Mid Band
977 #define ADC_DCCTL1_CTC_HIGH 0x00000C00 // High Band
978 #define ADC_DCCTL1_CTM_M 0x00000300 // Comparison Trigger Mode
979 #define ADC_DCCTL1_CTM_ALWAYS 0x00000000 // Always
980 #define ADC_DCCTL1_CTM_ONCE 0x00000100 // Once
981 #define ADC_DCCTL1_CTM_HALWAYS 0x00000200 // Hysteresis Always
982 #define ADC_DCCTL1_CTM_HONCE 0x00000300 // Hysteresis Once
983 #define ADC_DCCTL1_CIE 0x00000010 // Comparison Interrupt Enable
984 #define ADC_DCCTL1_CIC_M 0x0000000C // Comparison Interrupt Condition
985 #define ADC_DCCTL1_CIC_LOW 0x00000000 // Low Band
986 #define ADC_DCCTL1_CIC_MID 0x00000004 // Mid Band
987 #define ADC_DCCTL1_CIC_HIGH 0x0000000C // High Band
988 #define ADC_DCCTL1_CIM_M 0x00000003 // Comparison Interrupt Mode
989 #define ADC_DCCTL1_CIM_ALWAYS 0x00000000 // Always
990 #define ADC_DCCTL1_CIM_ONCE 0x00000001 // Once
991 #define ADC_DCCTL1_CIM_HALWAYS 0x00000002 // Hysteresis Always
992 #define ADC_DCCTL1_CIM_HONCE 0x00000003 // Hysteresis Once
993 
994 //*****************************************************************************
995 //
996 // The following are defines for the bit fields in the ADC_O_DCCTL2 register.
997 //
998 //*****************************************************************************
999 #define ADC_DCCTL2_CTE 0x00001000 // Comparison Trigger Enable
1000 #define ADC_DCCTL2_CTC_M 0x00000C00 // Comparison Trigger Condition
1001 #define ADC_DCCTL2_CTC_LOW 0x00000000 // Low Band
1002 #define ADC_DCCTL2_CTC_MID 0x00000400 // Mid Band
1003 #define ADC_DCCTL2_CTC_HIGH 0x00000C00 // High Band
1004 #define ADC_DCCTL2_CTM_M 0x00000300 // Comparison Trigger Mode
1005 #define ADC_DCCTL2_CTM_ALWAYS 0x00000000 // Always
1006 #define ADC_DCCTL2_CTM_ONCE 0x00000100 // Once
1007 #define ADC_DCCTL2_CTM_HALWAYS 0x00000200 // Hysteresis Always
1008 #define ADC_DCCTL2_CTM_HONCE 0x00000300 // Hysteresis Once
1009 #define ADC_DCCTL2_CIE 0x00000010 // Comparison Interrupt Enable
1010 #define ADC_DCCTL2_CIC_M 0x0000000C // Comparison Interrupt Condition
1011 #define ADC_DCCTL2_CIC_LOW 0x00000000 // Low Band
1012 #define ADC_DCCTL2_CIC_MID 0x00000004 // Mid Band
1013 #define ADC_DCCTL2_CIC_HIGH 0x0000000C // High Band
1014 #define ADC_DCCTL2_CIM_M 0x00000003 // Comparison Interrupt Mode
1015 #define ADC_DCCTL2_CIM_ALWAYS 0x00000000 // Always
1016 #define ADC_DCCTL2_CIM_ONCE 0x00000001 // Once
1017 #define ADC_DCCTL2_CIM_HALWAYS 0x00000002 // Hysteresis Always
1018 #define ADC_DCCTL2_CIM_HONCE 0x00000003 // Hysteresis Once
1019 
1020 //*****************************************************************************
1021 //
1022 // The following are defines for the bit fields in the ADC_O_DCCTL3 register.
1023 //
1024 //*****************************************************************************
1025 #define ADC_DCCTL3_CTE 0x00001000 // Comparison Trigger Enable
1026 #define ADC_DCCTL3_CTC_M 0x00000C00 // Comparison Trigger Condition
1027 #define ADC_DCCTL3_CTC_LOW 0x00000000 // Low Band
1028 #define ADC_DCCTL3_CTC_MID 0x00000400 // Mid Band
1029 #define ADC_DCCTL3_CTC_HIGH 0x00000C00 // High Band
1030 #define ADC_DCCTL3_CTM_M 0x00000300 // Comparison Trigger Mode
1031 #define ADC_DCCTL3_CTM_ALWAYS 0x00000000 // Always
1032 #define ADC_DCCTL3_CTM_ONCE 0x00000100 // Once
1033 #define ADC_DCCTL3_CTM_HALWAYS 0x00000200 // Hysteresis Always
1034 #define ADC_DCCTL3_CTM_HONCE 0x00000300 // Hysteresis Once
1035 #define ADC_DCCTL3_CIE 0x00000010 // Comparison Interrupt Enable
1036 #define ADC_DCCTL3_CIC_M 0x0000000C // Comparison Interrupt Condition
1037 #define ADC_DCCTL3_CIC_LOW 0x00000000 // Low Band
1038 #define ADC_DCCTL3_CIC_MID 0x00000004 // Mid Band
1039 #define ADC_DCCTL3_CIC_HIGH 0x0000000C // High Band
1040 #define ADC_DCCTL3_CIM_M 0x00000003 // Comparison Interrupt Mode
1041 #define ADC_DCCTL3_CIM_ALWAYS 0x00000000 // Always
1042 #define ADC_DCCTL3_CIM_ONCE 0x00000001 // Once
1043 #define ADC_DCCTL3_CIM_HALWAYS 0x00000002 // Hysteresis Always
1044 #define ADC_DCCTL3_CIM_HONCE 0x00000003 // Hysteresis Once
1045 
1046 //*****************************************************************************
1047 //
1048 // The following are defines for the bit fields in the ADC_O_DCCTL4 register.
1049 //
1050 //*****************************************************************************
1051 #define ADC_DCCTL4_CTE 0x00001000 // Comparison Trigger Enable
1052 #define ADC_DCCTL4_CTC_M 0x00000C00 // Comparison Trigger Condition
1053 #define ADC_DCCTL4_CTC_LOW 0x00000000 // Low Band
1054 #define ADC_DCCTL4_CTC_MID 0x00000400 // Mid Band
1055 #define ADC_DCCTL4_CTC_HIGH 0x00000C00 // High Band
1056 #define ADC_DCCTL4_CTM_M 0x00000300 // Comparison Trigger Mode
1057 #define ADC_DCCTL4_CTM_ALWAYS 0x00000000 // Always
1058 #define ADC_DCCTL4_CTM_ONCE 0x00000100 // Once
1059 #define ADC_DCCTL4_CTM_HALWAYS 0x00000200 // Hysteresis Always
1060 #define ADC_DCCTL4_CTM_HONCE 0x00000300 // Hysteresis Once
1061 #define ADC_DCCTL4_CIE 0x00000010 // Comparison Interrupt Enable
1062 #define ADC_DCCTL4_CIC_M 0x0000000C // Comparison Interrupt Condition
1063 #define ADC_DCCTL4_CIC_LOW 0x00000000 // Low Band
1064 #define ADC_DCCTL4_CIC_MID 0x00000004 // Mid Band
1065 #define ADC_DCCTL4_CIC_HIGH 0x0000000C // High Band
1066 #define ADC_DCCTL4_CIM_M 0x00000003 // Comparison Interrupt Mode
1067 #define ADC_DCCTL4_CIM_ALWAYS 0x00000000 // Always
1068 #define ADC_DCCTL4_CIM_ONCE 0x00000001 // Once
1069 #define ADC_DCCTL4_CIM_HALWAYS 0x00000002 // Hysteresis Always
1070 #define ADC_DCCTL4_CIM_HONCE 0x00000003 // Hysteresis Once
1071 
1072 //*****************************************************************************
1073 //
1074 // The following are defines for the bit fields in the ADC_O_DCCTL5 register.
1075 //
1076 //*****************************************************************************
1077 #define ADC_DCCTL5_CTE 0x00001000 // Comparison Trigger Enable
1078 #define ADC_DCCTL5_CTC_M 0x00000C00 // Comparison Trigger Condition
1079 #define ADC_DCCTL5_CTC_LOW 0x00000000 // Low Band
1080 #define ADC_DCCTL5_CTC_MID 0x00000400 // Mid Band
1081 #define ADC_DCCTL5_CTC_HIGH 0x00000C00 // High Band
1082 #define ADC_DCCTL5_CTM_M 0x00000300 // Comparison Trigger Mode
1083 #define ADC_DCCTL5_CTM_ALWAYS 0x00000000 // Always
1084 #define ADC_DCCTL5_CTM_ONCE 0x00000100 // Once
1085 #define ADC_DCCTL5_CTM_HALWAYS 0x00000200 // Hysteresis Always
1086 #define ADC_DCCTL5_CTM_HONCE 0x00000300 // Hysteresis Once
1087 #define ADC_DCCTL5_CIE 0x00000010 // Comparison Interrupt Enable
1088 #define ADC_DCCTL5_CIC_M 0x0000000C // Comparison Interrupt Condition
1089 #define ADC_DCCTL5_CIC_LOW 0x00000000 // Low Band
1090 #define ADC_DCCTL5_CIC_MID 0x00000004 // Mid Band
1091 #define ADC_DCCTL5_CIC_HIGH 0x0000000C // High Band
1092 #define ADC_DCCTL5_CIM_M 0x00000003 // Comparison Interrupt Mode
1093 #define ADC_DCCTL5_CIM_ALWAYS 0x00000000 // Always
1094 #define ADC_DCCTL5_CIM_ONCE 0x00000001 // Once
1095 #define ADC_DCCTL5_CIM_HALWAYS 0x00000002 // Hysteresis Always
1096 #define ADC_DCCTL5_CIM_HONCE 0x00000003 // Hysteresis Once
1097 
1098 //*****************************************************************************
1099 //
1100 // The following are defines for the bit fields in the ADC_O_DCCTL6 register.
1101 //
1102 //*****************************************************************************
1103 #define ADC_DCCTL6_CTE 0x00001000 // Comparison Trigger Enable
1104 #define ADC_DCCTL6_CTC_M 0x00000C00 // Comparison Trigger Condition
1105 #define ADC_DCCTL6_CTC_LOW 0x00000000 // Low Band
1106 #define ADC_DCCTL6_CTC_MID 0x00000400 // Mid Band
1107 #define ADC_DCCTL6_CTC_HIGH 0x00000C00 // High Band
1108 #define ADC_DCCTL6_CTM_M 0x00000300 // Comparison Trigger Mode
1109 #define ADC_DCCTL6_CTM_ALWAYS 0x00000000 // Always
1110 #define ADC_DCCTL6_CTM_ONCE 0x00000100 // Once
1111 #define ADC_DCCTL6_CTM_HALWAYS 0x00000200 // Hysteresis Always
1112 #define ADC_DCCTL6_CTM_HONCE 0x00000300 // Hysteresis Once
1113 #define ADC_DCCTL6_CIE 0x00000010 // Comparison Interrupt Enable
1114 #define ADC_DCCTL6_CIC_M 0x0000000C // Comparison Interrupt Condition
1115 #define ADC_DCCTL6_CIC_LOW 0x00000000 // Low Band
1116 #define ADC_DCCTL6_CIC_MID 0x00000004 // Mid Band
1117 #define ADC_DCCTL6_CIC_HIGH 0x0000000C // High Band
1118 #define ADC_DCCTL6_CIM_M 0x00000003 // Comparison Interrupt Mode
1119 #define ADC_DCCTL6_CIM_ALWAYS 0x00000000 // Always
1120 #define ADC_DCCTL6_CIM_ONCE 0x00000001 // Once
1121 #define ADC_DCCTL6_CIM_HALWAYS 0x00000002 // Hysteresis Always
1122 #define ADC_DCCTL6_CIM_HONCE 0x00000003 // Hysteresis Once
1123 
1124 //*****************************************************************************
1125 //
1126 // The following are defines for the bit fields in the ADC_O_DCCTL7 register.
1127 //
1128 //*****************************************************************************
1129 #define ADC_DCCTL7_CTE 0x00001000 // Comparison Trigger Enable
1130 #define ADC_DCCTL7_CTC_M 0x00000C00 // Comparison Trigger Condition
1131 #define ADC_DCCTL7_CTC_LOW 0x00000000 // Low Band
1132 #define ADC_DCCTL7_CTC_MID 0x00000400 // Mid Band
1133 #define ADC_DCCTL7_CTC_HIGH 0x00000C00 // High Band
1134 #define ADC_DCCTL7_CTM_M 0x00000300 // Comparison Trigger Mode
1135 #define ADC_DCCTL7_CTM_ALWAYS 0x00000000 // Always
1136 #define ADC_DCCTL7_CTM_ONCE 0x00000100 // Once
1137 #define ADC_DCCTL7_CTM_HALWAYS 0x00000200 // Hysteresis Always
1138 #define ADC_DCCTL7_CTM_HONCE 0x00000300 // Hysteresis Once
1139 #define ADC_DCCTL7_CIE 0x00000010 // Comparison Interrupt Enable
1140 #define ADC_DCCTL7_CIC_M 0x0000000C // Comparison Interrupt Condition
1141 #define ADC_DCCTL7_CIC_LOW 0x00000000 // Low Band
1142 #define ADC_DCCTL7_CIC_MID 0x00000004 // Mid Band
1143 #define ADC_DCCTL7_CIC_HIGH 0x0000000C // High Band
1144 #define ADC_DCCTL7_CIM_M 0x00000003 // Comparison Interrupt Mode
1145 #define ADC_DCCTL7_CIM_ALWAYS 0x00000000 // Always
1146 #define ADC_DCCTL7_CIM_ONCE 0x00000001 // Once
1147 #define ADC_DCCTL7_CIM_HALWAYS 0x00000002 // Hysteresis Always
1148 #define ADC_DCCTL7_CIM_HONCE 0x00000003 // Hysteresis Once
1149 
1150 //*****************************************************************************
1151 //
1152 // The following are defines for the bit fields in the ADC_O_DCCMP0 register.
1153 //
1154 //*****************************************************************************
1155 #define ADC_DCCMP0_COMP1_M 0x0FFF0000 // Compare 1
1156 #define ADC_DCCMP0_COMP0_M 0x00000FFF // Compare 0
1157 #define ADC_DCCMP0_COMP1_S 16
1158 #define ADC_DCCMP0_COMP0_S 0
1159 
1160 //*****************************************************************************
1161 //
1162 // The following are defines for the bit fields in the ADC_O_DCCMP1 register.
1163 //
1164 //*****************************************************************************
1165 #define ADC_DCCMP1_COMP1_M 0x0FFF0000 // Compare 1
1166 #define ADC_DCCMP1_COMP0_M 0x00000FFF // Compare 0
1167 #define ADC_DCCMP1_COMP1_S 16
1168 #define ADC_DCCMP1_COMP0_S 0
1169 
1170 //*****************************************************************************
1171 //
1172 // The following are defines for the bit fields in the ADC_O_DCCMP2 register.
1173 //
1174 //*****************************************************************************
1175 #define ADC_DCCMP2_COMP1_M 0x0FFF0000 // Compare 1
1176 #define ADC_DCCMP2_COMP0_M 0x00000FFF // Compare 0
1177 #define ADC_DCCMP2_COMP1_S 16
1178 #define ADC_DCCMP2_COMP0_S 0
1179 
1180 //*****************************************************************************
1181 //
1182 // The following are defines for the bit fields in the ADC_O_DCCMP3 register.
1183 //
1184 //*****************************************************************************
1185 #define ADC_DCCMP3_COMP1_M 0x0FFF0000 // Compare 1
1186 #define ADC_DCCMP3_COMP0_M 0x00000FFF // Compare 0
1187 #define ADC_DCCMP3_COMP1_S 16
1188 #define ADC_DCCMP3_COMP0_S 0
1189 
1190 //*****************************************************************************
1191 //
1192 // The following are defines for the bit fields in the ADC_O_DCCMP4 register.
1193 //
1194 //*****************************************************************************
1195 #define ADC_DCCMP4_COMP1_M 0x0FFF0000 // Compare 1
1196 #define ADC_DCCMP4_COMP0_M 0x00000FFF // Compare 0
1197 #define ADC_DCCMP4_COMP1_S 16
1198 #define ADC_DCCMP4_COMP0_S 0
1199 
1200 //*****************************************************************************
1201 //
1202 // The following are defines for the bit fields in the ADC_O_DCCMP5 register.
1203 //
1204 //*****************************************************************************
1205 #define ADC_DCCMP5_COMP1_M 0x0FFF0000 // Compare 1
1206 #define ADC_DCCMP5_COMP0_M 0x00000FFF // Compare 0
1207 #define ADC_DCCMP5_COMP1_S 16
1208 #define ADC_DCCMP5_COMP0_S 0
1209 
1210 //*****************************************************************************
1211 //
1212 // The following are defines for the bit fields in the ADC_O_DCCMP6 register.
1213 //
1214 //*****************************************************************************
1215 #define ADC_DCCMP6_COMP1_M 0x0FFF0000 // Compare 1
1216 #define ADC_DCCMP6_COMP0_M 0x00000FFF // Compare 0
1217 #define ADC_DCCMP6_COMP1_S 16
1218 #define ADC_DCCMP6_COMP0_S 0
1219 
1220 //*****************************************************************************
1221 //
1222 // The following are defines for the bit fields in the ADC_O_DCCMP7 register.
1223 //
1224 //*****************************************************************************
1225 #define ADC_DCCMP7_COMP1_M 0x0FFF0000 // Compare 1
1226 #define ADC_DCCMP7_COMP0_M 0x00000FFF // Compare 0
1227 #define ADC_DCCMP7_COMP1_S 16
1228 #define ADC_DCCMP7_COMP0_S 0
1229 
1230 //*****************************************************************************
1231 //
1232 // The following are defines for the bit fields in the ADC_O_PP register.
1233 //
1234 //*****************************************************************************
1235 #define ADC_PP_APSHT 0x01000000 // Application-Programmable
1236  // Sample-and-Hold Time
1237 #define ADC_PP_TS 0x00800000 // Temperature Sensor
1238 #define ADC_PP_RSL_M 0x007C0000 // Resolution
1239 #define ADC_PP_TYPE_M 0x00030000 // ADC Architecture
1240 #define ADC_PP_TYPE_SAR 0x00000000 // SAR
1241 #define ADC_PP_DC_M 0x0000FC00 // Digital Comparator Count
1242 #define ADC_PP_CH_M 0x000003F0 // ADC Channel Count
1243 #define ADC_PP_MCR_M 0x0000000F // Maximum Conversion Rate
1244 #define ADC_PP_MCR_FULL 0x00000007 // Full conversion rate (FCONV) as
1245  // defined by TADC and NSH
1246 #define ADC_PP_MSR_M 0x0000000F // Maximum ADC Sample Rate
1247 #define ADC_PP_MSR_125K 0x00000001 // 125 ksps
1248 #define ADC_PP_MSR_250K 0x00000003 // 250 ksps
1249 #define ADC_PP_MSR_500K 0x00000005 // 500 ksps
1250 #define ADC_PP_MSR_1M 0x00000007 // 1 Msps
1251 #define ADC_PP_RSL_S 18
1252 #define ADC_PP_DC_S 10
1253 #define ADC_PP_CH_S 4
1254 
1255 //*****************************************************************************
1256 //
1257 // The following are defines for the bit fields in the ADC_O_PC register.
1258 //
1259 //*****************************************************************************
1260 #define ADC_PC_SR_M 0x0000000F // ADC Sample Rate
1261 #define ADC_PC_SR_125K 0x00000001 // 125 ksps
1262 #define ADC_PC_SR_250K 0x00000003 // 250 ksps
1263 #define ADC_PC_SR_500K 0x00000005 // 500 ksps
1264 #define ADC_PC_SR_1M 0x00000007 // 1 Msps
1265 #define ADC_PC_MCR_M 0x0000000F // Conversion Rate
1266 #define ADC_PC_MCR_1_8 0x00000001 // Eighth conversion rate. After a
1267  // conversion completes, the logic
1268  // pauses for 112 TADC periods
1269  // before starting the next
1270  // conversion
1271 #define ADC_PC_MCR_1_4 0x00000003 // Quarter conversion rate. After a
1272  // conversion completes, the logic
1273  // pauses for 48 TADC periods
1274  // before starting the next
1275  // conversion
1276 #define ADC_PC_MCR_1_2 0x00000005 // Half conversion rate. After a
1277  // conversion completes, the logic
1278  // pauses for 16 TADC periods
1279  // before starting the next
1280  // conversion
1281 #define ADC_PC_MCR_FULL 0x00000007 // Full conversion rate (FCONV) as
1282  // defined by TADC and NSH
1283 
1284 //*****************************************************************************
1285 //
1286 // The following are defines for the bit fields in the ADC_O_CC register.
1287 //
1288 //*****************************************************************************
1289 #define ADC_CC_CLKDIV_M 0x000003F0 // PLL VCO Clock Divisor
1290 #define ADC_CC_CS_M 0x0000000F // ADC Clock Source
1291 #define ADC_CC_CS_SYSPLL 0x00000000 // PLL VCO divided by CLKDIV
1292 #define ADC_CC_CS_PIOSC 0x00000001 // PIOSC
1293 #define ADC_CC_CS_MOSC 0x00000002 // MOSC
1294 #define ADC_CC_CLKDIV_S 4
1295 
1296 #endif // __HW_ADC_H__
Copyright 2018, Texas Instruments Incorporated