I2CMSP432E4.h
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1 /*
2  * Copyright (c) 2017-2018, Texas Instruments Incorporated
3  * All rights reserved.
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18  * from this software without specific prior written permission.
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31  */
32 /*!****************************************************************************
33  * @file I2CMSP432E4.h
34  *
35  * @brief I2C driver implementation for a MSP432E4 I2C controller.
36  *
37  * The I2C header file should be included in an application as follows:
38  * @code
39  * #include <ti/drivers/I2C.h>
40  * #include <ti/drivers/i2c/I2CMSP432E4.h>
41  * @endcode
42  *
43  * Refer to @ref I2C.h for a complete description of APIs & example of use.
44  *
45  * ## Supported Bit Rates ##
46  * - #I2C_100kHz
47  * - #I2C_400kHz
48  * - #I2C_1000kHz
49  *
50  ******************************************************************************
51  */
52 
53 #ifndef ti_drivers_i2c_I2CMSP432E4__include
54 #define ti_drivers_i2c_I2CMSP432E4__include
55 
56 #ifdef __cplusplus
57 extern "C" {
58 #endif
59 
60 #include <stdbool.h>
61 #include <stddef.h>
62 #include <stdint.h>
63 
64 #include <ti/devices/msp432e4/inc/msp432.h>
65 
66 #include <ti/devices/msp432e4/driverlib/gpio.h>
67 #include <ti/devices/msp432e4/driverlib/pin_map.h>
68 
69 #include <ti/drivers/dpl/SemaphoreP.h>
70 #include <ti/drivers/dpl/HwiP.h>
72 #include <ti/drivers/I2C.h>
73 
84 /* Add I2CMSP432E4_STATUS_* macros here */
85 
98 /* Add I2CMSP432E4_CMD_* macros here */
99 
105 #define I2CMSP432E4_PB2_I2C0SCL GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTB, 2, GPIO_PB2_I2C0SCL)
106 
110 #define I2CMSP432E4_PB3_I2C0SDA GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTB, 3, GPIO_PB3_I2C0SDA)
111 
115 #define I2CMSP432E4_PG0_I2C1SCL GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTG, 0, GPIO_PG0_I2C1SCL)
116 
120 #define I2CMSP432E4_PR0_I2C1SCL GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTR, 0, GPIO_PR0_I2C1SCL)
121 
125 #define I2CMSP432E4_PG1_I2C1SDA GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTG, 1, GPIO_PG1_I2C1SDA)
126 
130 #define I2CMSP432E4_PR1_I2C1SDA GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTR, 1, GPIO_PR1_I2C1SDA)
131 
135 #define I2CMSP432E4_PL1_I2C2SCL GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTL, 1, GPIO_PL1_I2C2SCL)
136 
140 #define I2CMSP432E4_PP5_I2C2SCL GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTP, 5, GPIO_PP5_I2C2SCL)
141 
145 #define I2CMSP432E4_PN5_I2C2SCL GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTN, 5, GPIO_PN5_I2C2SCL)
146 
150 #define I2CMSP432E4_PG2_I2C2SCL GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTG, 2, GPIO_PG2_I2C2SCL)
151 
155 #define I2CMSP432E4_PR2_I2C2SCL GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTR, 2, GPIO_PR2_I2C2SCL)
156 
160 #define I2CMSP432E4_PL0_I2C2SDA GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTL, 0, GPIO_PL0_I2C2SDA)
161 
165 #define I2CMSP432E4_PN4_I2C2SDA GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTN, 4, GPIO_PN4_I2C2SDA)
166 
170 #define I2CMSP432E4_PP6_I2C2SDA GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTP, 6, GPIO_PP6_I2C2SDA)
171 
175 #define I2CMSP432E4_PG3_I2C2SDA GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTG, 3, GPIO_PG3_I2C2SDA)
176 
180 #define I2CMSP432E4_PR3_I2C2SDA GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTR, 3, GPIO_PR3_I2C2SDA)
181 
185 #define I2CMSP432E4_PK4_I2C3SCL GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTK, 4, GPIO_PK4_I2C3SCL)
186 
190 #define I2CMSP432E4_PG4_I2C3SCL GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTG, 4, GPIO_PG4_I2C3SCL)
191 
195 #define I2CMSP432E4_PR4_I2C3SCL GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTR, 4, GPIO_PR4_I2C3SCL)
196 
200 #define I2CMSP432E4_PK5_I2C3SDA GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTK, 5, GPIO_PK5_I2C3SDA)
201 
205 #define I2CMSP432E4_PG5_I2C3SDA GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTG, 5, GPIO_PG5_I2C3SDA)
206 
210 #define I2CMSP432E4_PR5_I2C3SDA GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTR, 5, GPIO_PR5_I2C3SDA)
211 
215 #define I2CMSP432E4_PK6_I2C4SCL GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTK, 6, GPIO_PK6_I2C4SCL)
216 
220 #define I2CMSP432E4_PG6_I2C4SCL GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTG, 6, GPIO_PG6_I2C4SCL)
221 
225 #define I2CMSP432E4_PR6_I2C4SCL GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTR, 6, GPIO_PR6_I2C4SCL)
226 
230 #define I2CMSP432E4_PK7_I2C4SDA GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTK, 7, GPIO_PK7_I2C4SDA)
231 
235 #define I2CMSP432E4_PG7_I2C4SDA GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTG, 7, GPIO_PG7_I2C4SDA)
236 
240 #define I2CMSP432E4_PR7_I2C4SDA GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTR, 7, GPIO_PR7_I2C4SDA)
241 
245 #define I2CMSP432E4_PB0_I2C5SCL GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTB, 0, GPIO_PB0_I2C5SCL)
246 
250 #define I2CMSP432E4_PB4_I2C5SCL GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTB, 4, GPIO_PB4_I2C5SCL)
251 
255 #define I2CMSP432E4_PB1_I2C5SDA GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTB, 1, GPIO_PB1_I2C5SDA)
256 
260 #define I2CMSP432E4_PB5_I2C5SDA GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTB, 5, GPIO_PB5_I2C5SDA)
261 
265 #define I2CMSP432E4_PA6_I2C6SCL GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTA, 6, GPIO_PA6_I2C6SCL)
266 
270 #define I2CMSP432E4_PB6_I2C6SCL GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTB, 6, GPIO_PB6_I2C6SCL)
271 
275 #define I2CMSP432E4_PA7_I2C6SDA GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTA, 7, GPIO_PA7_I2C6SDA)
276 
280 #define I2CMSP432E4_PB7_I2C6SDA GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTB, 7, GPIO_PB7_I2C6SDA)
281 
285 #define I2CMSP432E4_PD0_I2C7SCL GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTD, 0, GPIO_PD0_I2C7SCL)
286 
290 #define I2CMSP432E4_PA4_I2C7SCL GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTA, 4, GPIO_PA4_I2C7SCL)
291 
295 #define I2CMSP432E4_PD1_I2C7SDA GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTD, 1, GPIO_PD1_I2C7SDA)
296 
300 #define I2CMSP432E4_PA5_I2C7SDA GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTA, 5, GPIO_PA5_I2C7SDA)
301 
305 #define I2CMSP432E4_PD2_I2C8SCL GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTD, 2, GPIO_PD2_I2C8SCL)
306 
310 #define I2CMSP432E4_PA2_I2C8SCL GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTA, 2, GPIO_PA2_I2C8SCL)
311 
315 #define I2CMSP432E4_PD3_I2C8SDA GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTD, 3, GPIO_PD3_I2C8SDA)
316 
320 #define I2CMSP432E4_PA3_I2C8SDA GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTA, 3, GPIO_PA3_I2C8SDA)
321 
325 #define I2CMSP432E4_PA0_I2C9SCL GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTA, 0, GPIO_PA0_I2C9SCL)
326 
330 #define I2CMSP432E4_PE6_I2C9SCL GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTE, 6, GPIO_PE6_I2C9SCL)
331 
335 #define I2CMSP432E4_PA1_I2C9SDA GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTA, 1, GPIO_PA1_I2C9SDA)
336 
340 #define I2CMSP432E4_PE7_I2C9SDA GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTE, 7, GPIO_PE7_I2C9SDA)
341 
342 
343 /* I2C function table pointer */
345 
352 typedef enum I2CMSP432E4_Mode {
353  I2CMSP432E4_IDLE_MODE = 0, /* I2C is not performing a transaction */
354  I2CMSP432E4_WRITE_MODE, /* I2C is currently performing write operations */
355  I2CMSP432E4_READ_MODE, /* I2C is currently performing read operations */
356  I2CMSP432E4_ERROR = 0xFF /* I2C error has occurred, exit gracefully */
358 
397 typedef struct I2CMSP432E4_HWAttrs_ {
399  uint32_t baseAddr;
401  uint32_t intNum;
403  uint32_t intPriority;
405  uint32_t sclPin;
407  uint32_t sdaPin;
409 
415 typedef struct I2CMSP432E4_Object_ {
416  /* Grants exclusive access to I2C */
417  SemaphoreP_Handle mutex;
418 
419  /* Notify finished I2C transfer */
420  SemaphoreP_Handle transferComplete;
421 
422  /* Hardware interrupt handle */
423  HwiP_Handle hwiHandle;
424 
425  /* Blocking or Callback mode */
427 
428  /* Application callback function pointer */
430 
431  /* Stores the I2C object state */
433 
434  /* Pointer to current I2C transaction */
436 
437  /* Head and tail pointers for queued transactions in I2C_MODE_CALLBACK */
440 
441  /* Enumerated bit rate */
442  uint8_t bitRate;
443 
444  uint8_t *writeBufIdx; /* Internal increment writeBuf index */
445  size_t writeCountIdx; /* Internal decrement writeCounter */
446  uint8_t *readBufIdx; /* Internal increment readBuf index */
447  size_t readCountIdx; /* Internal decrement readCounter */
448  bool isOpen; /* Flag to indicate module is open */
450 
451 #ifdef __cplusplus
452 }
453 #endif
454 
455 #endif /* ti_drivers_i2c_I2CMSP432E4__include */
size_t writeCountIdx
Definition: I2CMSP432E4.h:445
I2CMSP432E4 Hardware attributes.
Definition: I2CMSP432E4.h:397
volatile I2CMSP432E4_Mode mode
Definition: I2CMSP432E4.h:432
I2CMSP432E4 Object.
Definition: I2CMSP432E4.h:415
This structure defines the I2C slave address, pointers to write and read buffers, and their associate...
Definition: I2C.h:411
uint32_t intNum
Definition: I2CMSP432E4.h:401
I2C_Transaction * tailPtr
Definition: I2CMSP432E4.h:439
uint32_t intPriority
Definition: I2CMSP432E4.h:403
I2C_TransferMode transferMode
Definition: I2CMSP432E4.h:426
uint32_t sdaPin
Definition: I2CMSP432E4.h:407
enum I2C_TransferMode_ I2C_TransferMode
This I2C driver supports two transfer modes of operation: blocking and callback. The transfer mode is...
uint8_t bitRate
Definition: I2CMSP432E4.h:442
I2CMSP432E4_Mode
I2CMSP432E4 mode.
Definition: I2CMSP432E4.h:352
Definition: I2CMSP432E4.h:356
Definition: I2CMSP432E4.h:355
bool isOpen
Definition: I2CMSP432E4.h:448
const I2C_FxnTable I2CMSP432E4_fxnTable
The definition of an I2C function table that contains the required set of functions to control a spec...
Definition: I2C.h:552
uint32_t baseAddr
Definition: I2CMSP432E4.h:399
struct I2CMSP432E4_Object_ I2CMSP432E4_Object
I2CMSP432E4 Object.
MSP432E4 GPIO driver.
uint8_t * writeBufIdx
Definition: I2CMSP432E4.h:444
SemaphoreP_Handle mutex
Definition: I2CMSP432E4.h:417
I2C_CallbackFxn transferCallbackFxn
Definition: I2CMSP432E4.h:429
uint8_t * readBufIdx
Definition: I2CMSP432E4.h:446
struct I2CMSP432E4_HWAttrs_ I2CMSP432E4_HWAttrs
I2CMSP432E4 Hardware attributes.
size_t readCountIdx
Definition: I2CMSP432E4.h:447
SemaphoreP_Handle transferComplete
Definition: I2CMSP432E4.h:420
void(* I2C_CallbackFxn)(I2C_Handle handle, I2C_Transaction *transaction, bool transferStatus)
I2C callback function prototype. The application is responsible for declaring a callback function whe...
Definition: I2C.h:475
HwiP_Handle hwiHandle
Definition: I2CMSP432E4.h:423
I2C_Transaction * currentTransaction
Definition: I2CMSP432E4.h:435
uint32_t sclPin
Definition: I2CMSP432E4.h:405
I2C_Transaction * headPtr
Definition: I2CMSP432E4.h:438
Inter-Intergrated Circuit driver interface.
Definition: I2CMSP432E4.h:354
Definition: I2CMSP432E4.h:353
Copyright 2018, Texas Instruments Incorporated