hw_watchdog.h
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1 //*****************************************************************************
2 //
3 // hw_watchdog.h - Macros used when accessing the Watchdog Timer hardware.
4 //
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36 //*****************************************************************************
37 
38 #ifndef __HW_WATCHDOG_H__
39 #define __HW_WATCHDOG_H__
40 
41 //*****************************************************************************
42 //
43 // The following are defines for the Watchdog Timer register offsets.
44 //
45 //*****************************************************************************
46 #define WDT_O_LOAD 0x00000000 // Watchdog Load
47 #define WDT_O_VALUE 0x00000004 // Watchdog Value
48 #define WDT_O_CTL 0x00000008 // Watchdog Control
49 #define WDT_O_ICR 0x0000000C // Watchdog Interrupt Clear
50 #define WDT_O_RIS 0x00000010 // Watchdog Raw Interrupt Status
51 #define WDT_O_MIS 0x00000014 // Watchdog Masked Interrupt Status
52 #define WDT_O_TEST 0x00000418 // Watchdog Test
53 #define WDT_O_LOCK 0x00000C00 // Watchdog Lock
54 
55 //*****************************************************************************
56 //
57 // The following are defines for the bit fields in the WDT_O_LOAD register.
58 //
59 //*****************************************************************************
60 #define WDT_LOAD_M 0xFFFFFFFF // Watchdog Load Value
61 #define WDT_LOAD_S 0
62 
63 //*****************************************************************************
64 //
65 // The following are defines for the bit fields in the WDT_O_VALUE register.
66 //
67 //*****************************************************************************
68 #define WDT_VALUE_M 0xFFFFFFFF // Watchdog Value
69 #define WDT_VALUE_S 0
70 
71 //*****************************************************************************
72 //
73 // The following are defines for the bit fields in the WDT_O_CTL register.
74 //
75 //*****************************************************************************
76 #define WDT_CTL_WRC 0x80000000 // Write Complete
77 #define WDT_CTL_INTTYPE 0x00000004 // Watchdog Interrupt Type
78 #define WDT_CTL_RESEN 0x00000002 // Watchdog Reset Enable
79 #define WDT_CTL_INTEN 0x00000001 // Watchdog Interrupt Enable
80 
81 //*****************************************************************************
82 //
83 // The following are defines for the bit fields in the WDT_O_ICR register.
84 //
85 //*****************************************************************************
86 #define WDT_ICR_M 0xFFFFFFFF // Watchdog Interrupt Clear
87 #define WDT_ICR_S 0
88 
89 //*****************************************************************************
90 //
91 // The following are defines for the bit fields in the WDT_O_RIS register.
92 //
93 //*****************************************************************************
94 #define WDT_RIS_WDTRIS 0x00000001 // Watchdog Raw Interrupt Status
95 
96 //*****************************************************************************
97 //
98 // The following are defines for the bit fields in the WDT_O_MIS register.
99 //
100 //*****************************************************************************
101 #define WDT_MIS_WDTMIS 0x00000001 // Watchdog Masked Interrupt Status
102 
103 //*****************************************************************************
104 //
105 // The following are defines for the bit fields in the WDT_O_TEST register.
106 //
107 //*****************************************************************************
108 #define WDT_TEST_STALL 0x00000100 // Watchdog Stall Enable
109 
110 //*****************************************************************************
111 //
112 // The following are defines for the bit fields in the WDT_O_LOCK register.
113 //
114 //*****************************************************************************
115 #define WDT_LOCK_M 0xFFFFFFFF // Watchdog Lock
116 #define WDT_LOCK_UNLOCKED 0x00000000 // Unlocked
117 #define WDT_LOCK_LOCKED 0x00000001 // Locked
118 #define WDT_LOCK_UNLOCK 0x1ACCE551 // Unlocks the watchdog timer
119 
120 #endif // __HW_WATCHDOG_H__
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