hw_usb.h
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1 //*****************************************************************************
2 //
3 // hw_usb.h - Macros for use in accessing the USB registers.
4 //
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37 
38 #ifndef __HW_USB_H__
39 #define __HW_USB_H__
40 
41 //*****************************************************************************
42 //
43 // The following are defines for the Univeral Serial Bus register offsets.
44 //
45 //*****************************************************************************
46 #define USB_O_FADDR 0x00000000 // USB Device Functional Address
47 #define USB_O_POWER 0x00000001 // USB Power
48 #define USB_O_TXIS 0x00000002 // USB Transmit Interrupt Status
49 #define USB_O_RXIS 0x00000004 // USB Receive Interrupt Status
50 #define USB_O_TXIE 0x00000006 // USB Transmit Interrupt Enable
51 #define USB_O_RXIE 0x00000008 // USB Receive Interrupt Enable
52 #define USB_O_IS 0x0000000A // USB General Interrupt Status
53 #define USB_O_IE 0x0000000B // USB Interrupt Enable
54 #define USB_O_FRAME 0x0000000C // USB Frame Value
55 #define USB_O_EPIDX 0x0000000E // USB Endpoint Index
56 #define USB_O_TEST 0x0000000F // USB Test Mode
57 #define USB_O_FIFO0 0x00000020 // USB FIFO Endpoint 0
58 #define USB_O_FIFO1 0x00000024 // USB FIFO Endpoint 1
59 #define USB_O_FIFO2 0x00000028 // USB FIFO Endpoint 2
60 #define USB_O_FIFO3 0x0000002C // USB FIFO Endpoint 3
61 #define USB_O_FIFO4 0x00000030 // USB FIFO Endpoint 4
62 #define USB_O_FIFO5 0x00000034 // USB FIFO Endpoint 5
63 #define USB_O_FIFO6 0x00000038 // USB FIFO Endpoint 6
64 #define USB_O_FIFO7 0x0000003C // USB FIFO Endpoint 7
65 #define USB_O_DEVCTL 0x00000060 // USB Device Control
66 #define USB_O_CCONF 0x00000061 // USB Common Configuration
67 #define USB_O_TXFIFOSZ 0x00000062 // USB Transmit Dynamic FIFO Sizing
68 #define USB_O_RXFIFOSZ 0x00000063 // USB Receive Dynamic FIFO Sizing
69 #define USB_O_TXFIFOADD 0x00000064 // USB Transmit FIFO Start Address
70 #define USB_O_RXFIFOADD 0x00000066 // USB Receive FIFO Start Address
71 #define USB_O_ULPIVBUSCTL 0x00000070 // USB ULPI VBUS Control
72 #define USB_O_ULPIREGDATA 0x00000074 // USB ULPI Register Data
73 #define USB_O_ULPIREGADDR 0x00000075 // USB ULPI Register Address
74 #define USB_O_ULPIREGCTL 0x00000076 // USB ULPI Register Control
75 #define USB_O_EPINFO 0x00000078 // USB Endpoint Information
76 #define USB_O_RAMINFO 0x00000079 // USB RAM Information
77 #define USB_O_CONTIM 0x0000007A // USB Connect Timing
78 #define USB_O_VPLEN 0x0000007B // USB OTG VBUS Pulse Timing
79 #define USB_O_HSEOF 0x0000007C // USB High-Speed Last Transaction
80  // to End of Frame Timing
81 #define USB_O_FSEOF 0x0000007D // USB Full-Speed Last Transaction
82  // to End of Frame Timing
83 #define USB_O_LSEOF 0x0000007E // USB Low-Speed Last Transaction
84  // to End of Frame Timing
85 #define USB_O_TXFUNCADDR0 0x00000080 // USB Transmit Functional Address
86  // Endpoint 0
87 #define USB_O_TXHUBADDR0 0x00000082 // USB Transmit Hub Address
88  // Endpoint 0
89 #define USB_O_TXHUBPORT0 0x00000083 // USB Transmit Hub Port Endpoint 0
90 #define USB_O_TXFUNCADDR1 0x00000088 // USB Transmit Functional Address
91  // Endpoint 1
92 #define USB_O_TXHUBADDR1 0x0000008A // USB Transmit Hub Address
93  // Endpoint 1
94 #define USB_O_TXHUBPORT1 0x0000008B // USB Transmit Hub Port Endpoint 1
95 #define USB_O_RXFUNCADDR1 0x0000008C // USB Receive Functional Address
96  // Endpoint 1
97 #define USB_O_RXHUBADDR1 0x0000008E // USB Receive Hub Address Endpoint
98  // 1
99 #define USB_O_RXHUBPORT1 0x0000008F // USB Receive Hub Port Endpoint 1
100 #define USB_O_TXFUNCADDR2 0x00000090 // USB Transmit Functional Address
101  // Endpoint 2
102 #define USB_O_TXHUBADDR2 0x00000092 // USB Transmit Hub Address
103  // Endpoint 2
104 #define USB_O_TXHUBPORT2 0x00000093 // USB Transmit Hub Port Endpoint 2
105 #define USB_O_RXFUNCADDR2 0x00000094 // USB Receive Functional Address
106  // Endpoint 2
107 #define USB_O_RXHUBADDR2 0x00000096 // USB Receive Hub Address Endpoint
108  // 2
109 #define USB_O_RXHUBPORT2 0x00000097 // USB Receive Hub Port Endpoint 2
110 #define USB_O_TXFUNCADDR3 0x00000098 // USB Transmit Functional Address
111  // Endpoint 3
112 #define USB_O_TXHUBADDR3 0x0000009A // USB Transmit Hub Address
113  // Endpoint 3
114 #define USB_O_TXHUBPORT3 0x0000009B // USB Transmit Hub Port Endpoint 3
115 #define USB_O_RXFUNCADDR3 0x0000009C // USB Receive Functional Address
116  // Endpoint 3
117 #define USB_O_RXHUBADDR3 0x0000009E // USB Receive Hub Address Endpoint
118  // 3
119 #define USB_O_RXHUBPORT3 0x0000009F // USB Receive Hub Port Endpoint 3
120 #define USB_O_TXFUNCADDR4 0x000000A0 // USB Transmit Functional Address
121  // Endpoint 4
122 #define USB_O_TXHUBADDR4 0x000000A2 // USB Transmit Hub Address
123  // Endpoint 4
124 #define USB_O_TXHUBPORT4 0x000000A3 // USB Transmit Hub Port Endpoint 4
125 #define USB_O_RXFUNCADDR4 0x000000A4 // USB Receive Functional Address
126  // Endpoint 4
127 #define USB_O_RXHUBADDR4 0x000000A6 // USB Receive Hub Address Endpoint
128  // 4
129 #define USB_O_RXHUBPORT4 0x000000A7 // USB Receive Hub Port Endpoint 4
130 #define USB_O_TXFUNCADDR5 0x000000A8 // USB Transmit Functional Address
131  // Endpoint 5
132 #define USB_O_TXHUBADDR5 0x000000AA // USB Transmit Hub Address
133  // Endpoint 5
134 #define USB_O_TXHUBPORT5 0x000000AB // USB Transmit Hub Port Endpoint 5
135 #define USB_O_RXFUNCADDR5 0x000000AC // USB Receive Functional Address
136  // Endpoint 5
137 #define USB_O_RXHUBADDR5 0x000000AE // USB Receive Hub Address Endpoint
138  // 5
139 #define USB_O_RXHUBPORT5 0x000000AF // USB Receive Hub Port Endpoint 5
140 #define USB_O_TXFUNCADDR6 0x000000B0 // USB Transmit Functional Address
141  // Endpoint 6
142 #define USB_O_TXHUBADDR6 0x000000B2 // USB Transmit Hub Address
143  // Endpoint 6
144 #define USB_O_TXHUBPORT6 0x000000B3 // USB Transmit Hub Port Endpoint 6
145 #define USB_O_RXFUNCADDR6 0x000000B4 // USB Receive Functional Address
146  // Endpoint 6
147 #define USB_O_RXHUBADDR6 0x000000B6 // USB Receive Hub Address Endpoint
148  // 6
149 #define USB_O_RXHUBPORT6 0x000000B7 // USB Receive Hub Port Endpoint 6
150 #define USB_O_TXFUNCADDR7 0x000000B8 // USB Transmit Functional Address
151  // Endpoint 7
152 #define USB_O_TXHUBADDR7 0x000000BA // USB Transmit Hub Address
153  // Endpoint 7
154 #define USB_O_TXHUBPORT7 0x000000BB // USB Transmit Hub Port Endpoint 7
155 #define USB_O_RXFUNCADDR7 0x000000BC // USB Receive Functional Address
156  // Endpoint 7
157 #define USB_O_RXHUBADDR7 0x000000BE // USB Receive Hub Address Endpoint
158  // 7
159 #define USB_O_RXHUBPORT7 0x000000BF // USB Receive Hub Port Endpoint 7
160 #define USB_O_CSRL0 0x00000102 // USB Control and Status Endpoint
161  // 0 Low
162 #define USB_O_CSRH0 0x00000103 // USB Control and Status Endpoint
163  // 0 High
164 #define USB_O_COUNT0 0x00000108 // USB Receive Byte Count Endpoint
165  // 0
166 #define USB_O_TYPE0 0x0000010A // USB Type Endpoint 0
167 #define USB_O_NAKLMT 0x0000010B // USB NAK Limit
168 #define USB_O_TXMAXP1 0x00000110 // USB Maximum Transmit Data
169  // Endpoint 1
170 #define USB_O_TXCSRL1 0x00000112 // USB Transmit Control and Status
171  // Endpoint 1 Low
172 #define USB_O_TXCSRH1 0x00000113 // USB Transmit Control and Status
173  // Endpoint 1 High
174 #define USB_O_RXMAXP1 0x00000114 // USB Maximum Receive Data
175  // Endpoint 1
176 #define USB_O_RXCSRL1 0x00000116 // USB Receive Control and Status
177  // Endpoint 1 Low
178 #define USB_O_RXCSRH1 0x00000117 // USB Receive Control and Status
179  // Endpoint 1 High
180 #define USB_O_RXCOUNT1 0x00000118 // USB Receive Byte Count Endpoint
181  // 1
182 #define USB_O_TXTYPE1 0x0000011A // USB Host Transmit Configure Type
183  // Endpoint 1
184 #define USB_O_TXINTERVAL1 0x0000011B // USB Host Transmit Interval
185  // Endpoint 1
186 #define USB_O_RXTYPE1 0x0000011C // USB Host Configure Receive Type
187  // Endpoint 1
188 #define USB_O_RXINTERVAL1 0x0000011D // USB Host Receive Polling
189  // Interval Endpoint 1
190 #define USB_O_TXMAXP2 0x00000120 // USB Maximum Transmit Data
191  // Endpoint 2
192 #define USB_O_TXCSRL2 0x00000122 // USB Transmit Control and Status
193  // Endpoint 2 Low
194 #define USB_O_TXCSRH2 0x00000123 // USB Transmit Control and Status
195  // Endpoint 2 High
196 #define USB_O_RXMAXP2 0x00000124 // USB Maximum Receive Data
197  // Endpoint 2
198 #define USB_O_RXCSRL2 0x00000126 // USB Receive Control and Status
199  // Endpoint 2 Low
200 #define USB_O_RXCSRH2 0x00000127 // USB Receive Control and Status
201  // Endpoint 2 High
202 #define USB_O_RXCOUNT2 0x00000128 // USB Receive Byte Count Endpoint
203  // 2
204 #define USB_O_TXTYPE2 0x0000012A // USB Host Transmit Configure Type
205  // Endpoint 2
206 #define USB_O_TXINTERVAL2 0x0000012B // USB Host Transmit Interval
207  // Endpoint 2
208 #define USB_O_RXTYPE2 0x0000012C // USB Host Configure Receive Type
209  // Endpoint 2
210 #define USB_O_RXINTERVAL2 0x0000012D // USB Host Receive Polling
211  // Interval Endpoint 2
212 #define USB_O_TXMAXP3 0x00000130 // USB Maximum Transmit Data
213  // Endpoint 3
214 #define USB_O_TXCSRL3 0x00000132 // USB Transmit Control and Status
215  // Endpoint 3 Low
216 #define USB_O_TXCSRH3 0x00000133 // USB Transmit Control and Status
217  // Endpoint 3 High
218 #define USB_O_RXMAXP3 0x00000134 // USB Maximum Receive Data
219  // Endpoint 3
220 #define USB_O_RXCSRL3 0x00000136 // USB Receive Control and Status
221  // Endpoint 3 Low
222 #define USB_O_RXCSRH3 0x00000137 // USB Receive Control and Status
223  // Endpoint 3 High
224 #define USB_O_RXCOUNT3 0x00000138 // USB Receive Byte Count Endpoint
225  // 3
226 #define USB_O_TXTYPE3 0x0000013A // USB Host Transmit Configure Type
227  // Endpoint 3
228 #define USB_O_TXINTERVAL3 0x0000013B // USB Host Transmit Interval
229  // Endpoint 3
230 #define USB_O_RXTYPE3 0x0000013C // USB Host Configure Receive Type
231  // Endpoint 3
232 #define USB_O_RXINTERVAL3 0x0000013D // USB Host Receive Polling
233  // Interval Endpoint 3
234 #define USB_O_TXMAXP4 0x00000140 // USB Maximum Transmit Data
235  // Endpoint 4
236 #define USB_O_TXCSRL4 0x00000142 // USB Transmit Control and Status
237  // Endpoint 4 Low
238 #define USB_O_TXCSRH4 0x00000143 // USB Transmit Control and Status
239  // Endpoint 4 High
240 #define USB_O_RXMAXP4 0x00000144 // USB Maximum Receive Data
241  // Endpoint 4
242 #define USB_O_RXCSRL4 0x00000146 // USB Receive Control and Status
243  // Endpoint 4 Low
244 #define USB_O_RXCSRH4 0x00000147 // USB Receive Control and Status
245  // Endpoint 4 High
246 #define USB_O_RXCOUNT4 0x00000148 // USB Receive Byte Count Endpoint
247  // 4
248 #define USB_O_TXTYPE4 0x0000014A // USB Host Transmit Configure Type
249  // Endpoint 4
250 #define USB_O_TXINTERVAL4 0x0000014B // USB Host Transmit Interval
251  // Endpoint 4
252 #define USB_O_RXTYPE4 0x0000014C // USB Host Configure Receive Type
253  // Endpoint 4
254 #define USB_O_RXINTERVAL4 0x0000014D // USB Host Receive Polling
255  // Interval Endpoint 4
256 #define USB_O_TXMAXP5 0x00000150 // USB Maximum Transmit Data
257  // Endpoint 5
258 #define USB_O_TXCSRL5 0x00000152 // USB Transmit Control and Status
259  // Endpoint 5 Low
260 #define USB_O_TXCSRH5 0x00000153 // USB Transmit Control and Status
261  // Endpoint 5 High
262 #define USB_O_RXMAXP5 0x00000154 // USB Maximum Receive Data
263  // Endpoint 5
264 #define USB_O_RXCSRL5 0x00000156 // USB Receive Control and Status
265  // Endpoint 5 Low
266 #define USB_O_RXCSRH5 0x00000157 // USB Receive Control and Status
267  // Endpoint 5 High
268 #define USB_O_RXCOUNT5 0x00000158 // USB Receive Byte Count Endpoint
269  // 5
270 #define USB_O_TXTYPE5 0x0000015A // USB Host Transmit Configure Type
271  // Endpoint 5
272 #define USB_O_TXINTERVAL5 0x0000015B // USB Host Transmit Interval
273  // Endpoint 5
274 #define USB_O_RXTYPE5 0x0000015C // USB Host Configure Receive Type
275  // Endpoint 5
276 #define USB_O_RXINTERVAL5 0x0000015D // USB Host Receive Polling
277  // Interval Endpoint 5
278 #define USB_O_TXMAXP6 0x00000160 // USB Maximum Transmit Data
279  // Endpoint 6
280 #define USB_O_TXCSRL6 0x00000162 // USB Transmit Control and Status
281  // Endpoint 6 Low
282 #define USB_O_TXCSRH6 0x00000163 // USB Transmit Control and Status
283  // Endpoint 6 High
284 #define USB_O_RXMAXP6 0x00000164 // USB Maximum Receive Data
285  // Endpoint 6
286 #define USB_O_RXCSRL6 0x00000166 // USB Receive Control and Status
287  // Endpoint 6 Low
288 #define USB_O_RXCSRH6 0x00000167 // USB Receive Control and Status
289  // Endpoint 6 High
290 #define USB_O_RXCOUNT6 0x00000168 // USB Receive Byte Count Endpoint
291  // 6
292 #define USB_O_TXTYPE6 0x0000016A // USB Host Transmit Configure Type
293  // Endpoint 6
294 #define USB_O_TXINTERVAL6 0x0000016B // USB Host Transmit Interval
295  // Endpoint 6
296 #define USB_O_RXTYPE6 0x0000016C // USB Host Configure Receive Type
297  // Endpoint 6
298 #define USB_O_RXINTERVAL6 0x0000016D // USB Host Receive Polling
299  // Interval Endpoint 6
300 #define USB_O_TXMAXP7 0x00000170 // USB Maximum Transmit Data
301  // Endpoint 7
302 #define USB_O_TXCSRL7 0x00000172 // USB Transmit Control and Status
303  // Endpoint 7 Low
304 #define USB_O_TXCSRH7 0x00000173 // USB Transmit Control and Status
305  // Endpoint 7 High
306 #define USB_O_RXMAXP7 0x00000174 // USB Maximum Receive Data
307  // Endpoint 7
308 #define USB_O_RXCSRL7 0x00000176 // USB Receive Control and Status
309  // Endpoint 7 Low
310 #define USB_O_RXCSRH7 0x00000177 // USB Receive Control and Status
311  // Endpoint 7 High
312 #define USB_O_RXCOUNT7 0x00000178 // USB Receive Byte Count Endpoint
313  // 7
314 #define USB_O_TXTYPE7 0x0000017A // USB Host Transmit Configure Type
315  // Endpoint 7
316 #define USB_O_TXINTERVAL7 0x0000017B // USB Host Transmit Interval
317  // Endpoint 7
318 #define USB_O_RXTYPE7 0x0000017C // USB Host Configure Receive Type
319  // Endpoint 7
320 #define USB_O_RXINTERVAL7 0x0000017D // USB Host Receive Polling
321  // Interval Endpoint 7
322 #define USB_O_DMAINTR 0x00000200 // USB DMA Interrupt
323 #define USB_O_DMACTL0 0x00000204 // USB DMA Control 0
324 #define USB_O_DMAADDR0 0x00000208 // USB DMA Address 0
325 #define USB_O_DMACOUNT0 0x0000020C // USB DMA Count 0
326 #define USB_O_DMACTL1 0x00000214 // USB DMA Control 1
327 #define USB_O_DMAADDR1 0x00000218 // USB DMA Address 1
328 #define USB_O_DMACOUNT1 0x0000021C // USB DMA Count 1
329 #define USB_O_DMACTL2 0x00000224 // USB DMA Control 2
330 #define USB_O_DMAADDR2 0x00000228 // USB DMA Address 2
331 #define USB_O_DMACOUNT2 0x0000022C // USB DMA Count 2
332 #define USB_O_DMACTL3 0x00000234 // USB DMA Control 3
333 #define USB_O_DMAADDR3 0x00000238 // USB DMA Address 3
334 #define USB_O_DMACOUNT3 0x0000023C // USB DMA Count 3
335 #define USB_O_DMACTL4 0x00000244 // USB DMA Control 4
336 #define USB_O_DMAADDR4 0x00000248 // USB DMA Address 4
337 #define USB_O_DMACOUNT4 0x0000024C // USB DMA Count 4
338 #define USB_O_DMACTL5 0x00000254 // USB DMA Control 5
339 #define USB_O_DMAADDR5 0x00000258 // USB DMA Address 5
340 #define USB_O_DMACOUNT5 0x0000025C // USB DMA Count 5
341 #define USB_O_DMACTL6 0x00000264 // USB DMA Control 6
342 #define USB_O_DMAADDR6 0x00000268 // USB DMA Address 6
343 #define USB_O_DMACOUNT6 0x0000026C // USB DMA Count 6
344 #define USB_O_DMACTL7 0x00000274 // USB DMA Control 7
345 #define USB_O_DMAADDR7 0x00000278 // USB DMA Address 7
346 #define USB_O_DMACOUNT7 0x0000027C // USB DMA Count 7
347 #define USB_O_RQPKTCOUNT1 0x00000304 // USB Request Packet Count in
348  // Block Transfer Endpoint 1
349 #define USB_O_RQPKTCOUNT2 0x00000308 // USB Request Packet Count in
350  // Block Transfer Endpoint 2
351 #define USB_O_RQPKTCOUNT3 0x0000030C // USB Request Packet Count in
352  // Block Transfer Endpoint 3
353 #define USB_O_RQPKTCOUNT4 0x00000310 // USB Request Packet Count in
354  // Block Transfer Endpoint 4
355 #define USB_O_RQPKTCOUNT5 0x00000314 // USB Request Packet Count in
356  // Block Transfer Endpoint 5
357 #define USB_O_RQPKTCOUNT6 0x00000318 // USB Request Packet Count in
358  // Block Transfer Endpoint 6
359 #define USB_O_RQPKTCOUNT7 0x0000031C // USB Request Packet Count in
360  // Block Transfer Endpoint 7
361 #define USB_O_RXDPKTBUFDIS 0x00000340 // USB Receive Double Packet Buffer
362  // Disable
363 #define USB_O_TXDPKTBUFDIS 0x00000342 // USB Transmit Double Packet
364  // Buffer Disable
365 #define USB_O_CTO 0x00000344 // USB Chirp Timeout
366 #define USB_O_HHSRTN 0x00000346 // USB High Speed to UTM Operating
367  // Delay
368 #define USB_O_HSBT 0x00000348 // USB High Speed Time-out Adder
369 #define USB_O_LPMATTR 0x00000360 // USB LPM Attributes
370 #define USB_O_LPMCNTRL 0x00000362 // USB LPM Control
371 #define USB_O_LPMIM 0x00000363 // USB LPM Interrupt Mask
372 #define USB_O_LPMRIS 0x00000364 // USB LPM Raw Interrupt Status
373 #define USB_O_LPMFADDR 0x00000365 // USB LPM Function Address
374 #define USB_O_EPC 0x00000400 // USB External Power Control
375 #define USB_O_EPCRIS 0x00000404 // USB External Power Control Raw
376  // Interrupt Status
377 #define USB_O_EPCIM 0x00000408 // USB External Power Control
378  // Interrupt Mask
379 #define USB_O_EPCISC 0x0000040C // USB External Power Control
380  // Interrupt Status and Clear
381 #define USB_O_DRRIS 0x00000410 // USB Device RESUME Raw Interrupt
382  // Status
383 #define USB_O_DRIM 0x00000414 // USB Device RESUME Interrupt Mask
384 #define USB_O_DRISC 0x00000418 // USB Device RESUME Interrupt
385  // Status and Clear
386 #define USB_O_GPCS 0x0000041C // USB General-Purpose Control and
387  // Status
388 #define USB_O_VDC 0x00000430 // USB VBUS Droop Control
389 #define USB_O_VDCRIS 0x00000434 // USB VBUS Droop Control Raw
390  // Interrupt Status
391 #define USB_O_VDCIM 0x00000438 // USB VBUS Droop Control Interrupt
392  // Mask
393 #define USB_O_VDCISC 0x0000043C // USB VBUS Droop Control Interrupt
394  // Status and Clear
395 #define USB_O_IDVRIS 0x00000444 // USB ID Valid Detect Raw
396  // Interrupt Status
397 #define USB_O_IDVIM 0x00000448 // USB ID Valid Detect Interrupt
398  // Mask
399 #define USB_O_IDVISC 0x0000044C // USB ID Valid Detect Interrupt
400  // Status and Clear
401 #define USB_O_PP 0x00000FC0 // USB Peripheral Properties
402 #define USB_O_PC 0x00000FC4 // USB Peripheral Configuration
403 #define USB_O_CC 0x00000FC8 // USB Clock Configuration
404 
405 //*****************************************************************************
406 //
407 // The following are defines for the bit fields in the USB_O_FADDR register.
408 //
409 //*****************************************************************************
410 #define USB_FADDR_M 0x0000007F // Function Address
411 #define USB_FADDR_S 0
412 
413 //*****************************************************************************
414 //
415 // The following are defines for the bit fields in the USB_O_POWER register.
416 //
417 //*****************************************************************************
418 #define USB_POWER_ISOUP 0x00000080 // Isochronous Update
419 #define USB_POWER_SOFTCONN 0x00000040 // Soft Connect/Disconnect
420 #define USB_POWER_HSENAB 0x00000020 // High Speed Enable
421 #define USB_POWER_HSMODE 0x00000010 // High Speed Enable
422 #define USB_POWER_RESET 0x00000008 // RESET Signaling
423 #define USB_POWER_RESUME 0x00000004 // RESUME Signaling
424 #define USB_POWER_SUSPEND 0x00000002 // SUSPEND Mode
425 #define USB_POWER_PWRDNPHY 0x00000001 // Power Down PHY
426 
427 //*****************************************************************************
428 //
429 // The following are defines for the bit fields in the USB_O_TXIS register.
430 //
431 //*****************************************************************************
432 #define USB_TXIS_EP7 0x00000080 // TX Endpoint 7 Interrupt
433 #define USB_TXIS_EP6 0x00000040 // TX Endpoint 6 Interrupt
434 #define USB_TXIS_EP5 0x00000020 // TX Endpoint 5 Interrupt
435 #define USB_TXIS_EP4 0x00000010 // TX Endpoint 4 Interrupt
436 #define USB_TXIS_EP3 0x00000008 // TX Endpoint 3 Interrupt
437 #define USB_TXIS_EP2 0x00000004 // TX Endpoint 2 Interrupt
438 #define USB_TXIS_EP1 0x00000002 // TX Endpoint 1 Interrupt
439 #define USB_TXIS_EP0 0x00000001 // TX and RX Endpoint 0 Interrupt
440 
441 //*****************************************************************************
442 //
443 // The following are defines for the bit fields in the USB_O_RXIS register.
444 //
445 //*****************************************************************************
446 #define USB_RXIS_EP7 0x00000080 // RX Endpoint 7 Interrupt
447 #define USB_RXIS_EP6 0x00000040 // RX Endpoint 6 Interrupt
448 #define USB_RXIS_EP5 0x00000020 // RX Endpoint 5 Interrupt
449 #define USB_RXIS_EP4 0x00000010 // RX Endpoint 4 Interrupt
450 #define USB_RXIS_EP3 0x00000008 // RX Endpoint 3 Interrupt
451 #define USB_RXIS_EP2 0x00000004 // RX Endpoint 2 Interrupt
452 #define USB_RXIS_EP1 0x00000002 // RX Endpoint 1 Interrupt
453 
454 //*****************************************************************************
455 //
456 // The following are defines for the bit fields in the USB_O_TXIE register.
457 //
458 //*****************************************************************************
459 #define USB_TXIE_EP7 0x00000080 // TX Endpoint 7 Interrupt Enable
460 #define USB_TXIE_EP6 0x00000040 // TX Endpoint 6 Interrupt Enable
461 #define USB_TXIE_EP5 0x00000020 // TX Endpoint 5 Interrupt Enable
462 #define USB_TXIE_EP4 0x00000010 // TX Endpoint 4 Interrupt Enable
463 #define USB_TXIE_EP3 0x00000008 // TX Endpoint 3 Interrupt Enable
464 #define USB_TXIE_EP2 0x00000004 // TX Endpoint 2 Interrupt Enable
465 #define USB_TXIE_EP1 0x00000002 // TX Endpoint 1 Interrupt Enable
466 #define USB_TXIE_EP0 0x00000001 // TX and RX Endpoint 0 Interrupt
467  // Enable
468 
469 //*****************************************************************************
470 //
471 // The following are defines for the bit fields in the USB_O_RXIE register.
472 //
473 //*****************************************************************************
474 #define USB_RXIE_EP7 0x00000080 // RX Endpoint 7 Interrupt Enable
475 #define USB_RXIE_EP6 0x00000040 // RX Endpoint 6 Interrupt Enable
476 #define USB_RXIE_EP5 0x00000020 // RX Endpoint 5 Interrupt Enable
477 #define USB_RXIE_EP4 0x00000010 // RX Endpoint 4 Interrupt Enable
478 #define USB_RXIE_EP3 0x00000008 // RX Endpoint 3 Interrupt Enable
479 #define USB_RXIE_EP2 0x00000004 // RX Endpoint 2 Interrupt Enable
480 #define USB_RXIE_EP1 0x00000002 // RX Endpoint 1 Interrupt Enable
481 
482 //*****************************************************************************
483 //
484 // The following are defines for the bit fields in the USB_O_IS register.
485 //
486 //*****************************************************************************
487 #define USB_IS_VBUSERR 0x00000080 // VBUS Error (OTG only)
488 #define USB_IS_SESREQ 0x00000040 // SESSION REQUEST (OTG only)
489 #define USB_IS_DISCON 0x00000020 // Session Disconnect (OTG only)
490 #define USB_IS_CONN 0x00000010 // Session Connect
491 #define USB_IS_SOF 0x00000008 // Start of Frame
492 #define USB_IS_BABBLE 0x00000004 // Babble Detected
493 #define USB_IS_RESET 0x00000004 // RESET Signaling Detected
494 #define USB_IS_RESUME 0x00000002 // RESUME Signaling Detected
495 #define USB_IS_SUSPEND 0x00000001 // SUSPEND Signaling Detected
496 
497 //*****************************************************************************
498 //
499 // The following are defines for the bit fields in the USB_O_IE register.
500 //
501 //*****************************************************************************
502 #define USB_IE_VBUSERR 0x00000080 // Enable VBUS Error Interrupt (OTG
503  // only)
504 #define USB_IE_SESREQ 0x00000040 // Enable Session Request (OTG
505  // only)
506 #define USB_IE_DISCON 0x00000020 // Enable Disconnect Interrupt
507 #define USB_IE_CONN 0x00000010 // Enable Connect Interrupt
508 #define USB_IE_SOF 0x00000008 // Enable Start-of-Frame Interrupt
509 #define USB_IE_BABBLE 0x00000004 // Enable Babble Interrupt
510 #define USB_IE_RESET 0x00000004 // Enable RESET Interrupt
511 #define USB_IE_RESUME 0x00000002 // Enable RESUME Interrupt
512 #define USB_IE_SUSPND 0x00000001 // Enable SUSPEND Interrupt
513 
514 //*****************************************************************************
515 //
516 // The following are defines for the bit fields in the USB_O_FRAME register.
517 //
518 //*****************************************************************************
519 #define USB_FRAME_M 0x000007FF // Frame Number
520 #define USB_FRAME_S 0
521 
522 //*****************************************************************************
523 //
524 // The following are defines for the bit fields in the USB_O_EPIDX register.
525 //
526 //*****************************************************************************
527 #define USB_EPIDX_EPIDX_M 0x0000000F // Endpoint Index
528 #define USB_EPIDX_EPIDX_S 0
529 
530 //*****************************************************************************
531 //
532 // The following are defines for the bit fields in the USB_O_TEST register.
533 //
534 //*****************************************************************************
535 #define USB_TEST_FORCEH 0x00000080 // Force Host Mode
536 #define USB_TEST_FIFOACC 0x00000040 // FIFO Access
537 #define USB_TEST_FORCEFS 0x00000020 // Force Full-Speed Mode
538 #define USB_TEST_FORCEHS 0x00000010 // Force High-Speed Mode
539 #define USB_TEST_TESTPKT 0x00000008 // Test Packet Mode Enable
540 #define USB_TEST_TESTK 0x00000004 // Test_K Mode Enable
541 #define USB_TEST_TESTJ 0x00000002 // Test_J Mode Enable
542 #define USB_TEST_TESTSE0NAK 0x00000001 // Test_SE0_NAK Test Mode Enable
543 
544 //*****************************************************************************
545 //
546 // The following are defines for the bit fields in the USB_O_FIFO0 register.
547 //
548 //*****************************************************************************
549 #define USB_FIFO0_EPDATA_M 0xFFFFFFFF // Endpoint Data
550 #define USB_FIFO0_EPDATA_S 0
551 
552 //*****************************************************************************
553 //
554 // The following are defines for the bit fields in the USB_O_FIFO1 register.
555 //
556 //*****************************************************************************
557 #define USB_FIFO1_EPDATA_M 0xFFFFFFFF // Endpoint Data
558 #define USB_FIFO1_EPDATA_S 0
559 
560 //*****************************************************************************
561 //
562 // The following are defines for the bit fields in the USB_O_FIFO2 register.
563 //
564 //*****************************************************************************
565 #define USB_FIFO2_EPDATA_M 0xFFFFFFFF // Endpoint Data
566 #define USB_FIFO2_EPDATA_S 0
567 
568 //*****************************************************************************
569 //
570 // The following are defines for the bit fields in the USB_O_FIFO3 register.
571 //
572 //*****************************************************************************
573 #define USB_FIFO3_EPDATA_M 0xFFFFFFFF // Endpoint Data
574 #define USB_FIFO3_EPDATA_S 0
575 
576 //*****************************************************************************
577 //
578 // The following are defines for the bit fields in the USB_O_FIFO4 register.
579 //
580 //*****************************************************************************
581 #define USB_FIFO4_EPDATA_M 0xFFFFFFFF // Endpoint Data
582 #define USB_FIFO4_EPDATA_S 0
583 
584 //*****************************************************************************
585 //
586 // The following are defines for the bit fields in the USB_O_FIFO5 register.
587 //
588 //*****************************************************************************
589 #define USB_FIFO5_EPDATA_M 0xFFFFFFFF // Endpoint Data
590 #define USB_FIFO5_EPDATA_S 0
591 
592 //*****************************************************************************
593 //
594 // The following are defines for the bit fields in the USB_O_FIFO6 register.
595 //
596 //*****************************************************************************
597 #define USB_FIFO6_EPDATA_M 0xFFFFFFFF // Endpoint Data
598 #define USB_FIFO6_EPDATA_S 0
599 
600 //*****************************************************************************
601 //
602 // The following are defines for the bit fields in the USB_O_FIFO7 register.
603 //
604 //*****************************************************************************
605 #define USB_FIFO7_EPDATA_M 0xFFFFFFFF // Endpoint Data
606 #define USB_FIFO7_EPDATA_S 0
607 
608 //*****************************************************************************
609 //
610 // The following are defines for the bit fields in the USB_O_DEVCTL register.
611 //
612 //*****************************************************************************
613 #define USB_DEVCTL_DEV 0x00000080 // Device Mode (OTG only)
614 #define USB_DEVCTL_FSDEV 0x00000040 // Full-Speed Device Detected
615 #define USB_DEVCTL_LSDEV 0x00000020 // Low-Speed Device Detected
616 #define USB_DEVCTL_VBUS_M 0x00000018 // VBUS Level (OTG only)
617 #define USB_DEVCTL_VBUS_NONE 0x00000000 // Below SessionEnd
618 #define USB_DEVCTL_VBUS_SEND 0x00000008 // Above SessionEnd, below AValid
619 #define USB_DEVCTL_VBUS_AVALID 0x00000010 // Above AValid, below VBUSValid
620 #define USB_DEVCTL_VBUS_VALID 0x00000018 // Above VBUSValid
621 #define USB_DEVCTL_HOST 0x00000004 // Host Mode
622 #define USB_DEVCTL_HOSTREQ 0x00000002 // Host Request (OTG only)
623 #define USB_DEVCTL_SESSION 0x00000001 // Session Start/End (OTG only)
624 
625 //*****************************************************************************
626 //
627 // The following are defines for the bit fields in the USB_O_CCONF register.
628 //
629 //*****************************************************************************
630 #define USB_CCONF_TXEDMA 0x00000002 // TX Early DMA Enable
631 #define USB_CCONF_RXEDMA 0x00000001 // TX Early DMA Enable
632 
633 //*****************************************************************************
634 //
635 // The following are defines for the bit fields in the USB_O_TXFIFOSZ register.
636 //
637 //*****************************************************************************
638 #define USB_TXFIFOSZ_DPB 0x00000010 // Double Packet Buffer Support
639 #define USB_TXFIFOSZ_SIZE_M 0x0000000F // Max Packet Size
640 #define USB_TXFIFOSZ_SIZE_8 0x00000000 // 8
641 #define USB_TXFIFOSZ_SIZE_16 0x00000001 // 16
642 #define USB_TXFIFOSZ_SIZE_32 0x00000002 // 32
643 #define USB_TXFIFOSZ_SIZE_64 0x00000003 // 64
644 #define USB_TXFIFOSZ_SIZE_128 0x00000004 // 128
645 #define USB_TXFIFOSZ_SIZE_256 0x00000005 // 256
646 #define USB_TXFIFOSZ_SIZE_512 0x00000006 // 512
647 #define USB_TXFIFOSZ_SIZE_1024 0x00000007 // 1024
648 #define USB_TXFIFOSZ_SIZE_2048 0x00000008 // 2048
649 
650 //*****************************************************************************
651 //
652 // The following are defines for the bit fields in the USB_O_RXFIFOSZ register.
653 //
654 //*****************************************************************************
655 #define USB_RXFIFOSZ_DPB 0x00000010 // Double Packet Buffer Support
656 #define USB_RXFIFOSZ_SIZE_M 0x0000000F // Max Packet Size
657 #define USB_RXFIFOSZ_SIZE_8 0x00000000 // 8
658 #define USB_RXFIFOSZ_SIZE_16 0x00000001 // 16
659 #define USB_RXFIFOSZ_SIZE_32 0x00000002 // 32
660 #define USB_RXFIFOSZ_SIZE_64 0x00000003 // 64
661 #define USB_RXFIFOSZ_SIZE_128 0x00000004 // 128
662 #define USB_RXFIFOSZ_SIZE_256 0x00000005 // 256
663 #define USB_RXFIFOSZ_SIZE_512 0x00000006 // 512
664 #define USB_RXFIFOSZ_SIZE_1024 0x00000007 // 1024
665 #define USB_RXFIFOSZ_SIZE_2048 0x00000008 // 2048
666 
667 //*****************************************************************************
668 //
669 // The following are defines for the bit fields in the USB_O_TXFIFOADD
670 // register.
671 //
672 //*****************************************************************************
673 #define USB_TXFIFOADD_ADDR_M 0x000001FF // Transmit/Receive Start Address
674 #define USB_TXFIFOADD_ADDR_S 0
675 
676 //*****************************************************************************
677 //
678 // The following are defines for the bit fields in the USB_O_RXFIFOADD
679 // register.
680 //
681 //*****************************************************************************
682 #define USB_RXFIFOADD_ADDR_M 0x000001FF // Transmit/Receive Start Address
683 #define USB_RXFIFOADD_ADDR_S 0
684 
685 //*****************************************************************************
686 //
687 // The following are defines for the bit fields in the USB_O_ULPIVBUSCTL
688 // register.
689 //
690 //*****************************************************************************
691 #define USB_ULPIVBUSCTL_USEEXTVBUSIND \
692  0x00000002 // Use External VBUS Indicator
693 #define USB_ULPIVBUSCTL_USEEXTVBUS \
694  0x00000001 // Use External VBUS
695 
696 //*****************************************************************************
697 //
698 // The following are defines for the bit fields in the USB_O_ULPIREGDATA
699 // register.
700 //
701 //*****************************************************************************
702 #define USB_ULPIREGDATA_REGDATA_M \
703  0x000000FF // Register Data
704 #define USB_ULPIREGDATA_REGDATA_S \
705  0
706 
707 //*****************************************************************************
708 //
709 // The following are defines for the bit fields in the USB_O_ULPIREGADDR
710 // register.
711 //
712 //*****************************************************************************
713 #define USB_ULPIREGADDR_ADDR_M 0x000000FF // Register Address
714 #define USB_ULPIREGADDR_ADDR_S 0
715 
716 //*****************************************************************************
717 //
718 // The following are defines for the bit fields in the USB_O_ULPIREGCTL
719 // register.
720 //
721 //*****************************************************************************
722 #define USB_ULPIREGCTL_RDWR 0x00000004 // Read/Write Control
723 #define USB_ULPIREGCTL_REGCMPLT 0x00000002 // Register Access Complete
724 #define USB_ULPIREGCTL_REGACC 0x00000001 // Initiate Register Access
725 
726 //*****************************************************************************
727 //
728 // The following are defines for the bit fields in the USB_O_EPINFO register.
729 //
730 //*****************************************************************************
731 #define USB_EPINFO_RXEP_M 0x000000F0 // RX Endpoints
732 #define USB_EPINFO_TXEP_M 0x0000000F // TX Endpoints
733 #define USB_EPINFO_RXEP_S 4
734 #define USB_EPINFO_TXEP_S 0
735 
736 //*****************************************************************************
737 //
738 // The following are defines for the bit fields in the USB_O_RAMINFO register.
739 //
740 //*****************************************************************************
741 #define USB_RAMINFO_DMACHAN_M 0x000000F0 // DMA Channels
742 #define USB_RAMINFO_RAMBITS_M 0x0000000F // RAM Address Bus Width
743 #define USB_RAMINFO_DMACHAN_S 4
744 #define USB_RAMINFO_RAMBITS_S 0
745 
746 //*****************************************************************************
747 //
748 // The following are defines for the bit fields in the USB_O_CONTIM register.
749 //
750 //*****************************************************************************
751 #define USB_CONTIM_WTCON_M 0x000000F0 // Connect Wait
752 #define USB_CONTIM_WTID_M 0x0000000F // Wait ID
753 #define USB_CONTIM_WTCON_S 4
754 #define USB_CONTIM_WTID_S 0
755 
756 //*****************************************************************************
757 //
758 // The following are defines for the bit fields in the USB_O_VPLEN register.
759 //
760 //*****************************************************************************
761 #define USB_VPLEN_VPLEN_M 0x000000FF // VBUS Pulse Length
762 #define USB_VPLEN_VPLEN_S 0
763 
764 //*****************************************************************************
765 //
766 // The following are defines for the bit fields in the USB_O_HSEOF register.
767 //
768 //*****************************************************************************
769 #define USB_HSEOF_HSEOFG_M 0x000000FF // HIgh-Speed End-of-Frame Gap
770 #define USB_HSEOF_HSEOFG_S 0
771 
772 //*****************************************************************************
773 //
774 // The following are defines for the bit fields in the USB_O_FSEOF register.
775 //
776 //*****************************************************************************
777 #define USB_FSEOF_FSEOFG_M 0x000000FF // Full-Speed End-of-Frame Gap
778 #define USB_FSEOF_FSEOFG_S 0
779 
780 //*****************************************************************************
781 //
782 // The following are defines for the bit fields in the USB_O_LSEOF register.
783 //
784 //*****************************************************************************
785 #define USB_LSEOF_LSEOFG_M 0x000000FF // Low-Speed End-of-Frame Gap
786 #define USB_LSEOF_LSEOFG_S 0
787 
788 //*****************************************************************************
789 //
790 // The following are defines for the bit fields in the USB_O_TXFUNCADDR0
791 // register.
792 //
793 //*****************************************************************************
794 #define USB_TXFUNCADDR0_ADDR_M 0x0000007F // Device Address
795 #define USB_TXFUNCADDR0_ADDR_S 0
796 
797 //*****************************************************************************
798 //
799 // The following are defines for the bit fields in the USB_O_TXHUBADDR0
800 // register.
801 //
802 //*****************************************************************************
803 #define USB_TXHUBADDR0_ADDR_M 0x0000007F // Hub Address
804 #define USB_TXHUBADDR0_ADDR_S 0
805 
806 //*****************************************************************************
807 //
808 // The following are defines for the bit fields in the USB_O_TXHUBPORT0
809 // register.
810 //
811 //*****************************************************************************
812 #define USB_TXHUBPORT0_PORT_M 0x0000007F // Hub Port
813 #define USB_TXHUBPORT0_PORT_S 0
814 
815 //*****************************************************************************
816 //
817 // The following are defines for the bit fields in the USB_O_TXFUNCADDR1
818 // register.
819 //
820 //*****************************************************************************
821 #define USB_TXFUNCADDR1_ADDR_M 0x0000007F // Device Address
822 #define USB_TXFUNCADDR1_ADDR_S 0
823 
824 //*****************************************************************************
825 //
826 // The following are defines for the bit fields in the USB_O_TXHUBADDR1
827 // register.
828 //
829 //*****************************************************************************
830 #define USB_TXHUBADDR1_ADDR_M 0x0000007F // Hub Address
831 #define USB_TXHUBADDR1_ADDR_S 0
832 
833 //*****************************************************************************
834 //
835 // The following are defines for the bit fields in the USB_O_TXHUBPORT1
836 // register.
837 //
838 //*****************************************************************************
839 #define USB_TXHUBPORT1_PORT_M 0x0000007F // Hub Port
840 #define USB_TXHUBPORT1_PORT_S 0
841 
842 //*****************************************************************************
843 //
844 // The following are defines for the bit fields in the USB_O_RXFUNCADDR1
845 // register.
846 //
847 //*****************************************************************************
848 #define USB_RXFUNCADDR1_ADDR_M 0x0000007F // Device Address
849 #define USB_RXFUNCADDR1_ADDR_S 0
850 
851 //*****************************************************************************
852 //
853 // The following are defines for the bit fields in the USB_O_RXHUBADDR1
854 // register.
855 //
856 //*****************************************************************************
857 #define USB_RXHUBADDR1_ADDR_M 0x0000007F // Hub Address
858 #define USB_RXHUBADDR1_ADDR_S 0
859 
860 //*****************************************************************************
861 //
862 // The following are defines for the bit fields in the USB_O_RXHUBPORT1
863 // register.
864 //
865 //*****************************************************************************
866 #define USB_RXHUBPORT1_PORT_M 0x0000007F // Hub Port
867 #define USB_RXHUBPORT1_PORT_S 0
868 
869 //*****************************************************************************
870 //
871 // The following are defines for the bit fields in the USB_O_TXFUNCADDR2
872 // register.
873 //
874 //*****************************************************************************
875 #define USB_TXFUNCADDR2_ADDR_M 0x0000007F // Device Address
876 #define USB_TXFUNCADDR2_ADDR_S 0
877 
878 //*****************************************************************************
879 //
880 // The following are defines for the bit fields in the USB_O_TXHUBADDR2
881 // register.
882 //
883 //*****************************************************************************
884 #define USB_TXHUBADDR2_ADDR_M 0x0000007F // Hub Address
885 #define USB_TXHUBADDR2_ADDR_S 0
886 
887 //*****************************************************************************
888 //
889 // The following are defines for the bit fields in the USB_O_TXHUBPORT2
890 // register.
891 //
892 //*****************************************************************************
893 #define USB_TXHUBPORT2_PORT_M 0x0000007F // Hub Port
894 #define USB_TXHUBPORT2_PORT_S 0
895 
896 //*****************************************************************************
897 //
898 // The following are defines for the bit fields in the USB_O_RXFUNCADDR2
899 // register.
900 //
901 //*****************************************************************************
902 #define USB_RXFUNCADDR2_ADDR_M 0x0000007F // Device Address
903 #define USB_RXFUNCADDR2_ADDR_S 0
904 
905 //*****************************************************************************
906 //
907 // The following are defines for the bit fields in the USB_O_RXHUBADDR2
908 // register.
909 //
910 //*****************************************************************************
911 #define USB_RXHUBADDR2_ADDR_M 0x0000007F // Hub Address
912 #define USB_RXHUBADDR2_ADDR_S 0
913 
914 //*****************************************************************************
915 //
916 // The following are defines for the bit fields in the USB_O_RXHUBPORT2
917 // register.
918 //
919 //*****************************************************************************
920 #define USB_RXHUBPORT2_PORT_M 0x0000007F // Hub Port
921 #define USB_RXHUBPORT2_PORT_S 0
922 
923 //*****************************************************************************
924 //
925 // The following are defines for the bit fields in the USB_O_TXFUNCADDR3
926 // register.
927 //
928 //*****************************************************************************
929 #define USB_TXFUNCADDR3_ADDR_M 0x0000007F // Device Address
930 #define USB_TXFUNCADDR3_ADDR_S 0
931 
932 //*****************************************************************************
933 //
934 // The following are defines for the bit fields in the USB_O_TXHUBADDR3
935 // register.
936 //
937 //*****************************************************************************
938 #define USB_TXHUBADDR3_ADDR_M 0x0000007F // Hub Address
939 #define USB_TXHUBADDR3_ADDR_S 0
940 
941 //*****************************************************************************
942 //
943 // The following are defines for the bit fields in the USB_O_TXHUBPORT3
944 // register.
945 //
946 //*****************************************************************************
947 #define USB_TXHUBPORT3_PORT_M 0x0000007F // Hub Port
948 #define USB_TXHUBPORT3_PORT_S 0
949 
950 //*****************************************************************************
951 //
952 // The following are defines for the bit fields in the USB_O_RXFUNCADDR3
953 // register.
954 //
955 //*****************************************************************************
956 #define USB_RXFUNCADDR3_ADDR_M 0x0000007F // Device Address
957 #define USB_RXFUNCADDR3_ADDR_S 0
958 
959 //*****************************************************************************
960 //
961 // The following are defines for the bit fields in the USB_O_RXHUBADDR3
962 // register.
963 //
964 //*****************************************************************************
965 #define USB_RXHUBADDR3_ADDR_M 0x0000007F // Hub Address
966 #define USB_RXHUBADDR3_ADDR_S 0
967 
968 //*****************************************************************************
969 //
970 // The following are defines for the bit fields in the USB_O_RXHUBPORT3
971 // register.
972 //
973 //*****************************************************************************
974 #define USB_RXHUBPORT3_PORT_M 0x0000007F // Hub Port
975 #define USB_RXHUBPORT3_PORT_S 0
976 
977 //*****************************************************************************
978 //
979 // The following are defines for the bit fields in the USB_O_TXFUNCADDR4
980 // register.
981 //
982 //*****************************************************************************
983 #define USB_TXFUNCADDR4_ADDR_M 0x0000007F // Device Address
984 #define USB_TXFUNCADDR4_ADDR_S 0
985 
986 //*****************************************************************************
987 //
988 // The following are defines for the bit fields in the USB_O_TXHUBADDR4
989 // register.
990 //
991 //*****************************************************************************
992 #define USB_TXHUBADDR4_ADDR_M 0x0000007F // Hub Address
993 #define USB_TXHUBADDR4_ADDR_S 0
994 
995 //*****************************************************************************
996 //
997 // The following are defines for the bit fields in the USB_O_TXHUBPORT4
998 // register.
999 //
1000 //*****************************************************************************
1001 #define USB_TXHUBPORT4_PORT_M 0x0000007F // Hub Port
1002 #define USB_TXHUBPORT4_PORT_S 0
1003 
1004 //*****************************************************************************
1005 //
1006 // The following are defines for the bit fields in the USB_O_RXFUNCADDR4
1007 // register.
1008 //
1009 //*****************************************************************************
1010 #define USB_RXFUNCADDR4_ADDR_M 0x0000007F // Device Address
1011 #define USB_RXFUNCADDR4_ADDR_S 0
1012 
1013 //*****************************************************************************
1014 //
1015 // The following are defines for the bit fields in the USB_O_RXHUBADDR4
1016 // register.
1017 //
1018 //*****************************************************************************
1019 #define USB_RXHUBADDR4_ADDR_M 0x0000007F // Hub Address
1020 #define USB_RXHUBADDR4_ADDR_S 0
1021 
1022 //*****************************************************************************
1023 //
1024 // The following are defines for the bit fields in the USB_O_RXHUBPORT4
1025 // register.
1026 //
1027 //*****************************************************************************
1028 #define USB_RXHUBPORT4_PORT_M 0x0000007F // Hub Port
1029 #define USB_RXHUBPORT4_PORT_S 0
1030 
1031 //*****************************************************************************
1032 //
1033 // The following are defines for the bit fields in the USB_O_TXFUNCADDR5
1034 // register.
1035 //
1036 //*****************************************************************************
1037 #define USB_TXFUNCADDR5_ADDR_M 0x0000007F // Device Address
1038 #define USB_TXFUNCADDR5_ADDR_S 0
1039 
1040 //*****************************************************************************
1041 //
1042 // The following are defines for the bit fields in the USB_O_TXHUBADDR5
1043 // register.
1044 //
1045 //*****************************************************************************
1046 #define USB_TXHUBADDR5_ADDR_M 0x0000007F // Hub Address
1047 #define USB_TXHUBADDR5_ADDR_S 0
1048 
1049 //*****************************************************************************
1050 //
1051 // The following are defines for the bit fields in the USB_O_TXHUBPORT5
1052 // register.
1053 //
1054 //*****************************************************************************
1055 #define USB_TXHUBPORT5_PORT_M 0x0000007F // Hub Port
1056 #define USB_TXHUBPORT5_PORT_S 0
1057 
1058 //*****************************************************************************
1059 //
1060 // The following are defines for the bit fields in the USB_O_RXFUNCADDR5
1061 // register.
1062 //
1063 //*****************************************************************************
1064 #define USB_RXFUNCADDR5_ADDR_M 0x0000007F // Device Address
1065 #define USB_RXFUNCADDR5_ADDR_S 0
1066 
1067 //*****************************************************************************
1068 //
1069 // The following are defines for the bit fields in the USB_O_RXHUBADDR5
1070 // register.
1071 //
1072 //*****************************************************************************
1073 #define USB_RXHUBADDR5_ADDR_M 0x0000007F // Hub Address
1074 #define USB_RXHUBADDR5_ADDR_S 0
1075 
1076 //*****************************************************************************
1077 //
1078 // The following are defines for the bit fields in the USB_O_RXHUBPORT5
1079 // register.
1080 //
1081 //*****************************************************************************
1082 #define USB_RXHUBPORT5_PORT_M 0x0000007F // Hub Port
1083 #define USB_RXHUBPORT5_PORT_S 0
1084 
1085 //*****************************************************************************
1086 //
1087 // The following are defines for the bit fields in the USB_O_TXFUNCADDR6
1088 // register.
1089 //
1090 //*****************************************************************************
1091 #define USB_TXFUNCADDR6_ADDR_M 0x0000007F // Device Address
1092 #define USB_TXFUNCADDR6_ADDR_S 0
1093 
1094 //*****************************************************************************
1095 //
1096 // The following are defines for the bit fields in the USB_O_TXHUBADDR6
1097 // register.
1098 //
1099 //*****************************************************************************
1100 #define USB_TXHUBADDR6_ADDR_M 0x0000007F // Hub Address
1101 #define USB_TXHUBADDR6_ADDR_S 0
1102 
1103 //*****************************************************************************
1104 //
1105 // The following are defines for the bit fields in the USB_O_TXHUBPORT6
1106 // register.
1107 //
1108 //*****************************************************************************
1109 #define USB_TXHUBPORT6_PORT_M 0x0000007F // Hub Port
1110 #define USB_TXHUBPORT6_PORT_S 0
1111 
1112 //*****************************************************************************
1113 //
1114 // The following are defines for the bit fields in the USB_O_RXFUNCADDR6
1115 // register.
1116 //
1117 //*****************************************************************************
1118 #define USB_RXFUNCADDR6_ADDR_M 0x0000007F // Device Address
1119 #define USB_RXFUNCADDR6_ADDR_S 0
1120 
1121 //*****************************************************************************
1122 //
1123 // The following are defines for the bit fields in the USB_O_RXHUBADDR6
1124 // register.
1125 //
1126 //*****************************************************************************
1127 #define USB_RXHUBADDR6_ADDR_M 0x0000007F // Hub Address
1128 #define USB_RXHUBADDR6_ADDR_S 0
1129 
1130 //*****************************************************************************
1131 //
1132 // The following are defines for the bit fields in the USB_O_RXHUBPORT6
1133 // register.
1134 //
1135 //*****************************************************************************
1136 #define USB_RXHUBPORT6_PORT_M 0x0000007F // Hub Port
1137 #define USB_RXHUBPORT6_PORT_S 0
1138 
1139 //*****************************************************************************
1140 //
1141 // The following are defines for the bit fields in the USB_O_TXFUNCADDR7
1142 // register.
1143 //
1144 //*****************************************************************************
1145 #define USB_TXFUNCADDR7_ADDR_M 0x0000007F // Device Address
1146 #define USB_TXFUNCADDR7_ADDR_S 0
1147 
1148 //*****************************************************************************
1149 //
1150 // The following are defines for the bit fields in the USB_O_TXHUBADDR7
1151 // register.
1152 //
1153 //*****************************************************************************
1154 #define USB_TXHUBADDR7_ADDR_M 0x0000007F // Hub Address
1155 #define USB_TXHUBADDR7_ADDR_S 0
1156 
1157 //*****************************************************************************
1158 //
1159 // The following are defines for the bit fields in the USB_O_TXHUBPORT7
1160 // register.
1161 //
1162 //*****************************************************************************
1163 #define USB_TXHUBPORT7_PORT_M 0x0000007F // Hub Port
1164 #define USB_TXHUBPORT7_PORT_S 0
1165 
1166 //*****************************************************************************
1167 //
1168 // The following are defines for the bit fields in the USB_O_RXFUNCADDR7
1169 // register.
1170 //
1171 //*****************************************************************************
1172 #define USB_RXFUNCADDR7_ADDR_M 0x0000007F // Device Address
1173 #define USB_RXFUNCADDR7_ADDR_S 0
1174 
1175 //*****************************************************************************
1176 //
1177 // The following are defines for the bit fields in the USB_O_RXHUBADDR7
1178 // register.
1179 //
1180 //*****************************************************************************
1181 #define USB_RXHUBADDR7_ADDR_M 0x0000007F // Hub Address
1182 #define USB_RXHUBADDR7_ADDR_S 0
1183 
1184 //*****************************************************************************
1185 //
1186 // The following are defines for the bit fields in the USB_O_RXHUBPORT7
1187 // register.
1188 //
1189 //*****************************************************************************
1190 #define USB_RXHUBPORT7_PORT_M 0x0000007F // Hub Port
1191 #define USB_RXHUBPORT7_PORT_S 0
1192 
1193 //*****************************************************************************
1194 //
1195 // The following are defines for the bit fields in the USB_O_CSRL0 register.
1196 //
1197 //*****************************************************************************
1198 #define USB_CSRL0_NAKTO 0x00000080 // NAK Timeout
1199 #define USB_CSRL0_SETENDC 0x00000080 // Setup End Clear
1200 #define USB_CSRL0_STATUS 0x00000040 // STATUS Packet
1201 #define USB_CSRL0_RXRDYC 0x00000040 // RXRDY Clear
1202 #define USB_CSRL0_REQPKT 0x00000020 // Request Packet
1203 #define USB_CSRL0_STALL 0x00000020 // Send Stall
1204 #define USB_CSRL0_SETEND 0x00000010 // Setup End
1205 #define USB_CSRL0_ERROR 0x00000010 // Error
1206 #define USB_CSRL0_DATAEND 0x00000008 // Data End
1207 #define USB_CSRL0_SETUP 0x00000008 // Setup Packet
1208 #define USB_CSRL0_STALLED 0x00000004 // Endpoint Stalled
1209 #define USB_CSRL0_TXRDY 0x00000002 // Transmit Packet Ready
1210 #define USB_CSRL0_RXRDY 0x00000001 // Receive Packet Ready
1211 
1212 //*****************************************************************************
1213 //
1214 // The following are defines for the bit fields in the USB_O_CSRH0 register.
1215 //
1216 //*****************************************************************************
1217 #define USB_CSRH0_DISPING 0x00000008 // PING Disable
1218 #define USB_CSRH0_DTWE 0x00000004 // Data Toggle Write Enable
1219 #define USB_CSRH0_DT 0x00000002 // Data Toggle
1220 #define USB_CSRH0_FLUSH 0x00000001 // Flush FIFO
1221 
1222 //*****************************************************************************
1223 //
1224 // The following are defines for the bit fields in the USB_O_COUNT0 register.
1225 //
1226 //*****************************************************************************
1227 #define USB_COUNT0_COUNT_M 0x0000007F // FIFO Count
1228 #define USB_COUNT0_COUNT_S 0
1229 
1230 //*****************************************************************************
1231 //
1232 // The following are defines for the bit fields in the USB_O_TYPE0 register.
1233 //
1234 //*****************************************************************************
1235 #define USB_TYPE0_SPEED_M 0x000000C0 // Operating Speed
1236 #define USB_TYPE0_SPEED_HIGH 0x00000040 // High
1237 #define USB_TYPE0_SPEED_FULL 0x00000080 // Full
1238 #define USB_TYPE0_SPEED_LOW 0x000000C0 // Low
1239 
1240 //*****************************************************************************
1241 //
1242 // The following are defines for the bit fields in the USB_O_NAKLMT register.
1243 //
1244 //*****************************************************************************
1245 #define USB_NAKLMT_NAKLMT_M 0x0000001F // EP0 NAK Limit
1246 #define USB_NAKLMT_NAKLMT_S 0
1247 
1248 //*****************************************************************************
1249 //
1250 // The following are defines for the bit fields in the USB_O_TXMAXP1 register.
1251 //
1252 //*****************************************************************************
1253 #define USB_TXMAXP1_MAXLOAD_M 0x000007FF // Maximum Payload
1254 #define USB_TXMAXP1_MAXLOAD_S 0
1255 
1256 //*****************************************************************************
1257 //
1258 // The following are defines for the bit fields in the USB_O_TXCSRL1 register.
1259 //
1260 //*****************************************************************************
1261 #define USB_TXCSRL1_NAKTO 0x00000080 // NAK Timeout
1262 #define USB_TXCSRL1_CLRDT 0x00000040 // Clear Data Toggle
1263 #define USB_TXCSRL1_STALLED 0x00000020 // Endpoint Stalled
1264 #define USB_TXCSRL1_STALL 0x00000010 // Send STALL
1265 #define USB_TXCSRL1_SETUP 0x00000010 // Setup Packet
1266 #define USB_TXCSRL1_FLUSH 0x00000008 // Flush FIFO
1267 #define USB_TXCSRL1_ERROR 0x00000004 // Error
1268 #define USB_TXCSRL1_UNDRN 0x00000004 // Underrun
1269 #define USB_TXCSRL1_FIFONE 0x00000002 // FIFO Not Empty
1270 #define USB_TXCSRL1_TXRDY 0x00000001 // Transmit Packet Ready
1271 
1272 //*****************************************************************************
1273 //
1274 // The following are defines for the bit fields in the USB_O_TXCSRH1 register.
1275 //
1276 //*****************************************************************************
1277 #define USB_TXCSRH1_AUTOSET 0x00000080 // Auto Set
1278 #define USB_TXCSRH1_ISO 0x00000040 // Isochronous Transfers
1279 #define USB_TXCSRH1_MODE 0x00000020 // Mode
1280 #define USB_TXCSRH1_DMAEN 0x00000010 // DMA Request Enable
1281 #define USB_TXCSRH1_FDT 0x00000008 // Force Data Toggle
1282 #define USB_TXCSRH1_DMAMOD 0x00000004 // DMA Request Mode
1283 #define USB_TXCSRH1_DTWE 0x00000002 // Data Toggle Write Enable
1284 #define USB_TXCSRH1_DT 0x00000001 // Data Toggle
1285 
1286 //*****************************************************************************
1287 //
1288 // The following are defines for the bit fields in the USB_O_RXMAXP1 register.
1289 //
1290 //*****************************************************************************
1291 #define USB_RXMAXP1_MAXLOAD_M 0x000007FF // Maximum Payload
1292 #define USB_RXMAXP1_MAXLOAD_S 0
1293 
1294 //*****************************************************************************
1295 //
1296 // The following are defines for the bit fields in the USB_O_RXCSRL1 register.
1297 //
1298 //*****************************************************************************
1299 #define USB_RXCSRL1_CLRDT 0x00000080 // Clear Data Toggle
1300 #define USB_RXCSRL1_STALLED 0x00000040 // Endpoint Stalled
1301 #define USB_RXCSRL1_STALL 0x00000020 // Send STALL
1302 #define USB_RXCSRL1_REQPKT 0x00000020 // Request Packet
1303 #define USB_RXCSRL1_FLUSH 0x00000010 // Flush FIFO
1304 #define USB_RXCSRL1_DATAERR 0x00000008 // Data Error
1305 #define USB_RXCSRL1_NAKTO 0x00000008 // NAK Timeout
1306 #define USB_RXCSRL1_OVER 0x00000004 // Overrun
1307 #define USB_RXCSRL1_ERROR 0x00000004 // Error
1308 #define USB_RXCSRL1_FULL 0x00000002 // FIFO Full
1309 #define USB_RXCSRL1_RXRDY 0x00000001 // Receive Packet Ready
1310 
1311 //*****************************************************************************
1312 //
1313 // The following are defines for the bit fields in the USB_O_RXCSRH1 register.
1314 //
1315 //*****************************************************************************
1316 #define USB_RXCSRH1_AUTOCL 0x00000080 // Auto Clear
1317 #define USB_RXCSRH1_AUTORQ 0x00000040 // Auto Request
1318 #define USB_RXCSRH1_ISO 0x00000040 // Isochronous Transfers
1319 #define USB_RXCSRH1_DMAEN 0x00000020 // DMA Request Enable
1320 #define USB_RXCSRH1_DISNYET 0x00000010 // Disable NYET
1321 #define USB_RXCSRH1_PIDERR 0x00000010 // PID Error
1322 #define USB_RXCSRH1_DMAMOD 0x00000008 // DMA Request Mode
1323 #define USB_RXCSRH1_DTWE 0x00000004 // Data Toggle Write Enable
1324 #define USB_RXCSRH1_DT 0x00000002 // Data Toggle
1325 #define USB_RXCSRH1_INCOMPRX 0x00000001 // Incomplete RX Transmission
1326  // Status
1327 
1328 //*****************************************************************************
1329 //
1330 // The following are defines for the bit fields in the USB_O_RXCOUNT1 register.
1331 //
1332 //*****************************************************************************
1333 #define USB_RXCOUNT1_COUNT_M 0x00001FFF // Receive Packet Count
1334 #define USB_RXCOUNT1_COUNT_S 0
1335 
1336 //*****************************************************************************
1337 //
1338 // The following are defines for the bit fields in the USB_O_TXTYPE1 register.
1339 //
1340 //*****************************************************************************
1341 #define USB_TXTYPE1_SPEED_M 0x000000C0 // Operating Speed
1342 #define USB_TXTYPE1_SPEED_DFLT 0x00000000 // Default
1343 #define USB_TXTYPE1_SPEED_HIGH 0x00000040 // High
1344 #define USB_TXTYPE1_SPEED_FULL 0x00000080 // Full
1345 #define USB_TXTYPE1_SPEED_LOW 0x000000C0 // Low
1346 #define USB_TXTYPE1_PROTO_M 0x00000030 // Protocol
1347 #define USB_TXTYPE1_PROTO_CTRL 0x00000000 // Control
1348 #define USB_TXTYPE1_PROTO_ISOC 0x00000010 // Isochronous
1349 #define USB_TXTYPE1_PROTO_BULK 0x00000020 // Bulk
1350 #define USB_TXTYPE1_PROTO_INT 0x00000030 // Interrupt
1351 #define USB_TXTYPE1_TEP_M 0x0000000F // Target Endpoint Number
1352 #define USB_TXTYPE1_TEP_S 0
1353 
1354 //*****************************************************************************
1355 //
1356 // The following are defines for the bit fields in the USB_O_TXINTERVAL1
1357 // register.
1358 //
1359 //*****************************************************************************
1360 #define USB_TXINTERVAL1_NAKLMT_M \
1361  0x000000FF // NAK Limit
1362 #define USB_TXINTERVAL1_TXPOLL_M \
1363  0x000000FF // TX Polling
1364 #define USB_TXINTERVAL1_TXPOLL_S \
1365  0
1366 #define USB_TXINTERVAL1_NAKLMT_S \
1367  0
1368 
1369 //*****************************************************************************
1370 //
1371 // The following are defines for the bit fields in the USB_O_RXTYPE1 register.
1372 //
1373 //*****************************************************************************
1374 #define USB_RXTYPE1_SPEED_M 0x000000C0 // Operating Speed
1375 #define USB_RXTYPE1_SPEED_DFLT 0x00000000 // Default
1376 #define USB_RXTYPE1_SPEED_HIGH 0x00000040 // High
1377 #define USB_RXTYPE1_SPEED_FULL 0x00000080 // Full
1378 #define USB_RXTYPE1_SPEED_LOW 0x000000C0 // Low
1379 #define USB_RXTYPE1_PROTO_M 0x00000030 // Protocol
1380 #define USB_RXTYPE1_PROTO_CTRL 0x00000000 // Control
1381 #define USB_RXTYPE1_PROTO_ISOC 0x00000010 // Isochronous
1382 #define USB_RXTYPE1_PROTO_BULK 0x00000020 // Bulk
1383 #define USB_RXTYPE1_PROTO_INT 0x00000030 // Interrupt
1384 #define USB_RXTYPE1_TEP_M 0x0000000F // Target Endpoint Number
1385 #define USB_RXTYPE1_TEP_S 0
1386 
1387 //*****************************************************************************
1388 //
1389 // The following are defines for the bit fields in the USB_O_RXINTERVAL1
1390 // register.
1391 //
1392 //*****************************************************************************
1393 #define USB_RXINTERVAL1_TXPOLL_M \
1394  0x000000FF // RX Polling
1395 #define USB_RXINTERVAL1_NAKLMT_M \
1396  0x000000FF // NAK Limit
1397 #define USB_RXINTERVAL1_TXPOLL_S \
1398  0
1399 #define USB_RXINTERVAL1_NAKLMT_S \
1400  0
1401 
1402 //*****************************************************************************
1403 //
1404 // The following are defines for the bit fields in the USB_O_TXMAXP2 register.
1405 //
1406 //*****************************************************************************
1407 #define USB_TXMAXP2_MAXLOAD_M 0x000007FF // Maximum Payload
1408 #define USB_TXMAXP2_MAXLOAD_S 0
1409 
1410 //*****************************************************************************
1411 //
1412 // The following are defines for the bit fields in the USB_O_TXCSRL2 register.
1413 //
1414 //*****************************************************************************
1415 #define USB_TXCSRL2_NAKTO 0x00000080 // NAK Timeout
1416 #define USB_TXCSRL2_CLRDT 0x00000040 // Clear Data Toggle
1417 #define USB_TXCSRL2_STALLED 0x00000020 // Endpoint Stalled
1418 #define USB_TXCSRL2_SETUP 0x00000010 // Setup Packet
1419 #define USB_TXCSRL2_STALL 0x00000010 // Send STALL
1420 #define USB_TXCSRL2_FLUSH 0x00000008 // Flush FIFO
1421 #define USB_TXCSRL2_ERROR 0x00000004 // Error
1422 #define USB_TXCSRL2_UNDRN 0x00000004 // Underrun
1423 #define USB_TXCSRL2_FIFONE 0x00000002 // FIFO Not Empty
1424 #define USB_TXCSRL2_TXRDY 0x00000001 // Transmit Packet Ready
1425 
1426 //*****************************************************************************
1427 //
1428 // The following are defines for the bit fields in the USB_O_TXCSRH2 register.
1429 //
1430 //*****************************************************************************
1431 #define USB_TXCSRH2_AUTOSET 0x00000080 // Auto Set
1432 #define USB_TXCSRH2_ISO 0x00000040 // Isochronous Transfers
1433 #define USB_TXCSRH2_MODE 0x00000020 // Mode
1434 #define USB_TXCSRH2_DMAEN 0x00000010 // DMA Request Enable
1435 #define USB_TXCSRH2_FDT 0x00000008 // Force Data Toggle
1436 #define USB_TXCSRH2_DMAMOD 0x00000004 // DMA Request Mode
1437 #define USB_TXCSRH2_DTWE 0x00000002 // Data Toggle Write Enable
1438 #define USB_TXCSRH2_DT 0x00000001 // Data Toggle
1439 
1440 //*****************************************************************************
1441 //
1442 // The following are defines for the bit fields in the USB_O_RXMAXP2 register.
1443 //
1444 //*****************************************************************************
1445 #define USB_RXMAXP2_MAXLOAD_M 0x000007FF // Maximum Payload
1446 #define USB_RXMAXP2_MAXLOAD_S 0
1447 
1448 //*****************************************************************************
1449 //
1450 // The following are defines for the bit fields in the USB_O_RXCSRL2 register.
1451 //
1452 //*****************************************************************************
1453 #define USB_RXCSRL2_CLRDT 0x00000080 // Clear Data Toggle
1454 #define USB_RXCSRL2_STALLED 0x00000040 // Endpoint Stalled
1455 #define USB_RXCSRL2_REQPKT 0x00000020 // Request Packet
1456 #define USB_RXCSRL2_STALL 0x00000020 // Send STALL
1457 #define USB_RXCSRL2_FLUSH 0x00000010 // Flush FIFO
1458 #define USB_RXCSRL2_DATAERR 0x00000008 // Data Error
1459 #define USB_RXCSRL2_NAKTO 0x00000008 // NAK Timeout
1460 #define USB_RXCSRL2_ERROR 0x00000004 // Error
1461 #define USB_RXCSRL2_OVER 0x00000004 // Overrun
1462 #define USB_RXCSRL2_FULL 0x00000002 // FIFO Full
1463 #define USB_RXCSRL2_RXRDY 0x00000001 // Receive Packet Ready
1464 
1465 //*****************************************************************************
1466 //
1467 // The following are defines for the bit fields in the USB_O_RXCSRH2 register.
1468 //
1469 //*****************************************************************************
1470 #define USB_RXCSRH2_AUTOCL 0x00000080 // Auto Clear
1471 #define USB_RXCSRH2_AUTORQ 0x00000040 // Auto Request
1472 #define USB_RXCSRH2_ISO 0x00000040 // Isochronous Transfers
1473 #define USB_RXCSRH2_DMAEN 0x00000020 // DMA Request Enable
1474 #define USB_RXCSRH2_DISNYET 0x00000010 // Disable NYET
1475 #define USB_RXCSRH2_PIDERR 0x00000010 // PID Error
1476 #define USB_RXCSRH2_DMAMOD 0x00000008 // DMA Request Mode
1477 #define USB_RXCSRH2_DTWE 0x00000004 // Data Toggle Write Enable
1478 #define USB_RXCSRH2_DT 0x00000002 // Data Toggle
1479 #define USB_RXCSRH2_INCOMPRX 0x00000001 // Incomplete RX Transmission
1480  // Status
1481 
1482 //*****************************************************************************
1483 //
1484 // The following are defines for the bit fields in the USB_O_RXCOUNT2 register.
1485 //
1486 //*****************************************************************************
1487 #define USB_RXCOUNT2_COUNT_M 0x00001FFF // Receive Packet Count
1488 #define USB_RXCOUNT2_COUNT_S 0
1489 
1490 //*****************************************************************************
1491 //
1492 // The following are defines for the bit fields in the USB_O_TXTYPE2 register.
1493 //
1494 //*****************************************************************************
1495 #define USB_TXTYPE2_SPEED_M 0x000000C0 // Operating Speed
1496 #define USB_TXTYPE2_SPEED_DFLT 0x00000000 // Default
1497 #define USB_TXTYPE2_SPEED_HIGH 0x00000040 // High
1498 #define USB_TXTYPE2_SPEED_FULL 0x00000080 // Full
1499 #define USB_TXTYPE2_SPEED_LOW 0x000000C0 // Low
1500 #define USB_TXTYPE2_PROTO_M 0x00000030 // Protocol
1501 #define USB_TXTYPE2_PROTO_CTRL 0x00000000 // Control
1502 #define USB_TXTYPE2_PROTO_ISOC 0x00000010 // Isochronous
1503 #define USB_TXTYPE2_PROTO_BULK 0x00000020 // Bulk
1504 #define USB_TXTYPE2_PROTO_INT 0x00000030 // Interrupt
1505 #define USB_TXTYPE2_TEP_M 0x0000000F // Target Endpoint Number
1506 #define USB_TXTYPE2_TEP_S 0
1507 
1508 //*****************************************************************************
1509 //
1510 // The following are defines for the bit fields in the USB_O_TXINTERVAL2
1511 // register.
1512 //
1513 //*****************************************************************************
1514 #define USB_TXINTERVAL2_TXPOLL_M \
1515  0x000000FF // TX Polling
1516 #define USB_TXINTERVAL2_NAKLMT_M \
1517  0x000000FF // NAK Limit
1518 #define USB_TXINTERVAL2_NAKLMT_S \
1519  0
1520 #define USB_TXINTERVAL2_TXPOLL_S \
1521  0
1522 
1523 //*****************************************************************************
1524 //
1525 // The following are defines for the bit fields in the USB_O_RXTYPE2 register.
1526 //
1527 //*****************************************************************************
1528 #define USB_RXTYPE2_SPEED_M 0x000000C0 // Operating Speed
1529 #define USB_RXTYPE2_SPEED_DFLT 0x00000000 // Default
1530 #define USB_RXTYPE2_SPEED_HIGH 0x00000040 // High
1531 #define USB_RXTYPE2_SPEED_FULL 0x00000080 // Full
1532 #define USB_RXTYPE2_SPEED_LOW 0x000000C0 // Low
1533 #define USB_RXTYPE2_PROTO_M 0x00000030 // Protocol
1534 #define USB_RXTYPE2_PROTO_CTRL 0x00000000 // Control
1535 #define USB_RXTYPE2_PROTO_ISOC 0x00000010 // Isochronous
1536 #define USB_RXTYPE2_PROTO_BULK 0x00000020 // Bulk
1537 #define USB_RXTYPE2_PROTO_INT 0x00000030 // Interrupt
1538 #define USB_RXTYPE2_TEP_M 0x0000000F // Target Endpoint Number
1539 #define USB_RXTYPE2_TEP_S 0
1540 
1541 //*****************************************************************************
1542 //
1543 // The following are defines for the bit fields in the USB_O_RXINTERVAL2
1544 // register.
1545 //
1546 //*****************************************************************************
1547 #define USB_RXINTERVAL2_TXPOLL_M \
1548  0x000000FF // RX Polling
1549 #define USB_RXINTERVAL2_NAKLMT_M \
1550  0x000000FF // NAK Limit
1551 #define USB_RXINTERVAL2_TXPOLL_S \
1552  0
1553 #define USB_RXINTERVAL2_NAKLMT_S \
1554  0
1555 
1556 //*****************************************************************************
1557 //
1558 // The following are defines for the bit fields in the USB_O_TXMAXP3 register.
1559 //
1560 //*****************************************************************************
1561 #define USB_TXMAXP3_MAXLOAD_M 0x000007FF // Maximum Payload
1562 #define USB_TXMAXP3_MAXLOAD_S 0
1563 
1564 //*****************************************************************************
1565 //
1566 // The following are defines for the bit fields in the USB_O_TXCSRL3 register.
1567 //
1568 //*****************************************************************************
1569 #define USB_TXCSRL3_NAKTO 0x00000080 // NAK Timeout
1570 #define USB_TXCSRL3_CLRDT 0x00000040 // Clear Data Toggle
1571 #define USB_TXCSRL3_STALLED 0x00000020 // Endpoint Stalled
1572 #define USB_TXCSRL3_SETUP 0x00000010 // Setup Packet
1573 #define USB_TXCSRL3_STALL 0x00000010 // Send STALL
1574 #define USB_TXCSRL3_FLUSH 0x00000008 // Flush FIFO
1575 #define USB_TXCSRL3_ERROR 0x00000004 // Error
1576 #define USB_TXCSRL3_UNDRN 0x00000004 // Underrun
1577 #define USB_TXCSRL3_FIFONE 0x00000002 // FIFO Not Empty
1578 #define USB_TXCSRL3_TXRDY 0x00000001 // Transmit Packet Ready
1579 
1580 //*****************************************************************************
1581 //
1582 // The following are defines for the bit fields in the USB_O_TXCSRH3 register.
1583 //
1584 //*****************************************************************************
1585 #define USB_TXCSRH3_AUTOSET 0x00000080 // Auto Set
1586 #define USB_TXCSRH3_ISO 0x00000040 // Isochronous Transfers
1587 #define USB_TXCSRH3_MODE 0x00000020 // Mode
1588 #define USB_TXCSRH3_DMAEN 0x00000010 // DMA Request Enable
1589 #define USB_TXCSRH3_FDT 0x00000008 // Force Data Toggle
1590 #define USB_TXCSRH3_DMAMOD 0x00000004 // DMA Request Mode
1591 #define USB_TXCSRH3_DTWE 0x00000002 // Data Toggle Write Enable
1592 #define USB_TXCSRH3_DT 0x00000001 // Data Toggle
1593 
1594 //*****************************************************************************
1595 //
1596 // The following are defines for the bit fields in the USB_O_RXMAXP3 register.
1597 //
1598 //*****************************************************************************
1599 #define USB_RXMAXP3_MAXLOAD_M 0x000007FF // Maximum Payload
1600 #define USB_RXMAXP3_MAXLOAD_S 0
1601 
1602 //*****************************************************************************
1603 //
1604 // The following are defines for the bit fields in the USB_O_RXCSRL3 register.
1605 //
1606 //*****************************************************************************
1607 #define USB_RXCSRL3_CLRDT 0x00000080 // Clear Data Toggle
1608 #define USB_RXCSRL3_STALLED 0x00000040 // Endpoint Stalled
1609 #define USB_RXCSRL3_STALL 0x00000020 // Send STALL
1610 #define USB_RXCSRL3_REQPKT 0x00000020 // Request Packet
1611 #define USB_RXCSRL3_FLUSH 0x00000010 // Flush FIFO
1612 #define USB_RXCSRL3_DATAERR 0x00000008 // Data Error
1613 #define USB_RXCSRL3_NAKTO 0x00000008 // NAK Timeout
1614 #define USB_RXCSRL3_ERROR 0x00000004 // Error
1615 #define USB_RXCSRL3_OVER 0x00000004 // Overrun
1616 #define USB_RXCSRL3_FULL 0x00000002 // FIFO Full
1617 #define USB_RXCSRL3_RXRDY 0x00000001 // Receive Packet Ready
1618 
1619 //*****************************************************************************
1620 //
1621 // The following are defines for the bit fields in the USB_O_RXCSRH3 register.
1622 //
1623 //*****************************************************************************
1624 #define USB_RXCSRH3_AUTOCL 0x00000080 // Auto Clear
1625 #define USB_RXCSRH3_AUTORQ 0x00000040 // Auto Request
1626 #define USB_RXCSRH3_ISO 0x00000040 // Isochronous Transfers
1627 #define USB_RXCSRH3_DMAEN 0x00000020 // DMA Request Enable
1628 #define USB_RXCSRH3_DISNYET 0x00000010 // Disable NYET
1629 #define USB_RXCSRH3_PIDERR 0x00000010 // PID Error
1630 #define USB_RXCSRH3_DMAMOD 0x00000008 // DMA Request Mode
1631 #define USB_RXCSRH3_DTWE 0x00000004 // Data Toggle Write Enable
1632 #define USB_RXCSRH3_DT 0x00000002 // Data Toggle
1633 #define USB_RXCSRH3_INCOMPRX 0x00000001 // Incomplete RX Transmission
1634  // Status
1635 
1636 //*****************************************************************************
1637 //
1638 // The following are defines for the bit fields in the USB_O_RXCOUNT3 register.
1639 //
1640 //*****************************************************************************
1641 #define USB_RXCOUNT3_COUNT_M 0x00001FFF // Receive Packet Count
1642 #define USB_RXCOUNT3_COUNT_S 0
1643 
1644 //*****************************************************************************
1645 //
1646 // The following are defines for the bit fields in the USB_O_TXTYPE3 register.
1647 //
1648 //*****************************************************************************
1649 #define USB_TXTYPE3_SPEED_M 0x000000C0 // Operating Speed
1650 #define USB_TXTYPE3_SPEED_DFLT 0x00000000 // Default
1651 #define USB_TXTYPE3_SPEED_HIGH 0x00000040 // High
1652 #define USB_TXTYPE3_SPEED_FULL 0x00000080 // Full
1653 #define USB_TXTYPE3_SPEED_LOW 0x000000C0 // Low
1654 #define USB_TXTYPE3_PROTO_M 0x00000030 // Protocol
1655 #define USB_TXTYPE3_PROTO_CTRL 0x00000000 // Control
1656 #define USB_TXTYPE3_PROTO_ISOC 0x00000010 // Isochronous
1657 #define USB_TXTYPE3_PROTO_BULK 0x00000020 // Bulk
1658 #define USB_TXTYPE3_PROTO_INT 0x00000030 // Interrupt
1659 #define USB_TXTYPE3_TEP_M 0x0000000F // Target Endpoint Number
1660 #define USB_TXTYPE3_TEP_S 0
1661 
1662 //*****************************************************************************
1663 //
1664 // The following are defines for the bit fields in the USB_O_TXINTERVAL3
1665 // register.
1666 //
1667 //*****************************************************************************
1668 #define USB_TXINTERVAL3_TXPOLL_M \
1669  0x000000FF // TX Polling
1670 #define USB_TXINTERVAL3_NAKLMT_M \
1671  0x000000FF // NAK Limit
1672 #define USB_TXINTERVAL3_TXPOLL_S \
1673  0
1674 #define USB_TXINTERVAL3_NAKLMT_S \
1675  0
1676 
1677 //*****************************************************************************
1678 //
1679 // The following are defines for the bit fields in the USB_O_RXTYPE3 register.
1680 //
1681 //*****************************************************************************
1682 #define USB_RXTYPE3_SPEED_M 0x000000C0 // Operating Speed
1683 #define USB_RXTYPE3_SPEED_DFLT 0x00000000 // Default
1684 #define USB_RXTYPE3_SPEED_HIGH 0x00000040 // High
1685 #define USB_RXTYPE3_SPEED_FULL 0x00000080 // Full
1686 #define USB_RXTYPE3_SPEED_LOW 0x000000C0 // Low
1687 #define USB_RXTYPE3_PROTO_M 0x00000030 // Protocol
1688 #define USB_RXTYPE3_PROTO_CTRL 0x00000000 // Control
1689 #define USB_RXTYPE3_PROTO_ISOC 0x00000010 // Isochronous
1690 #define USB_RXTYPE3_PROTO_BULK 0x00000020 // Bulk
1691 #define USB_RXTYPE3_PROTO_INT 0x00000030 // Interrupt
1692 #define USB_RXTYPE3_TEP_M 0x0000000F // Target Endpoint Number
1693 #define USB_RXTYPE3_TEP_S 0
1694 
1695 //*****************************************************************************
1696 //
1697 // The following are defines for the bit fields in the USB_O_RXINTERVAL3
1698 // register.
1699 //
1700 //*****************************************************************************
1701 #define USB_RXINTERVAL3_TXPOLL_M \
1702  0x000000FF // RX Polling
1703 #define USB_RXINTERVAL3_NAKLMT_M \
1704  0x000000FF // NAK Limit
1705 #define USB_RXINTERVAL3_TXPOLL_S \
1706  0
1707 #define USB_RXINTERVAL3_NAKLMT_S \
1708  0
1709 
1710 //*****************************************************************************
1711 //
1712 // The following are defines for the bit fields in the USB_O_TXMAXP4 register.
1713 //
1714 //*****************************************************************************
1715 #define USB_TXMAXP4_MAXLOAD_M 0x000007FF // Maximum Payload
1716 #define USB_TXMAXP4_MAXLOAD_S 0
1717 
1718 //*****************************************************************************
1719 //
1720 // The following are defines for the bit fields in the USB_O_TXCSRL4 register.
1721 //
1722 //*****************************************************************************
1723 #define USB_TXCSRL4_NAKTO 0x00000080 // NAK Timeout
1724 #define USB_TXCSRL4_CLRDT 0x00000040 // Clear Data Toggle
1725 #define USB_TXCSRL4_STALLED 0x00000020 // Endpoint Stalled
1726 #define USB_TXCSRL4_SETUP 0x00000010 // Setup Packet
1727 #define USB_TXCSRL4_STALL 0x00000010 // Send STALL
1728 #define USB_TXCSRL4_FLUSH 0x00000008 // Flush FIFO
1729 #define USB_TXCSRL4_ERROR 0x00000004 // Error
1730 #define USB_TXCSRL4_UNDRN 0x00000004 // Underrun
1731 #define USB_TXCSRL4_FIFONE 0x00000002 // FIFO Not Empty
1732 #define USB_TXCSRL4_TXRDY 0x00000001 // Transmit Packet Ready
1733 
1734 //*****************************************************************************
1735 //
1736 // The following are defines for the bit fields in the USB_O_TXCSRH4 register.
1737 //
1738 //*****************************************************************************
1739 #define USB_TXCSRH4_AUTOSET 0x00000080 // Auto Set
1740 #define USB_TXCSRH4_ISO 0x00000040 // Isochronous Transfers
1741 #define USB_TXCSRH4_MODE 0x00000020 // Mode
1742 #define USB_TXCSRH4_DMAEN 0x00000010 // DMA Request Enable
1743 #define USB_TXCSRH4_FDT 0x00000008 // Force Data Toggle
1744 #define USB_TXCSRH4_DMAMOD 0x00000004 // DMA Request Mode
1745 #define USB_TXCSRH4_DTWE 0x00000002 // Data Toggle Write Enable
1746 #define USB_TXCSRH4_DT 0x00000001 // Data Toggle
1747 
1748 //*****************************************************************************
1749 //
1750 // The following are defines for the bit fields in the USB_O_RXMAXP4 register.
1751 //
1752 //*****************************************************************************
1753 #define USB_RXMAXP4_MAXLOAD_M 0x000007FF // Maximum Payload
1754 #define USB_RXMAXP4_MAXLOAD_S 0
1755 
1756 //*****************************************************************************
1757 //
1758 // The following are defines for the bit fields in the USB_O_RXCSRL4 register.
1759 //
1760 //*****************************************************************************
1761 #define USB_RXCSRL4_CLRDT 0x00000080 // Clear Data Toggle
1762 #define USB_RXCSRL4_STALLED 0x00000040 // Endpoint Stalled
1763 #define USB_RXCSRL4_STALL 0x00000020 // Send STALL
1764 #define USB_RXCSRL4_REQPKT 0x00000020 // Request Packet
1765 #define USB_RXCSRL4_FLUSH 0x00000010 // Flush FIFO
1766 #define USB_RXCSRL4_NAKTO 0x00000008 // NAK Timeout
1767 #define USB_RXCSRL4_DATAERR 0x00000008 // Data Error
1768 #define USB_RXCSRL4_OVER 0x00000004 // Overrun
1769 #define USB_RXCSRL4_ERROR 0x00000004 // Error
1770 #define USB_RXCSRL4_FULL 0x00000002 // FIFO Full
1771 #define USB_RXCSRL4_RXRDY 0x00000001 // Receive Packet Ready
1772 
1773 //*****************************************************************************
1774 //
1775 // The following are defines for the bit fields in the USB_O_RXCSRH4 register.
1776 //
1777 //*****************************************************************************
1778 #define USB_RXCSRH4_AUTOCL 0x00000080 // Auto Clear
1779 #define USB_RXCSRH4_AUTORQ 0x00000040 // Auto Request
1780 #define USB_RXCSRH4_ISO 0x00000040 // Isochronous Transfers
1781 #define USB_RXCSRH4_DMAEN 0x00000020 // DMA Request Enable
1782 #define USB_RXCSRH4_DISNYET 0x00000010 // Disable NYET
1783 #define USB_RXCSRH4_PIDERR 0x00000010 // PID Error
1784 #define USB_RXCSRH4_DMAMOD 0x00000008 // DMA Request Mode
1785 #define USB_RXCSRH4_DTWE 0x00000004 // Data Toggle Write Enable
1786 #define USB_RXCSRH4_DT 0x00000002 // Data Toggle
1787 #define USB_RXCSRH4_INCOMPRX 0x00000001 // Incomplete RX Transmission
1788  // Status
1789 
1790 //*****************************************************************************
1791 //
1792 // The following are defines for the bit fields in the USB_O_RXCOUNT4 register.
1793 //
1794 //*****************************************************************************
1795 #define USB_RXCOUNT4_COUNT_M 0x00001FFF // Receive Packet Count
1796 #define USB_RXCOUNT4_COUNT_S 0
1797 
1798 //*****************************************************************************
1799 //
1800 // The following are defines for the bit fields in the USB_O_TXTYPE4 register.
1801 //
1802 //*****************************************************************************
1803 #define USB_TXTYPE4_SPEED_M 0x000000C0 // Operating Speed
1804 #define USB_TXTYPE4_SPEED_DFLT 0x00000000 // Default
1805 #define USB_TXTYPE4_SPEED_HIGH 0x00000040 // High
1806 #define USB_TXTYPE4_SPEED_FULL 0x00000080 // Full
1807 #define USB_TXTYPE4_SPEED_LOW 0x000000C0 // Low
1808 #define USB_TXTYPE4_PROTO_M 0x00000030 // Protocol
1809 #define USB_TXTYPE4_PROTO_CTRL 0x00000000 // Control
1810 #define USB_TXTYPE4_PROTO_ISOC 0x00000010 // Isochronous
1811 #define USB_TXTYPE4_PROTO_BULK 0x00000020 // Bulk
1812 #define USB_TXTYPE4_PROTO_INT 0x00000030 // Interrupt
1813 #define USB_TXTYPE4_TEP_M 0x0000000F // Target Endpoint Number
1814 #define USB_TXTYPE4_TEP_S 0
1815 
1816 //*****************************************************************************
1817 //
1818 // The following are defines for the bit fields in the USB_O_TXINTERVAL4
1819 // register.
1820 //
1821 //*****************************************************************************
1822 #define USB_TXINTERVAL4_TXPOLL_M \
1823  0x000000FF // TX Polling
1824 #define USB_TXINTERVAL4_NAKLMT_M \
1825  0x000000FF // NAK Limit
1826 #define USB_TXINTERVAL4_NAKLMT_S \
1827  0
1828 #define USB_TXINTERVAL4_TXPOLL_S \
1829  0
1830 
1831 //*****************************************************************************
1832 //
1833 // The following are defines for the bit fields in the USB_O_RXTYPE4 register.
1834 //
1835 //*****************************************************************************
1836 #define USB_RXTYPE4_SPEED_M 0x000000C0 // Operating Speed
1837 #define USB_RXTYPE4_SPEED_DFLT 0x00000000 // Default
1838 #define USB_RXTYPE4_SPEED_HIGH 0x00000040 // High
1839 #define USB_RXTYPE4_SPEED_FULL 0x00000080 // Full
1840 #define USB_RXTYPE4_SPEED_LOW 0x000000C0 // Low
1841 #define USB_RXTYPE4_PROTO_M 0x00000030 // Protocol
1842 #define USB_RXTYPE4_PROTO_CTRL 0x00000000 // Control
1843 #define USB_RXTYPE4_PROTO_ISOC 0x00000010 // Isochronous
1844 #define USB_RXTYPE4_PROTO_BULK 0x00000020 // Bulk
1845 #define USB_RXTYPE4_PROTO_INT 0x00000030 // Interrupt
1846 #define USB_RXTYPE4_TEP_M 0x0000000F // Target Endpoint Number
1847 #define USB_RXTYPE4_TEP_S 0
1848 
1849 //*****************************************************************************
1850 //
1851 // The following are defines for the bit fields in the USB_O_RXINTERVAL4
1852 // register.
1853 //
1854 //*****************************************************************************
1855 #define USB_RXINTERVAL4_TXPOLL_M \
1856  0x000000FF // RX Polling
1857 #define USB_RXINTERVAL4_NAKLMT_M \
1858  0x000000FF // NAK Limit
1859 #define USB_RXINTERVAL4_NAKLMT_S \
1860  0
1861 #define USB_RXINTERVAL4_TXPOLL_S \
1862  0
1863 
1864 //*****************************************************************************
1865 //
1866 // The following are defines for the bit fields in the USB_O_TXMAXP5 register.
1867 //
1868 //*****************************************************************************
1869 #define USB_TXMAXP5_MAXLOAD_M 0x000007FF // Maximum Payload
1870 #define USB_TXMAXP5_MAXLOAD_S 0
1871 
1872 //*****************************************************************************
1873 //
1874 // The following are defines for the bit fields in the USB_O_TXCSRL5 register.
1875 //
1876 //*****************************************************************************
1877 #define USB_TXCSRL5_NAKTO 0x00000080 // NAK Timeout
1878 #define USB_TXCSRL5_CLRDT 0x00000040 // Clear Data Toggle
1879 #define USB_TXCSRL5_STALLED 0x00000020 // Endpoint Stalled
1880 #define USB_TXCSRL5_SETUP 0x00000010 // Setup Packet
1881 #define USB_TXCSRL5_STALL 0x00000010 // Send STALL
1882 #define USB_TXCSRL5_FLUSH 0x00000008 // Flush FIFO
1883 #define USB_TXCSRL5_ERROR 0x00000004 // Error
1884 #define USB_TXCSRL5_UNDRN 0x00000004 // Underrun
1885 #define USB_TXCSRL5_FIFONE 0x00000002 // FIFO Not Empty
1886 #define USB_TXCSRL5_TXRDY 0x00000001 // Transmit Packet Ready
1887 
1888 //*****************************************************************************
1889 //
1890 // The following are defines for the bit fields in the USB_O_TXCSRH5 register.
1891 //
1892 //*****************************************************************************
1893 #define USB_TXCSRH5_AUTOSET 0x00000080 // Auto Set
1894 #define USB_TXCSRH5_ISO 0x00000040 // Isochronous Transfers
1895 #define USB_TXCSRH5_MODE 0x00000020 // Mode
1896 #define USB_TXCSRH5_DMAEN 0x00000010 // DMA Request Enable
1897 #define USB_TXCSRH5_FDT 0x00000008 // Force Data Toggle
1898 #define USB_TXCSRH5_DMAMOD 0x00000004 // DMA Request Mode
1899 #define USB_TXCSRH5_DTWE 0x00000002 // Data Toggle Write Enable
1900 #define USB_TXCSRH5_DT 0x00000001 // Data Toggle
1901 
1902 //*****************************************************************************
1903 //
1904 // The following are defines for the bit fields in the USB_O_RXMAXP5 register.
1905 //
1906 //*****************************************************************************
1907 #define USB_RXMAXP5_MAXLOAD_M 0x000007FF // Maximum Payload
1908 #define USB_RXMAXP5_MAXLOAD_S 0
1909 
1910 //*****************************************************************************
1911 //
1912 // The following are defines for the bit fields in the USB_O_RXCSRL5 register.
1913 //
1914 //*****************************************************************************
1915 #define USB_RXCSRL5_CLRDT 0x00000080 // Clear Data Toggle
1916 #define USB_RXCSRL5_STALLED 0x00000040 // Endpoint Stalled
1917 #define USB_RXCSRL5_STALL 0x00000020 // Send STALL
1918 #define USB_RXCSRL5_REQPKT 0x00000020 // Request Packet
1919 #define USB_RXCSRL5_FLUSH 0x00000010 // Flush FIFO
1920 #define USB_RXCSRL5_NAKTO 0x00000008 // NAK Timeout
1921 #define USB_RXCSRL5_DATAERR 0x00000008 // Data Error
1922 #define USB_RXCSRL5_ERROR 0x00000004 // Error
1923 #define USB_RXCSRL5_OVER 0x00000004 // Overrun
1924 #define USB_RXCSRL5_FULL 0x00000002 // FIFO Full
1925 #define USB_RXCSRL5_RXRDY 0x00000001 // Receive Packet Ready
1926 
1927 //*****************************************************************************
1928 //
1929 // The following are defines for the bit fields in the USB_O_RXCSRH5 register.
1930 //
1931 //*****************************************************************************
1932 #define USB_RXCSRH5_AUTOCL 0x00000080 // Auto Clear
1933 #define USB_RXCSRH5_AUTORQ 0x00000040 // Auto Request
1934 #define USB_RXCSRH5_ISO 0x00000040 // Isochronous Transfers
1935 #define USB_RXCSRH5_DMAEN 0x00000020 // DMA Request Enable
1936 #define USB_RXCSRH5_DISNYET 0x00000010 // Disable NYET
1937 #define USB_RXCSRH5_PIDERR 0x00000010 // PID Error
1938 #define USB_RXCSRH5_DMAMOD 0x00000008 // DMA Request Mode
1939 #define USB_RXCSRH5_DTWE 0x00000004 // Data Toggle Write Enable
1940 #define USB_RXCSRH5_DT 0x00000002 // Data Toggle
1941 #define USB_RXCSRH5_INCOMPRX 0x00000001 // Incomplete RX Transmission
1942  // Status
1943 
1944 //*****************************************************************************
1945 //
1946 // The following are defines for the bit fields in the USB_O_RXCOUNT5 register.
1947 //
1948 //*****************************************************************************
1949 #define USB_RXCOUNT5_COUNT_M 0x00001FFF // Receive Packet Count
1950 #define USB_RXCOUNT5_COUNT_S 0
1951 
1952 //*****************************************************************************
1953 //
1954 // The following are defines for the bit fields in the USB_O_TXTYPE5 register.
1955 //
1956 //*****************************************************************************
1957 #define USB_TXTYPE5_SPEED_M 0x000000C0 // Operating Speed
1958 #define USB_TXTYPE5_SPEED_DFLT 0x00000000 // Default
1959 #define USB_TXTYPE5_SPEED_HIGH 0x00000040 // High
1960 #define USB_TXTYPE5_SPEED_FULL 0x00000080 // Full
1961 #define USB_TXTYPE5_SPEED_LOW 0x000000C0 // Low
1962 #define USB_TXTYPE5_PROTO_M 0x00000030 // Protocol
1963 #define USB_TXTYPE5_PROTO_CTRL 0x00000000 // Control
1964 #define USB_TXTYPE5_PROTO_ISOC 0x00000010 // Isochronous
1965 #define USB_TXTYPE5_PROTO_BULK 0x00000020 // Bulk
1966 #define USB_TXTYPE5_PROTO_INT 0x00000030 // Interrupt
1967 #define USB_TXTYPE5_TEP_M 0x0000000F // Target Endpoint Number
1968 #define USB_TXTYPE5_TEP_S 0
1969 
1970 //*****************************************************************************
1971 //
1972 // The following are defines for the bit fields in the USB_O_TXINTERVAL5
1973 // register.
1974 //
1975 //*****************************************************************************
1976 #define USB_TXINTERVAL5_TXPOLL_M \
1977  0x000000FF // TX Polling
1978 #define USB_TXINTERVAL5_NAKLMT_M \
1979  0x000000FF // NAK Limit
1980 #define USB_TXINTERVAL5_NAKLMT_S \
1981  0
1982 #define USB_TXINTERVAL5_TXPOLL_S \
1983  0
1984 
1985 //*****************************************************************************
1986 //
1987 // The following are defines for the bit fields in the USB_O_RXTYPE5 register.
1988 //
1989 //*****************************************************************************
1990 #define USB_RXTYPE5_SPEED_M 0x000000C0 // Operating Speed
1991 #define USB_RXTYPE5_SPEED_DFLT 0x00000000 // Default
1992 #define USB_RXTYPE5_SPEED_HIGH 0x00000040 // High
1993 #define USB_RXTYPE5_SPEED_FULL 0x00000080 // Full
1994 #define USB_RXTYPE5_SPEED_LOW 0x000000C0 // Low
1995 #define USB_RXTYPE5_PROTO_M 0x00000030 // Protocol
1996 #define USB_RXTYPE5_PROTO_CTRL 0x00000000 // Control
1997 #define USB_RXTYPE5_PROTO_ISOC 0x00000010 // Isochronous
1998 #define USB_RXTYPE5_PROTO_BULK 0x00000020 // Bulk
1999 #define USB_RXTYPE5_PROTO_INT 0x00000030 // Interrupt
2000 #define USB_RXTYPE5_TEP_M 0x0000000F // Target Endpoint Number
2001 #define USB_RXTYPE5_TEP_S 0
2002 
2003 //*****************************************************************************
2004 //
2005 // The following are defines for the bit fields in the USB_O_RXINTERVAL5
2006 // register.
2007 //
2008 //*****************************************************************************
2009 #define USB_RXINTERVAL5_TXPOLL_M \
2010  0x000000FF // RX Polling
2011 #define USB_RXINTERVAL5_NAKLMT_M \
2012  0x000000FF // NAK Limit
2013 #define USB_RXINTERVAL5_TXPOLL_S \
2014  0
2015 #define USB_RXINTERVAL5_NAKLMT_S \
2016  0
2017 
2018 //*****************************************************************************
2019 //
2020 // The following are defines for the bit fields in the USB_O_TXMAXP6 register.
2021 //
2022 //*****************************************************************************
2023 #define USB_TXMAXP6_MAXLOAD_M 0x000007FF // Maximum Payload
2024 #define USB_TXMAXP6_MAXLOAD_S 0
2025 
2026 //*****************************************************************************
2027 //
2028 // The following are defines for the bit fields in the USB_O_TXCSRL6 register.
2029 //
2030 //*****************************************************************************
2031 #define USB_TXCSRL6_NAKTO 0x00000080 // NAK Timeout
2032 #define USB_TXCSRL6_CLRDT 0x00000040 // Clear Data Toggle
2033 #define USB_TXCSRL6_STALLED 0x00000020 // Endpoint Stalled
2034 #define USB_TXCSRL6_STALL 0x00000010 // Send STALL
2035 #define USB_TXCSRL6_SETUP 0x00000010 // Setup Packet
2036 #define USB_TXCSRL6_FLUSH 0x00000008 // Flush FIFO
2037 #define USB_TXCSRL6_ERROR 0x00000004 // Error
2038 #define USB_TXCSRL6_UNDRN 0x00000004 // Underrun
2039 #define USB_TXCSRL6_FIFONE 0x00000002 // FIFO Not Empty
2040 #define USB_TXCSRL6_TXRDY 0x00000001 // Transmit Packet Ready
2041 
2042 //*****************************************************************************
2043 //
2044 // The following are defines for the bit fields in the USB_O_TXCSRH6 register.
2045 //
2046 //*****************************************************************************
2047 #define USB_TXCSRH6_AUTOSET 0x00000080 // Auto Set
2048 #define USB_TXCSRH6_ISO 0x00000040 // Isochronous Transfers
2049 #define USB_TXCSRH6_MODE 0x00000020 // Mode
2050 #define USB_TXCSRH6_DMAEN 0x00000010 // DMA Request Enable
2051 #define USB_TXCSRH6_FDT 0x00000008 // Force Data Toggle
2052 #define USB_TXCSRH6_DMAMOD 0x00000004 // DMA Request Mode
2053 #define USB_TXCSRH6_DTWE 0x00000002 // Data Toggle Write Enable
2054 #define USB_TXCSRH6_DT 0x00000001 // Data Toggle
2055 
2056 //*****************************************************************************
2057 //
2058 // The following are defines for the bit fields in the USB_O_RXMAXP6 register.
2059 //
2060 //*****************************************************************************
2061 #define USB_RXMAXP6_MAXLOAD_M 0x000007FF // Maximum Payload
2062 #define USB_RXMAXP6_MAXLOAD_S 0
2063 
2064 //*****************************************************************************
2065 //
2066 // The following are defines for the bit fields in the USB_O_RXCSRL6 register.
2067 //
2068 //*****************************************************************************
2069 #define USB_RXCSRL6_CLRDT 0x00000080 // Clear Data Toggle
2070 #define USB_RXCSRL6_STALLED 0x00000040 // Endpoint Stalled
2071 #define USB_RXCSRL6_REQPKT 0x00000020 // Request Packet
2072 #define USB_RXCSRL6_STALL 0x00000020 // Send STALL
2073 #define USB_RXCSRL6_FLUSH 0x00000010 // Flush FIFO
2074 #define USB_RXCSRL6_NAKTO 0x00000008 // NAK Timeout
2075 #define USB_RXCSRL6_DATAERR 0x00000008 // Data Error
2076 #define USB_RXCSRL6_ERROR 0x00000004 // Error
2077 #define USB_RXCSRL6_OVER 0x00000004 // Overrun
2078 #define USB_RXCSRL6_FULL 0x00000002 // FIFO Full
2079 #define USB_RXCSRL6_RXRDY 0x00000001 // Receive Packet Ready
2080 
2081 //*****************************************************************************
2082 //
2083 // The following are defines for the bit fields in the USB_O_RXCSRH6 register.
2084 //
2085 //*****************************************************************************
2086 #define USB_RXCSRH6_AUTOCL 0x00000080 // Auto Clear
2087 #define USB_RXCSRH6_AUTORQ 0x00000040 // Auto Request
2088 #define USB_RXCSRH6_ISO 0x00000040 // Isochronous Transfers
2089 #define USB_RXCSRH6_DMAEN 0x00000020 // DMA Request Enable
2090 #define USB_RXCSRH6_DISNYET 0x00000010 // Disable NYET
2091 #define USB_RXCSRH6_PIDERR 0x00000010 // PID Error
2092 #define USB_RXCSRH6_DMAMOD 0x00000008 // DMA Request Mode
2093 #define USB_RXCSRH6_DTWE 0x00000004 // Data Toggle Write Enable
2094 #define USB_RXCSRH6_DT 0x00000002 // Data Toggle
2095 #define USB_RXCSRH6_INCOMPRX 0x00000001 // Incomplete RX Transmission
2096  // Status
2097 
2098 //*****************************************************************************
2099 //
2100 // The following are defines for the bit fields in the USB_O_RXCOUNT6 register.
2101 //
2102 //*****************************************************************************
2103 #define USB_RXCOUNT6_COUNT_M 0x00001FFF // Receive Packet Count
2104 #define USB_RXCOUNT6_COUNT_S 0
2105 
2106 //*****************************************************************************
2107 //
2108 // The following are defines for the bit fields in the USB_O_TXTYPE6 register.
2109 //
2110 //*****************************************************************************
2111 #define USB_TXTYPE6_SPEED_M 0x000000C0 // Operating Speed
2112 #define USB_TXTYPE6_SPEED_DFLT 0x00000000 // Default
2113 #define USB_TXTYPE6_SPEED_HIGH 0x00000040 // High
2114 #define USB_TXTYPE6_SPEED_FULL 0x00000080 // Full
2115 #define USB_TXTYPE6_SPEED_LOW 0x000000C0 // Low
2116 #define USB_TXTYPE6_PROTO_M 0x00000030 // Protocol
2117 #define USB_TXTYPE6_PROTO_CTRL 0x00000000 // Control
2118 #define USB_TXTYPE6_PROTO_ISOC 0x00000010 // Isochronous
2119 #define USB_TXTYPE6_PROTO_BULK 0x00000020 // Bulk
2120 #define USB_TXTYPE6_PROTO_INT 0x00000030 // Interrupt
2121 #define USB_TXTYPE6_TEP_M 0x0000000F // Target Endpoint Number
2122 #define USB_TXTYPE6_TEP_S 0
2123 
2124 //*****************************************************************************
2125 //
2126 // The following are defines for the bit fields in the USB_O_TXINTERVAL6
2127 // register.
2128 //
2129 //*****************************************************************************
2130 #define USB_TXINTERVAL6_TXPOLL_M \
2131  0x000000FF // TX Polling
2132 #define USB_TXINTERVAL6_NAKLMT_M \
2133  0x000000FF // NAK Limit
2134 #define USB_TXINTERVAL6_TXPOLL_S \
2135  0
2136 #define USB_TXINTERVAL6_NAKLMT_S \
2137  0
2138 
2139 //*****************************************************************************
2140 //
2141 // The following are defines for the bit fields in the USB_O_RXTYPE6 register.
2142 //
2143 //*****************************************************************************
2144 #define USB_RXTYPE6_SPEED_M 0x000000C0 // Operating Speed
2145 #define USB_RXTYPE6_SPEED_DFLT 0x00000000 // Default
2146 #define USB_RXTYPE6_SPEED_HIGH 0x00000040 // High
2147 #define USB_RXTYPE6_SPEED_FULL 0x00000080 // Full
2148 #define USB_RXTYPE6_SPEED_LOW 0x000000C0 // Low
2149 #define USB_RXTYPE6_PROTO_M 0x00000030 // Protocol
2150 #define USB_RXTYPE6_PROTO_CTRL 0x00000000 // Control
2151 #define USB_RXTYPE6_PROTO_ISOC 0x00000010 // Isochronous
2152 #define USB_RXTYPE6_PROTO_BULK 0x00000020 // Bulk
2153 #define USB_RXTYPE6_PROTO_INT 0x00000030 // Interrupt
2154 #define USB_RXTYPE6_TEP_M 0x0000000F // Target Endpoint Number
2155 #define USB_RXTYPE6_TEP_S 0
2156 
2157 //*****************************************************************************
2158 //
2159 // The following are defines for the bit fields in the USB_O_RXINTERVAL6
2160 // register.
2161 //
2162 //*****************************************************************************
2163 #define USB_RXINTERVAL6_TXPOLL_M \
2164  0x000000FF // RX Polling
2165 #define USB_RXINTERVAL6_NAKLMT_M \
2166  0x000000FF // NAK Limit
2167 #define USB_RXINTERVAL6_NAKLMT_S \
2168  0
2169 #define USB_RXINTERVAL6_TXPOLL_S \
2170  0
2171 
2172 //*****************************************************************************
2173 //
2174 // The following are defines for the bit fields in the USB_O_TXMAXP7 register.
2175 //
2176 //*****************************************************************************
2177 #define USB_TXMAXP7_MAXLOAD_M 0x000007FF // Maximum Payload
2178 #define USB_TXMAXP7_MAXLOAD_S 0
2179 
2180 //*****************************************************************************
2181 //
2182 // The following are defines for the bit fields in the USB_O_TXCSRL7 register.
2183 //
2184 //*****************************************************************************
2185 #define USB_TXCSRL7_NAKTO 0x00000080 // NAK Timeout
2186 #define USB_TXCSRL7_CLRDT 0x00000040 // Clear Data Toggle
2187 #define USB_TXCSRL7_STALLED 0x00000020 // Endpoint Stalled
2188 #define USB_TXCSRL7_STALL 0x00000010 // Send STALL
2189 #define USB_TXCSRL7_SETUP 0x00000010 // Setup Packet
2190 #define USB_TXCSRL7_FLUSH 0x00000008 // Flush FIFO
2191 #define USB_TXCSRL7_ERROR 0x00000004 // Error
2192 #define USB_TXCSRL7_UNDRN 0x00000004 // Underrun
2193 #define USB_TXCSRL7_FIFONE 0x00000002 // FIFO Not Empty
2194 #define USB_TXCSRL7_TXRDY 0x00000001 // Transmit Packet Ready
2195 
2196 //*****************************************************************************
2197 //
2198 // The following are defines for the bit fields in the USB_O_TXCSRH7 register.
2199 //
2200 //*****************************************************************************
2201 #define USB_TXCSRH7_AUTOSET 0x00000080 // Auto Set
2202 #define USB_TXCSRH7_ISO 0x00000040 // Isochronous Transfers
2203 #define USB_TXCSRH7_MODE 0x00000020 // Mode
2204 #define USB_TXCSRH7_DMAEN 0x00000010 // DMA Request Enable
2205 #define USB_TXCSRH7_FDT 0x00000008 // Force Data Toggle
2206 #define USB_TXCSRH7_DMAMOD 0x00000004 // DMA Request Mode
2207 #define USB_TXCSRH7_DTWE 0x00000002 // Data Toggle Write Enable
2208 #define USB_TXCSRH7_DT 0x00000001 // Data Toggle
2209 
2210 //*****************************************************************************
2211 //
2212 // The following are defines for the bit fields in the USB_O_RXMAXP7 register.
2213 //
2214 //*****************************************************************************
2215 #define USB_RXMAXP7_MAXLOAD_M 0x000007FF // Maximum Payload
2216 #define USB_RXMAXP7_MAXLOAD_S 0
2217 
2218 //*****************************************************************************
2219 //
2220 // The following are defines for the bit fields in the USB_O_RXCSRL7 register.
2221 //
2222 //*****************************************************************************
2223 #define USB_RXCSRL7_CLRDT 0x00000080 // Clear Data Toggle
2224 #define USB_RXCSRL7_STALLED 0x00000040 // Endpoint Stalled
2225 #define USB_RXCSRL7_REQPKT 0x00000020 // Request Packet
2226 #define USB_RXCSRL7_STALL 0x00000020 // Send STALL
2227 #define USB_RXCSRL7_FLUSH 0x00000010 // Flush FIFO
2228 #define USB_RXCSRL7_DATAERR 0x00000008 // Data Error
2229 #define USB_RXCSRL7_NAKTO 0x00000008 // NAK Timeout
2230 #define USB_RXCSRL7_ERROR 0x00000004 // Error
2231 #define USB_RXCSRL7_OVER 0x00000004 // Overrun
2232 #define USB_RXCSRL7_FULL 0x00000002 // FIFO Full
2233 #define USB_RXCSRL7_RXRDY 0x00000001 // Receive Packet Ready
2234 
2235 //*****************************************************************************
2236 //
2237 // The following are defines for the bit fields in the USB_O_RXCSRH7 register.
2238 //
2239 //*****************************************************************************
2240 #define USB_RXCSRH7_AUTOCL 0x00000080 // Auto Clear
2241 #define USB_RXCSRH7_ISO 0x00000040 // Isochronous Transfers
2242 #define USB_RXCSRH7_AUTORQ 0x00000040 // Auto Request
2243 #define USB_RXCSRH7_DMAEN 0x00000020 // DMA Request Enable
2244 #define USB_RXCSRH7_PIDERR 0x00000010 // PID Error
2245 #define USB_RXCSRH7_DISNYET 0x00000010 // Disable NYET
2246 #define USB_RXCSRH7_DMAMOD 0x00000008 // DMA Request Mode
2247 #define USB_RXCSRH7_DTWE 0x00000004 // Data Toggle Write Enable
2248 #define USB_RXCSRH7_DT 0x00000002 // Data Toggle
2249 #define USB_RXCSRH7_INCOMPRX 0x00000001 // Incomplete RX Transmission
2250  // Status
2251 
2252 //*****************************************************************************
2253 //
2254 // The following are defines for the bit fields in the USB_O_RXCOUNT7 register.
2255 //
2256 //*****************************************************************************
2257 #define USB_RXCOUNT7_COUNT_M 0x00001FFF // Receive Packet Count
2258 #define USB_RXCOUNT7_COUNT_S 0
2259 
2260 //*****************************************************************************
2261 //
2262 // The following are defines for the bit fields in the USB_O_TXTYPE7 register.
2263 //
2264 //*****************************************************************************
2265 #define USB_TXTYPE7_SPEED_M 0x000000C0 // Operating Speed
2266 #define USB_TXTYPE7_SPEED_DFLT 0x00000000 // Default
2267 #define USB_TXTYPE7_SPEED_HIGH 0x00000040 // High
2268 #define USB_TXTYPE7_SPEED_FULL 0x00000080 // Full
2269 #define USB_TXTYPE7_SPEED_LOW 0x000000C0 // Low
2270 #define USB_TXTYPE7_PROTO_M 0x00000030 // Protocol
2271 #define USB_TXTYPE7_PROTO_CTRL 0x00000000 // Control
2272 #define USB_TXTYPE7_PROTO_ISOC 0x00000010 // Isochronous
2273 #define USB_TXTYPE7_PROTO_BULK 0x00000020 // Bulk
2274 #define USB_TXTYPE7_PROTO_INT 0x00000030 // Interrupt
2275 #define USB_TXTYPE7_TEP_M 0x0000000F // Target Endpoint Number
2276 #define USB_TXTYPE7_TEP_S 0
2277 
2278 //*****************************************************************************
2279 //
2280 // The following are defines for the bit fields in the USB_O_TXINTERVAL7
2281 // register.
2282 //
2283 //*****************************************************************************
2284 #define USB_TXINTERVAL7_TXPOLL_M \
2285  0x000000FF // TX Polling
2286 #define USB_TXINTERVAL7_NAKLMT_M \
2287  0x000000FF // NAK Limit
2288 #define USB_TXINTERVAL7_NAKLMT_S \
2289  0
2290 #define USB_TXINTERVAL7_TXPOLL_S \
2291  0
2292 
2293 //*****************************************************************************
2294 //
2295 // The following are defines for the bit fields in the USB_O_RXTYPE7 register.
2296 //
2297 //*****************************************************************************
2298 #define USB_RXTYPE7_SPEED_M 0x000000C0 // Operating Speed
2299 #define USB_RXTYPE7_SPEED_DFLT 0x00000000 // Default
2300 #define USB_RXTYPE7_SPEED_HIGH 0x00000040 // High
2301 #define USB_RXTYPE7_SPEED_FULL 0x00000080 // Full
2302 #define USB_RXTYPE7_SPEED_LOW 0x000000C0 // Low
2303 #define USB_RXTYPE7_PROTO_M 0x00000030 // Protocol
2304 #define USB_RXTYPE7_PROTO_CTRL 0x00000000 // Control
2305 #define USB_RXTYPE7_PROTO_ISOC 0x00000010 // Isochronous
2306 #define USB_RXTYPE7_PROTO_BULK 0x00000020 // Bulk
2307 #define USB_RXTYPE7_PROTO_INT 0x00000030 // Interrupt
2308 #define USB_RXTYPE7_TEP_M 0x0000000F // Target Endpoint Number
2309 #define USB_RXTYPE7_TEP_S 0
2310 
2311 //*****************************************************************************
2312 //
2313 // The following are defines for the bit fields in the USB_O_RXINTERVAL7
2314 // register.
2315 //
2316 //*****************************************************************************
2317 #define USB_RXINTERVAL7_TXPOLL_M \
2318  0x000000FF // RX Polling
2319 #define USB_RXINTERVAL7_NAKLMT_M \
2320  0x000000FF // NAK Limit
2321 #define USB_RXINTERVAL7_NAKLMT_S \
2322  0
2323 #define USB_RXINTERVAL7_TXPOLL_S \
2324  0
2325 
2326 //*****************************************************************************
2327 //
2328 // The following are defines for the bit fields in the USB_O_DMAINTR register.
2329 //
2330 //*****************************************************************************
2331 #define USB_DMAINTR_CH7 0x00000080 // Channel 7 DMA Interrupt
2332 #define USB_DMAINTR_CH6 0x00000040 // Channel 6 DMA Interrupt
2333 #define USB_DMAINTR_CH5 0x00000020 // Channel 5 DMA Interrupt
2334 #define USB_DMAINTR_CH4 0x00000010 // Channel 4 DMA Interrupt
2335 #define USB_DMAINTR_CH3 0x00000008 // Channel 3 DMA Interrupt
2336 #define USB_DMAINTR_CH2 0x00000004 // Channel 2 DMA Interrupt
2337 #define USB_DMAINTR_CH1 0x00000002 // Channel 1 DMA Interrupt
2338 #define USB_DMAINTR_CH0 0x00000001 // Channel 0 DMA Interrupt
2339 
2340 //*****************************************************************************
2341 //
2342 // The following are defines for the bit fields in the USB_O_DMACTL0 register.
2343 //
2344 //*****************************************************************************
2345 #define USB_DMACTL0_BRSTM_M 0x00000600 // Burst Mode
2346 #define USB_DMACTL0_BRSTM_ANY 0x00000000 // Bursts of unspecified length
2347 #define USB_DMACTL0_BRSTM_INC4 0x00000200 // INCR4 or unspecified length
2348 #define USB_DMACTL0_BRSTM_INC8 0x00000400 // INCR8, INCR4 or unspecified
2349  // length
2350 #define USB_DMACTL0_BRSTM_INC16 0x00000600 // INCR16, INCR8, INCR4 or
2351  // unspecified length
2352 #define USB_DMACTL0_ERR 0x00000100 // Bus Error Bit
2353 #define USB_DMACTL0_EP_M 0x000000F0 // Endpoint number
2354 #define USB_DMACTL0_IE 0x00000008 // DMA Interrupt Enable
2355 #define USB_DMACTL0_MODE 0x00000004 // DMA Transfer Mode
2356 #define USB_DMACTL0_DIR 0x00000002 // DMA Direction
2357 #define USB_DMACTL0_ENABLE 0x00000001 // DMA Transfer Enable
2358 #define USB_DMACTL0_EP_S 4
2359 
2360 //*****************************************************************************
2361 //
2362 // The following are defines for the bit fields in the USB_O_DMAADDR0 register.
2363 //
2364 //*****************************************************************************
2365 #define USB_DMAADDR0_ADDR_M 0xFFFFFFFC // DMA Address
2366 #define USB_DMAADDR0_ADDR_S 2
2367 
2368 //*****************************************************************************
2369 //
2370 // The following are defines for the bit fields in the USB_O_DMACOUNT0
2371 // register.
2372 //
2373 //*****************************************************************************
2374 #define USB_DMACOUNT0_COUNT_M 0xFFFFFFFC // DMA Count
2375 #define USB_DMACOUNT0_COUNT_S 2
2376 
2377 //*****************************************************************************
2378 //
2379 // The following are defines for the bit fields in the USB_O_DMACTL1 register.
2380 //
2381 //*****************************************************************************
2382 #define USB_DMACTL1_BRSTM_M 0x00000600 // Burst Mode
2383 #define USB_DMACTL1_BRSTM_ANY 0x00000000 // Bursts of unspecified length
2384 #define USB_DMACTL1_BRSTM_INC4 0x00000200 // INCR4 or unspecified length
2385 #define USB_DMACTL1_BRSTM_INC8 0x00000400 // INCR8, INCR4 or unspecified
2386  // length
2387 #define USB_DMACTL1_BRSTM_INC16 0x00000600 // INCR16, INCR8, INCR4 or
2388  // unspecified length
2389 #define USB_DMACTL1_ERR 0x00000100 // Bus Error Bit
2390 #define USB_DMACTL1_EP_M 0x000000F0 // Endpoint number
2391 #define USB_DMACTL1_IE 0x00000008 // DMA Interrupt Enable
2392 #define USB_DMACTL1_MODE 0x00000004 // DMA Transfer Mode
2393 #define USB_DMACTL1_DIR 0x00000002 // DMA Direction
2394 #define USB_DMACTL1_ENABLE 0x00000001 // DMA Transfer Enable
2395 #define USB_DMACTL1_EP_S 4
2396 
2397 //*****************************************************************************
2398 //
2399 // The following are defines for the bit fields in the USB_O_DMAADDR1 register.
2400 //
2401 //*****************************************************************************
2402 #define USB_DMAADDR1_ADDR_M 0xFFFFFFFC // DMA Address
2403 #define USB_DMAADDR1_ADDR_S 2
2404 
2405 //*****************************************************************************
2406 //
2407 // The following are defines for the bit fields in the USB_O_DMACOUNT1
2408 // register.
2409 //
2410 //*****************************************************************************
2411 #define USB_DMACOUNT1_COUNT_M 0xFFFFFFFC // DMA Count
2412 #define USB_DMACOUNT1_COUNT_S 2
2413 
2414 //*****************************************************************************
2415 //
2416 // The following are defines for the bit fields in the USB_O_DMACTL2 register.
2417 //
2418 //*****************************************************************************
2419 #define USB_DMACTL2_BRSTM_M 0x00000600 // Burst Mode
2420 #define USB_DMACTL2_BRSTM_ANY 0x00000000 // Bursts of unspecified length
2421 #define USB_DMACTL2_BRSTM_INC4 0x00000200 // INCR4 or unspecified length
2422 #define USB_DMACTL2_BRSTM_INC8 0x00000400 // INCR8, INCR4 or unspecified
2423  // length
2424 #define USB_DMACTL2_BRSTM_INC16 0x00000600 // INCR16, INCR8, INCR4 or
2425  // unspecified length
2426 #define USB_DMACTL2_ERR 0x00000100 // Bus Error Bit
2427 #define USB_DMACTL2_EP_M 0x000000F0 // Endpoint number
2428 #define USB_DMACTL2_IE 0x00000008 // DMA Interrupt Enable
2429 #define USB_DMACTL2_MODE 0x00000004 // DMA Transfer Mode
2430 #define USB_DMACTL2_DIR 0x00000002 // DMA Direction
2431 #define USB_DMACTL2_ENABLE 0x00000001 // DMA Transfer Enable
2432 #define USB_DMACTL2_EP_S 4
2433 
2434 //*****************************************************************************
2435 //
2436 // The following are defines for the bit fields in the USB_O_DMAADDR2 register.
2437 //
2438 //*****************************************************************************
2439 #define USB_DMAADDR2_ADDR_M 0xFFFFFFFC // DMA Address
2440 #define USB_DMAADDR2_ADDR_S 2
2441 
2442 //*****************************************************************************
2443 //
2444 // The following are defines for the bit fields in the USB_O_DMACOUNT2
2445 // register.
2446 //
2447 //*****************************************************************************
2448 #define USB_DMACOUNT2_COUNT_M 0xFFFFFFFC // DMA Count
2449 #define USB_DMACOUNT2_COUNT_S 2
2450 
2451 //*****************************************************************************
2452 //
2453 // The following are defines for the bit fields in the USB_O_DMACTL3 register.
2454 //
2455 //*****************************************************************************
2456 #define USB_DMACTL3_BRSTM_M 0x00000600 // Burst Mode
2457 #define USB_DMACTL3_BRSTM_ANY 0x00000000 // Bursts of unspecified length
2458 #define USB_DMACTL3_BRSTM_INC4 0x00000200 // INCR4 or unspecified length
2459 #define USB_DMACTL3_BRSTM_INC8 0x00000400 // INCR8, INCR4 or unspecified
2460  // length
2461 #define USB_DMACTL3_BRSTM_INC16 0x00000600 // INCR16, INCR8, INCR4 or
2462  // unspecified length
2463 #define USB_DMACTL3_ERR 0x00000100 // Bus Error Bit
2464 #define USB_DMACTL3_EP_M 0x000000F0 // Endpoint number
2465 #define USB_DMACTL3_IE 0x00000008 // DMA Interrupt Enable
2466 #define USB_DMACTL3_MODE 0x00000004 // DMA Transfer Mode
2467 #define USB_DMACTL3_DIR 0x00000002 // DMA Direction
2468 #define USB_DMACTL3_ENABLE 0x00000001 // DMA Transfer Enable
2469 #define USB_DMACTL3_EP_S 4
2470 
2471 //*****************************************************************************
2472 //
2473 // The following are defines for the bit fields in the USB_O_DMAADDR3 register.
2474 //
2475 //*****************************************************************************
2476 #define USB_DMAADDR3_ADDR_M 0xFFFFFFFC // DMA Address
2477 #define USB_DMAADDR3_ADDR_S 2
2478 
2479 //*****************************************************************************
2480 //
2481 // The following are defines for the bit fields in the USB_O_DMACOUNT3
2482 // register.
2483 //
2484 //*****************************************************************************
2485 #define USB_DMACOUNT3_COUNT_M 0xFFFFFFFC // DMA Count
2486 #define USB_DMACOUNT3_COUNT_S 2
2487 
2488 //*****************************************************************************
2489 //
2490 // The following are defines for the bit fields in the USB_O_DMACTL4 register.
2491 //
2492 //*****************************************************************************
2493 #define USB_DMACTL4_BRSTM_M 0x00000600 // Burst Mode
2494 #define USB_DMACTL4_BRSTM_ANY 0x00000000 // Bursts of unspecified length
2495 #define USB_DMACTL4_BRSTM_INC4 0x00000200 // INCR4 or unspecified length
2496 #define USB_DMACTL4_BRSTM_INC8 0x00000400 // INCR8, INCR4 or unspecified
2497  // length
2498 #define USB_DMACTL4_BRSTM_INC16 0x00000600 // INCR16, INCR8, INCR4 or
2499  // unspecified length
2500 #define USB_DMACTL4_ERR 0x00000100 // Bus Error Bit
2501 #define USB_DMACTL4_EP_M 0x000000F0 // Endpoint number
2502 #define USB_DMACTL4_IE 0x00000008 // DMA Interrupt Enable
2503 #define USB_DMACTL4_MODE 0x00000004 // DMA Transfer Mode
2504 #define USB_DMACTL4_DIR 0x00000002 // DMA Direction
2505 #define USB_DMACTL4_ENABLE 0x00000001 // DMA Transfer Enable
2506 #define USB_DMACTL4_EP_S 4
2507 
2508 //*****************************************************************************
2509 //
2510 // The following are defines for the bit fields in the USB_O_DMAADDR4 register.
2511 //
2512 //*****************************************************************************
2513 #define USB_DMAADDR4_ADDR_M 0xFFFFFFFC // DMA Address
2514 #define USB_DMAADDR4_ADDR_S 2
2515 
2516 //*****************************************************************************
2517 //
2518 // The following are defines for the bit fields in the USB_O_DMACOUNT4
2519 // register.
2520 //
2521 //*****************************************************************************
2522 #define USB_DMACOUNT4_COUNT_M 0xFFFFFFFC // DMA Count
2523 #define USB_DMACOUNT4_COUNT_S 2
2524 
2525 //*****************************************************************************
2526 //
2527 // The following are defines for the bit fields in the USB_O_DMACTL5 register.
2528 //
2529 //*****************************************************************************
2530 #define USB_DMACTL5_BRSTM_M 0x00000600 // Burst Mode
2531 #define USB_DMACTL5_BRSTM_ANY 0x00000000 // Bursts of unspecified length
2532 #define USB_DMACTL5_BRSTM_INC4 0x00000200 // INCR4 or unspecified length
2533 #define USB_DMACTL5_BRSTM_INC8 0x00000400 // INCR8, INCR4 or unspecified
2534  // length
2535 #define USB_DMACTL5_BRSTM_INC16 0x00000600 // INCR16, INCR8, INCR4 or
2536  // unspecified length
2537 #define USB_DMACTL5_ERR 0x00000100 // Bus Error Bit
2538 #define USB_DMACTL5_EP_M 0x000000F0 // Endpoint number
2539 #define USB_DMACTL5_IE 0x00000008 // DMA Interrupt Enable
2540 #define USB_DMACTL5_MODE 0x00000004 // DMA Transfer Mode
2541 #define USB_DMACTL5_DIR 0x00000002 // DMA Direction
2542 #define USB_DMACTL5_ENABLE 0x00000001 // DMA Transfer Enable
2543 #define USB_DMACTL5_EP_S 4
2544 
2545 //*****************************************************************************
2546 //
2547 // The following are defines for the bit fields in the USB_O_DMAADDR5 register.
2548 //
2549 //*****************************************************************************
2550 #define USB_DMAADDR5_ADDR_M 0xFFFFFFFC // DMA Address
2551 #define USB_DMAADDR5_ADDR_S 2
2552 
2553 //*****************************************************************************
2554 //
2555 // The following are defines for the bit fields in the USB_O_DMACOUNT5
2556 // register.
2557 //
2558 //*****************************************************************************
2559 #define USB_DMACOUNT5_COUNT_M 0xFFFFFFFC // DMA Count
2560 #define USB_DMACOUNT5_COUNT_S 2
2561 
2562 //*****************************************************************************
2563 //
2564 // The following are defines for the bit fields in the USB_O_DMACTL6 register.
2565 //
2566 //*****************************************************************************
2567 #define USB_DMACTL6_BRSTM_M 0x00000600 // Burst Mode
2568 #define USB_DMACTL6_BRSTM_ANY 0x00000000 // Bursts of unspecified length
2569 #define USB_DMACTL6_BRSTM_INC4 0x00000200 // INCR4 or unspecified length
2570 #define USB_DMACTL6_BRSTM_INC8 0x00000400 // INCR8, INCR4 or unspecified
2571  // length
2572 #define USB_DMACTL6_BRSTM_INC16 0x00000600 // INCR16, INCR8, INCR4 or
2573  // unspecified length
2574 #define USB_DMACTL6_ERR 0x00000100 // Bus Error Bit
2575 #define USB_DMACTL6_EP_M 0x000000F0 // Endpoint number
2576 #define USB_DMACTL6_IE 0x00000008 // DMA Interrupt Enable
2577 #define USB_DMACTL6_MODE 0x00000004 // DMA Transfer Mode
2578 #define USB_DMACTL6_DIR 0x00000002 // DMA Direction
2579 #define USB_DMACTL6_ENABLE 0x00000001 // DMA Transfer Enable
2580 #define USB_DMACTL6_EP_S 4
2581 
2582 //*****************************************************************************
2583 //
2584 // The following are defines for the bit fields in the USB_O_DMAADDR6 register.
2585 //
2586 //*****************************************************************************
2587 #define USB_DMAADDR6_ADDR_M 0xFFFFFFFC // DMA Address
2588 #define USB_DMAADDR6_ADDR_S 2
2589 
2590 //*****************************************************************************
2591 //
2592 // The following are defines for the bit fields in the USB_O_DMACOUNT6
2593 // register.
2594 //
2595 //*****************************************************************************
2596 #define USB_DMACOUNT6_COUNT_M 0xFFFFFFFC // DMA Count
2597 #define USB_DMACOUNT6_COUNT_S 2
2598 
2599 //*****************************************************************************
2600 //
2601 // The following are defines for the bit fields in the USB_O_DMACTL7 register.
2602 //
2603 //*****************************************************************************
2604 #define USB_DMACTL7_BRSTM_M 0x00000600 // Burst Mode
2605 #define USB_DMACTL7_BRSTM_ANY 0x00000000 // Bursts of unspecified length
2606 #define USB_DMACTL7_BRSTM_INC4 0x00000200 // INCR4 or unspecified length
2607 #define USB_DMACTL7_BRSTM_INC8 0x00000400 // INCR8, INCR4 or unspecified
2608  // length
2609 #define USB_DMACTL7_BRSTM_INC16 0x00000600 // INCR16, INCR8, INCR4 or
2610  // unspecified length
2611 #define USB_DMACTL7_ERR 0x00000100 // Bus Error Bit
2612 #define USB_DMACTL7_EP_M 0x000000F0 // Endpoint number
2613 #define USB_DMACTL7_IE 0x00000008 // DMA Interrupt Enable
2614 #define USB_DMACTL7_MODE 0x00000004 // DMA Transfer Mode
2615 #define USB_DMACTL7_DIR 0x00000002 // DMA Direction
2616 #define USB_DMACTL7_ENABLE 0x00000001 // DMA Transfer Enable
2617 #define USB_DMACTL7_EP_S 4
2618 
2619 //*****************************************************************************
2620 //
2621 // The following are defines for the bit fields in the USB_O_DMAADDR7 register.
2622 //
2623 //*****************************************************************************
2624 #define USB_DMAADDR7_ADDR_M 0xFFFFFFFC // DMA Address
2625 #define USB_DMAADDR7_ADDR_S 2
2626 
2627 //*****************************************************************************
2628 //
2629 // The following are defines for the bit fields in the USB_O_DMACOUNT7
2630 // register.
2631 //
2632 //*****************************************************************************
2633 #define USB_DMACOUNT7_COUNT_M 0xFFFFFFFC // DMA Count
2634 #define USB_DMACOUNT7_COUNT_S 2
2635 
2636 //*****************************************************************************
2637 //
2638 // The following are defines for the bit fields in the USB_O_RQPKTCOUNT1
2639 // register.
2640 //
2641 //*****************************************************************************
2642 #define USB_RQPKTCOUNT1_M 0x0000FFFF // Block Transfer Packet Count
2643 #define USB_RQPKTCOUNT1_S 0
2644 
2645 //*****************************************************************************
2646 //
2647 // The following are defines for the bit fields in the USB_O_RQPKTCOUNT2
2648 // register.
2649 //
2650 //*****************************************************************************
2651 #define USB_RQPKTCOUNT2_M 0x0000FFFF // Block Transfer Packet Count
2652 #define USB_RQPKTCOUNT2_S 0
2653 
2654 //*****************************************************************************
2655 //
2656 // The following are defines for the bit fields in the USB_O_RQPKTCOUNT3
2657 // register.
2658 //
2659 //*****************************************************************************
2660 #define USB_RQPKTCOUNT3_M 0x0000FFFF // Block Transfer Packet Count
2661 #define USB_RQPKTCOUNT3_S 0
2662 
2663 //*****************************************************************************
2664 //
2665 // The following are defines for the bit fields in the USB_O_RQPKTCOUNT4
2666 // register.
2667 //
2668 //*****************************************************************************
2669 #define USB_RQPKTCOUNT4_COUNT_M 0x0000FFFF // Block Transfer Packet Count
2670 #define USB_RQPKTCOUNT4_COUNT_S 0
2671 
2672 //*****************************************************************************
2673 //
2674 // The following are defines for the bit fields in the USB_O_RQPKTCOUNT5
2675 // register.
2676 //
2677 //*****************************************************************************
2678 #define USB_RQPKTCOUNT5_COUNT_M 0x0000FFFF // Block Transfer Packet Count
2679 #define USB_RQPKTCOUNT5_COUNT_S 0
2680 
2681 //*****************************************************************************
2682 //
2683 // The following are defines for the bit fields in the USB_O_RQPKTCOUNT6
2684 // register.
2685 //
2686 //*****************************************************************************
2687 #define USB_RQPKTCOUNT6_COUNT_M 0x0000FFFF // Block Transfer Packet Count
2688 #define USB_RQPKTCOUNT6_COUNT_S 0
2689 
2690 //*****************************************************************************
2691 //
2692 // The following are defines for the bit fields in the USB_O_RQPKTCOUNT7
2693 // register.
2694 //
2695 //*****************************************************************************
2696 #define USB_RQPKTCOUNT7_COUNT_M 0x0000FFFF // Block Transfer Packet Count
2697 #define USB_RQPKTCOUNT7_COUNT_S 0
2698 
2699 //*****************************************************************************
2700 //
2701 // The following are defines for the bit fields in the USB_O_RXDPKTBUFDIS
2702 // register.
2703 //
2704 //*****************************************************************************
2705 #define USB_RXDPKTBUFDIS_EP7 0x00000080 // EP7 RX Double-Packet Buffer
2706  // Disable
2707 #define USB_RXDPKTBUFDIS_EP6 0x00000040 // EP6 RX Double-Packet Buffer
2708  // Disable
2709 #define USB_RXDPKTBUFDIS_EP5 0x00000020 // EP5 RX Double-Packet Buffer
2710  // Disable
2711 #define USB_RXDPKTBUFDIS_EP4 0x00000010 // EP4 RX Double-Packet Buffer
2712  // Disable
2713 #define USB_RXDPKTBUFDIS_EP3 0x00000008 // EP3 RX Double-Packet Buffer
2714  // Disable
2715 #define USB_RXDPKTBUFDIS_EP2 0x00000004 // EP2 RX Double-Packet Buffer
2716  // Disable
2717 #define USB_RXDPKTBUFDIS_EP1 0x00000002 // EP1 RX Double-Packet Buffer
2718  // Disable
2719 
2720 //*****************************************************************************
2721 //
2722 // The following are defines for the bit fields in the USB_O_TXDPKTBUFDIS
2723 // register.
2724 //
2725 //*****************************************************************************
2726 #define USB_TXDPKTBUFDIS_EP7 0x00000080 // EP7 TX Double-Packet Buffer
2727  // Disable
2728 #define USB_TXDPKTBUFDIS_EP6 0x00000040 // EP6 TX Double-Packet Buffer
2729  // Disable
2730 #define USB_TXDPKTBUFDIS_EP5 0x00000020 // EP5 TX Double-Packet Buffer
2731  // Disable
2732 #define USB_TXDPKTBUFDIS_EP4 0x00000010 // EP4 TX Double-Packet Buffer
2733  // Disable
2734 #define USB_TXDPKTBUFDIS_EP3 0x00000008 // EP3 TX Double-Packet Buffer
2735  // Disable
2736 #define USB_TXDPKTBUFDIS_EP2 0x00000004 // EP2 TX Double-Packet Buffer
2737  // Disable
2738 #define USB_TXDPKTBUFDIS_EP1 0x00000002 // EP1 TX Double-Packet Buffer
2739  // Disable
2740 
2741 //*****************************************************************************
2742 //
2743 // The following are defines for the bit fields in the USB_O_CTO register.
2744 //
2745 //*****************************************************************************
2746 #define USB_CTO_CCTV_M 0x0000FFFF // Configurable Chirp Timeout Value
2747 #define USB_CTO_CCTV_S 0
2748 
2749 //*****************************************************************************
2750 //
2751 // The following are defines for the bit fields in the USB_O_HHSRTN register.
2752 //
2753 //*****************************************************************************
2754 #define USB_HHSRTN_HHSRTN_M 0x0000FFFF // HIgh Speed to UTM Operating
2755  // Delay
2756 #define USB_HHSRTN_HHSRTN_S 0
2757 
2758 //*****************************************************************************
2759 //
2760 // The following are defines for the bit fields in the USB_O_HSBT register.
2761 //
2762 //*****************************************************************************
2763 #define USB_HSBT_HSBT_M 0x0000000F // High Speed Timeout Adder
2764 #define USB_HSBT_HSBT_S 0
2765 
2766 //*****************************************************************************
2767 //
2768 // The following are defines for the bit fields in the USB_O_LPMATTR register.
2769 //
2770 //*****************************************************************************
2771 #define USB_LPMATTR_ENDPT_M 0x0000F000 // Endpoint
2772 #define USB_LPMATTR_RMTWAK 0x00000100 // Remote Wake
2773 #define USB_LPMATTR_HIRD_M 0x000000F0 // Host Initiated Resume Duration
2774 #define USB_LPMATTR_LS_M 0x0000000F // Link State
2775 #define USB_LPMATTR_LS_L1 0x00000001 // Sleep State (L1)
2776 #define USB_LPMATTR_ENDPT_S 12
2777 #define USB_LPMATTR_HIRD_S 4
2778 
2779 //*****************************************************************************
2780 //
2781 // The following are defines for the bit fields in the USB_O_LPMCNTRL register.
2782 //
2783 //*****************************************************************************
2784 #define USB_LPMCNTRL_NAK 0x00000010 // LPM NAK
2785 #define USB_LPMCNTRL_EN_M 0x0000000C // LPM Enable
2786 #define USB_LPMCNTRL_EN_NONE 0x00000000 // LPM and Extended transactions
2787  // are not supported. In this case,
2788  // the USB does not respond to LPM
2789  // transactions and LPM
2790  // transactions cause a timeout
2791 #define USB_LPMCNTRL_EN_EXT 0x00000004 // LPM is not supported but
2792  // extended transactions are
2793  // supported. In this case, the USB
2794  // does respond to an LPM
2795  // transaction with a STALL
2796 #define USB_LPMCNTRL_EN_LPMEXT 0x0000000C // The USB supports LPM extended
2797  // transactions. In this case, the
2798  // USB responds with a NYET or an
2799  // ACK as determined by the value
2800  // of TXLPM and other conditions
2801 #define USB_LPMCNTRL_RES 0x00000002 // LPM Resume
2802 #define USB_LPMCNTRL_TXLPM 0x00000001 // Transmit LPM Transaction Enable
2803 
2804 //*****************************************************************************
2805 //
2806 // The following are defines for the bit fields in the USB_O_LPMIM register.
2807 //
2808 //*****************************************************************************
2809 #define USB_LPMIM_ERR 0x00000020 // LPM Error Interrupt Mask
2810 #define USB_LPMIM_RES 0x00000010 // LPM Resume Interrupt Mask
2811 #define USB_LPMIM_NC 0x00000008 // LPM NC Interrupt Mask
2812 #define USB_LPMIM_ACK 0x00000004 // LPM ACK Interrupt Mask
2813 #define USB_LPMIM_NY 0x00000002 // LPM NY Interrupt Mask
2814 #define USB_LPMIM_STALL 0x00000001 // LPM STALL Interrupt Mask
2815 
2816 //*****************************************************************************
2817 //
2818 // The following are defines for the bit fields in the USB_O_LPMRIS register.
2819 //
2820 //*****************************************************************************
2821 #define USB_LPMRIS_ERR 0x00000020 // LPM Interrupt Status
2822 #define USB_LPMRIS_RES 0x00000010 // LPM Resume Interrupt Status
2823 #define USB_LPMRIS_NC 0x00000008 // LPM NC Interrupt Status
2824 #define USB_LPMRIS_ACK 0x00000004 // LPM ACK Interrupt Status
2825 #define USB_LPMRIS_NY 0x00000002 // LPM NY Interrupt Status
2826 #define USB_LPMRIS_LPMST 0x00000001 // LPM STALL Interrupt Status
2827 
2828 //*****************************************************************************
2829 //
2830 // The following are defines for the bit fields in the USB_O_LPMFADDR register.
2831 //
2832 //*****************************************************************************
2833 #define USB_LPMFADDR_ADDR_M 0x0000007F // LPM Function Address
2834 #define USB_LPMFADDR_ADDR_S 0
2835 
2836 //*****************************************************************************
2837 //
2838 // The following are defines for the bit fields in the USB_O_EPC register.
2839 //
2840 //*****************************************************************************
2841 #define USB_EPC_PFLTACT_M 0x00000300 // Power Fault Action
2842 #define USB_EPC_PFLTACT_UNCHG 0x00000000 // Unchanged
2843 #define USB_EPC_PFLTACT_TRIS 0x00000100 // Tristate
2844 #define USB_EPC_PFLTACT_LOW 0x00000200 // Low
2845 #define USB_EPC_PFLTACT_HIGH 0x00000300 // High
2846 #define USB_EPC_PFLTAEN 0x00000040 // Power Fault Action Enable
2847 #define USB_EPC_PFLTSEN_HIGH 0x00000020 // Power Fault Sense
2848 #define USB_EPC_PFLTEN 0x00000010 // Power Fault Input Enable
2849 #define USB_EPC_EPENDE 0x00000004 // EPEN Drive Enable
2850 #define USB_EPC_EPEN_M 0x00000003 // External Power Supply Enable
2851  // Configuration
2852 #define USB_EPC_EPEN_LOW 0x00000000 // Power Enable Active Low
2853 #define USB_EPC_EPEN_HIGH 0x00000001 // Power Enable Active High
2854 #define USB_EPC_EPEN_VBLOW 0x00000002 // Power Enable High if VBUS Low
2855  // (OTG only)
2856 #define USB_EPC_EPEN_VBHIGH 0x00000003 // Power Enable High if VBUS High
2857  // (OTG only)
2858 
2859 //*****************************************************************************
2860 //
2861 // The following are defines for the bit fields in the USB_O_EPCRIS register.
2862 //
2863 //*****************************************************************************
2864 #define USB_EPCRIS_PF 0x00000001 // USB Power Fault Interrupt Status
2865 
2866 //*****************************************************************************
2867 //
2868 // The following are defines for the bit fields in the USB_O_EPCIM register.
2869 //
2870 //*****************************************************************************
2871 #define USB_EPCIM_PF 0x00000001 // USB Power Fault Interrupt Mask
2872 
2873 //*****************************************************************************
2874 //
2875 // The following are defines for the bit fields in the USB_O_EPCISC register.
2876 //
2877 //*****************************************************************************
2878 #define USB_EPCISC_PF 0x00000001 // USB Power Fault Interrupt Status
2879  // and Clear
2880 
2881 //*****************************************************************************
2882 //
2883 // The following are defines for the bit fields in the USB_O_DRRIS register.
2884 //
2885 //*****************************************************************************
2886 #define USB_DRRIS_RESUME 0x00000001 // RESUME Interrupt Status
2887 
2888 //*****************************************************************************
2889 //
2890 // The following are defines for the bit fields in the USB_O_DRIM register.
2891 //
2892 //*****************************************************************************
2893 #define USB_DRIM_RESUME 0x00000001 // RESUME Interrupt Mask
2894 
2895 //*****************************************************************************
2896 //
2897 // The following are defines for the bit fields in the USB_O_DRISC register.
2898 //
2899 //*****************************************************************************
2900 #define USB_DRISC_RESUME 0x00000001 // RESUME Interrupt Status and
2901  // Clear
2902 
2903 //*****************************************************************************
2904 //
2905 // The following are defines for the bit fields in the USB_O_GPCS register.
2906 //
2907 //*****************************************************************************
2908 #define USB_GPCS_DEVMOD_M 0x00000007 // Device Mode
2909 #define USB_GPCS_DEVMOD_OTG 0x00000000 // Use USB0VBUS and USB0ID pin
2910 #define USB_GPCS_DEVMOD_HOST 0x00000002 // Force USB0VBUS and USB0ID low
2911 #define USB_GPCS_DEVMOD_DEV 0x00000003 // Force USB0VBUS and USB0ID high
2912 #define USB_GPCS_DEVMOD_HOSTVBUS \
2913  0x00000004 // Use USB0VBUS and force USB0ID
2914  // low
2915 #define USB_GPCS_DEVMOD_DEVVBUS 0x00000005 // Use USB0VBUS and force USB0ID
2916  // high
2917 #define USB_GPCS_DEVMODOTG 0x00000002 // Enable Device Mode
2918 #define USB_GPCS_DEVMOD 0x00000001 // Device Mode
2919 
2920 //*****************************************************************************
2921 //
2922 // The following are defines for the bit fields in the USB_O_VDC register.
2923 //
2924 //*****************************************************************************
2925 #define USB_VDC_VBDEN 0x00000001 // VBUS Droop Enable
2926 
2927 //*****************************************************************************
2928 //
2929 // The following are defines for the bit fields in the USB_O_VDCRIS register.
2930 //
2931 //*****************************************************************************
2932 #define USB_VDCRIS_VD 0x00000001 // VBUS Droop Raw Interrupt Status
2933 
2934 //*****************************************************************************
2935 //
2936 // The following are defines for the bit fields in the USB_O_VDCIM register.
2937 //
2938 //*****************************************************************************
2939 #define USB_VDCIM_VD 0x00000001 // VBUS Droop Interrupt Mask
2940 
2941 //*****************************************************************************
2942 //
2943 // The following are defines for the bit fields in the USB_O_VDCISC register.
2944 //
2945 //*****************************************************************************
2946 #define USB_VDCISC_VD 0x00000001 // VBUS Droop Interrupt Status and
2947  // Clear
2948 
2949 //*****************************************************************************
2950 //
2951 // The following are defines for the bit fields in the USB_O_IDVRIS register.
2952 //
2953 //*****************************************************************************
2954 #define USB_IDVRIS_ID 0x00000001 // ID Valid Detect Raw Interrupt
2955  // Status
2956 
2957 //*****************************************************************************
2958 //
2959 // The following are defines for the bit fields in the USB_O_IDVIM register.
2960 //
2961 //*****************************************************************************
2962 #define USB_IDVIM_ID 0x00000001 // ID Valid Detect Interrupt Mask
2963 
2964 //*****************************************************************************
2965 //
2966 // The following are defines for the bit fields in the USB_O_IDVISC register.
2967 //
2968 //*****************************************************************************
2969 #define USB_IDVISC_ID 0x00000001 // ID Valid Detect Interrupt Status
2970  // and Clear
2971 
2972 //*****************************************************************************
2973 //
2974 // The following are defines for the bit fields in the USB_O_PP register.
2975 //
2976 //*****************************************************************************
2977 #define USB_PP_ECNT_M 0x0000FF00 // Endpoint Count
2978 #define USB_PP_USB_M 0x000000C0 // USB Capability
2979 #define USB_PP_USB_DEVICE 0x00000040 // DEVICE
2980 #define USB_PP_USB_HOSTDEVICE 0x00000080 // HOST
2981 #define USB_PP_USB_OTG 0x000000C0 // OTG
2982 #define USB_PP_ULPI 0x00000020 // ULPI Present
2983 #define USB_PP_PHY 0x00000010 // PHY Present
2984 
2985 #define USB_PP_ECNT_S 8
2986 
2987 //*****************************************************************************
2988 //
2989 // The following are defines for the bit fields in the USB_O_PC register.
2990 //
2991 //*****************************************************************************
2992 #define USB_PC_ULPIEN 0x00010000 // ULPI Enable
2993 
2994 //*****************************************************************************
2995 //
2996 // The following are defines for the bit fields in the USB_O_CC register.
2997 //
2998 //*****************************************************************************
2999 #define USB_CC_CLKEN 0x00000200 // USB Clock Enable
3000 #define USB_CC_CSD 0x00000100 // Clock Source/Direction
3001 #define USB_CC_CLKDIV_M 0x0000000F // PLL Clock Divisor
3002 #define USB_CC_CLKDIV_S 0
3003 
3004 #endif // __HW_USB_H__
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