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Go to the documentation of this file. 38 #ifndef __HW_SYSCTL_H__ 39 #define __HW_SYSCTL_H__ 46 #define SYSCTL_DID0 0x400FE000 // Device Identification 0 47 #define SYSCTL_DID1 0x400FE004 // Device Identification 1 48 #define SYSCTL_PTBOCTL 0x400FE038 // Power-Temp Brown Out Control 49 #define SYSCTL_RIS 0x400FE050 // Raw Interrupt Status 50 #define SYSCTL_IMC 0x400FE054 // Interrupt Mask Control 51 #define SYSCTL_MISC 0x400FE058 // Masked Interrupt Status and 53 #define SYSCTL_RESC 0x400FE05C // Reset Cause 54 #define SYSCTL_PWRTC 0x400FE060 // Power-Temperature Cause 55 #define SYSCTL_NMIC 0x400FE064 // NMI Cause Register 56 #define SYSCTL_MOSCCTL 0x400FE07C // Main Oscillator Control 57 #define SYSCTL_RSCLKCFG 0x400FE0B0 // Run and Sleep Mode Configuration 59 #define SYSCTL_MEMTIM0 0x400FE0C0 // Memory Timing Parameter Register 61 #define SYSCTL_ALTCLKCFG 0x400FE138 // Alternate Clock Configuration 62 #define SYSCTL_DSLPCLKCFG 0x400FE144 // Deep Sleep Clock Configuration 63 #define SYSCTL_DSCLKCFG 0x400FE144 // Deep Sleep Clock Configuration 65 #define SYSCTL_DIVSCLK 0x400FE148 // Divisor and Source Clock 67 #define SYSCTL_SYSPROP 0x400FE14C // System Properties 68 #define SYSCTL_PIOSCCAL 0x400FE150 // Precision Internal Oscillator 70 #define SYSCTL_PIOSCSTAT 0x400FE154 // Precision Internal Oscillator 72 #define SYSCTL_PLLFREQ0 0x400FE160 // PLL Frequency 0 73 #define SYSCTL_PLLFREQ1 0x400FE164 // PLL Frequency 1 74 #define SYSCTL_PLLSTAT 0x400FE168 // PLL Status 75 #define SYSCTL_SLPPWRCFG 0x400FE188 // Sleep Power Configuration 76 #define SYSCTL_DSLPPWRCFG 0x400FE18C // Deep-Sleep Power Configuration 77 #define SYSCTL_DC9 0x400FE190 // Device Capabilities 9 78 #define SYSCTL_NVMSTAT 0x400FE1A0 // Non-Volatile Memory Information 79 #define SYSCTL_LDOSPCTL 0x400FE1B4 // LDO Sleep Power Control 80 #define SYSCTL_LDODPCTL 0x400FE1BC // LDO Deep-Sleep Power Control 81 #define SYSCTL_RESBEHAVCTL 0x400FE1D8 // Reset Behavior Control Register 82 #define SYSCTL_HSSR 0x400FE1F4 // Hardware System Service Request 83 #define SYSCTL_USBPDS 0x400FE280 // USB Power Domain Status 84 #define SYSCTL_USBMPC 0x400FE284 // USB Memory Power Control 85 #define SYSCTL_EMACPDS 0x400FE288 // Ethernet MAC Power Domain Status 86 #define SYSCTL_EMACMPC 0x400FE28C // Ethernet MAC Memory Power 88 #define SYSCTL_LCDMPC 0x400FE294 // LCD Memory Power Control 89 #define SYSCTL_PPWD 0x400FE300 // Watchdog Timer Peripheral 91 #define SYSCTL_PPTIMER 0x400FE304 // 16/32-Bit General-Purpose Timer 93 #define SYSCTL_PPGPIO 0x400FE308 // General-Purpose Input/Output 95 #define SYSCTL_PPDMA 0x400FE30C // Micro Direct Memory Access 97 #define SYSCTL_PPEPI 0x400FE310 // EPI Peripheral Present 98 #define SYSCTL_PPHIB 0x400FE314 // Hibernation Peripheral Present 99 #define SYSCTL_PPUART 0x400FE318 // Universal Asynchronous 102 #define SYSCTL_PPSSI 0x400FE31C // Synchronous Serial Interface 104 #define SYSCTL_PPI2C 0x400FE320 // Inter-Integrated Circuit 106 #define SYSCTL_PPUSB 0x400FE328 // Universal Serial Bus Peripheral 108 #define SYSCTL_PPEPHY 0x400FE330 // Ethernet PHY Peripheral Present 109 #define SYSCTL_PPCAN 0x400FE334 // Controller Area Network 111 #define SYSCTL_PPADC 0x400FE338 // Analog-to-Digital Converter 113 #define SYSCTL_PPACMP 0x400FE33C // Analog Comparator Peripheral 115 #define SYSCTL_PPPWM 0x400FE340 // Pulse Width Modulator Peripheral 117 #define SYSCTL_PPQEI 0x400FE344 // Quadrature Encoder Interface 119 #define SYSCTL_PPEEPROM 0x400FE358 // EEPROM Peripheral Present 120 #define SYSCTL_PPCCM 0x400FE374 // CRC and Cryptographic Modules 122 #define SYSCTL_PPLCD 0x400FE390 // LCD Peripheral Present 123 #define SYSCTL_PPOWIRE 0x400FE398 // 1-Wire Peripheral Present 124 #define SYSCTL_PPEMAC 0x400FE39C // Ethernet MAC Peripheral Present 125 #define SYSCTL_SRWD 0x400FE500 // Watchdog Timer Software Reset 126 #define SYSCTL_SRTIMER 0x400FE504 // 16/32-Bit General-Purpose Timer 128 #define SYSCTL_SRGPIO 0x400FE508 // General-Purpose Input/Output 130 #define SYSCTL_SRDMA 0x400FE50C // Micro Direct Memory Access 132 #define SYSCTL_SREPI 0x400FE510 // EPI Software Reset 133 #define SYSCTL_SRHIB 0x400FE514 // Hibernation Software Reset 134 #define SYSCTL_SRUART 0x400FE518 // Universal Asynchronous 137 #define SYSCTL_SRSSI 0x400FE51C // Synchronous Serial Interface 139 #define SYSCTL_SRI2C 0x400FE520 // Inter-Integrated Circuit 141 #define SYSCTL_SRUSB 0x400FE528 // Universal Serial Bus Software 143 #define SYSCTL_SREPHY 0x400FE530 // Ethernet PHY Software Reset 144 #define SYSCTL_SRCAN 0x400FE534 // Controller Area Network Software 146 #define SYSCTL_SRADC 0x400FE538 // Analog-to-Digital Converter 148 #define SYSCTL_SRACMP 0x400FE53C // Analog Comparator Software Reset 149 #define SYSCTL_SRPWM 0x400FE540 // Pulse Width Modulator Software 151 #define SYSCTL_SRQEI 0x400FE544 // Quadrature Encoder Interface 153 #define SYSCTL_SREEPROM 0x400FE558 // EEPROM Software Reset 154 #define SYSCTL_SRCCM 0x400FE574 // CRC and Cryptographic Modules 156 #define SYSCTL_SRLCD 0x400FE590 // LCD Controller Software Reset 157 #define SYSCTL_SROWIRE 0x400FE598 // 1-Wire Software Reset 158 #define SYSCTL_SREMAC 0x400FE59C // Ethernet MAC Software Reset 159 #define SYSCTL_RCGCWD 0x400FE600 // Watchdog Timer Run Mode Clock 161 #define SYSCTL_RCGCTIMER 0x400FE604 // 16/32-Bit General-Purpose Timer 163 #define SYSCTL_RCGCGPIO 0x400FE608 // General-Purpose Input/Output Run 165 #define SYSCTL_RCGCDMA 0x400FE60C // Micro Direct Memory Access Run 167 #define SYSCTL_RCGCEPI 0x400FE610 // EPI Run Mode Clock Gating 169 #define SYSCTL_RCGCHIB 0x400FE614 // Hibernation Run Mode Clock 171 #define SYSCTL_RCGCUART 0x400FE618 // Universal Asynchronous 174 #define SYSCTL_RCGCSSI 0x400FE61C // Synchronous Serial Interface Run 176 #define SYSCTL_RCGCI2C 0x400FE620 // Inter-Integrated Circuit Run 178 #define SYSCTL_RCGCUSB 0x400FE628 // Universal Serial Bus Run Mode 180 #define SYSCTL_RCGCEPHY 0x400FE630 // Ethernet PHY Run Mode Clock 182 #define SYSCTL_RCGCCAN 0x400FE634 // Controller Area Network Run Mode 184 #define SYSCTL_RCGCADC 0x400FE638 // Analog-to-Digital Converter Run 186 #define SYSCTL_RCGCACMP 0x400FE63C // Analog Comparator Run Mode Clock 188 #define SYSCTL_RCGCPWM 0x400FE640 // Pulse Width Modulator Run Mode 190 #define SYSCTL_RCGCQEI 0x400FE644 // Quadrature Encoder Interface Run 192 #define SYSCTL_RCGCEEPROM 0x400FE658 // EEPROM Run Mode Clock Gating 194 #define SYSCTL_RCGCCCM 0x400FE674 // CRC and Cryptographic Modules 196 #define SYSCTL_RCGCLCD 0x400FE690 // LCD Controller Run Mode Clock 198 #define SYSCTL_RCGCOWIRE 0x400FE698 // 1-Wire Run Mode Clock Gating 200 #define SYSCTL_RCGCEMAC 0x400FE69C // Ethernet MAC Run Mode Clock 202 #define SYSCTL_SCGCWD 0x400FE700 // Watchdog Timer Sleep Mode Clock 204 #define SYSCTL_SCGCTIMER 0x400FE704 // 16/32-Bit General-Purpose Timer 206 #define SYSCTL_SCGCGPIO 0x400FE708 // General-Purpose Input/Output 208 #define SYSCTL_SCGCDMA 0x400FE70C // Micro Direct Memory Access Sleep 210 #define SYSCTL_SCGCEPI 0x400FE710 // EPI Sleep Mode Clock Gating 212 #define SYSCTL_SCGCHIB 0x400FE714 // Hibernation Sleep Mode Clock 214 #define SYSCTL_SCGCUART 0x400FE718 // Universal Asynchronous 217 #define SYSCTL_SCGCSSI 0x400FE71C // Synchronous Serial Interface 219 #define SYSCTL_SCGCI2C 0x400FE720 // Inter-Integrated Circuit Sleep 221 #define SYSCTL_SCGCUSB 0x400FE728 // Universal Serial Bus Sleep Mode 223 #define SYSCTL_SCGCEPHY 0x400FE730 // Ethernet PHY Sleep Mode Clock 225 #define SYSCTL_SCGCCAN 0x400FE734 // Controller Area Network Sleep 227 #define SYSCTL_SCGCADC 0x400FE738 // Analog-to-Digital Converter 229 #define SYSCTL_SCGCACMP 0x400FE73C // Analog Comparator Sleep Mode 231 #define SYSCTL_SCGCPWM 0x400FE740 // Pulse Width Modulator Sleep Mode 233 #define SYSCTL_SCGCQEI 0x400FE744 // Quadrature Encoder Interface 235 #define SYSCTL_SCGCEEPROM 0x400FE758 // EEPROM Sleep Mode Clock Gating 237 #define SYSCTL_SCGCCCM 0x400FE774 // CRC and Cryptographic Modules 239 #define SYSCTL_SCGCLCD 0x400FE790 // LCD Controller Sleep Mode Clock 241 #define SYSCTL_SCGCOWIRE 0x400FE798 // 1-Wire Sleep Mode Clock Gating 243 #define SYSCTL_SCGCEMAC 0x400FE79C // Ethernet MAC Sleep Mode Clock 245 #define SYSCTL_DCGCWD 0x400FE800 // Watchdog Timer Deep-Sleep Mode 247 #define SYSCTL_DCGCTIMER 0x400FE804 // 16/32-Bit General-Purpose Timer 250 #define SYSCTL_DCGCGPIO 0x400FE808 // General-Purpose Input/Output 253 #define SYSCTL_DCGCDMA 0x400FE80C // Micro Direct Memory Access 256 #define SYSCTL_DCGCEPI 0x400FE810 // EPI Deep-Sleep Mode Clock Gating 258 #define SYSCTL_DCGCHIB 0x400FE814 // Hibernation Deep-Sleep Mode 260 #define SYSCTL_DCGCUART 0x400FE818 // Universal Asynchronous 263 #define SYSCTL_DCGCSSI 0x400FE81C // Synchronous Serial Interface 266 #define SYSCTL_DCGCI2C 0x400FE820 // Inter-Integrated Circuit 269 #define SYSCTL_DCGCUSB 0x400FE828 // Universal Serial Bus Deep-Sleep 271 #define SYSCTL_DCGCEPHY 0x400FE830 // Ethernet PHY Deep-Sleep Mode 273 #define SYSCTL_DCGCCAN 0x400FE834 // Controller Area Network 276 #define SYSCTL_DCGCADC 0x400FE838 // Analog-to-Digital Converter 279 #define SYSCTL_DCGCACMP 0x400FE83C // Analog Comparator Deep-Sleep 281 #define SYSCTL_DCGCPWM 0x400FE840 // Pulse Width Modulator Deep-Sleep 283 #define SYSCTL_DCGCQEI 0x400FE844 // Quadrature Encoder Interface 286 #define SYSCTL_DCGCEEPROM 0x400FE858 // EEPROM Deep-Sleep Mode Clock 288 #define SYSCTL_DCGCCCM 0x400FE874 // CRC and Cryptographic Modules 291 #define SYSCTL_DCGCLCD 0x400FE890 // LCD Controller Deep-Sleep Mode 293 #define SYSCTL_DCGCOWIRE 0x400FE898 // 1-Wire Deep-Sleep Mode Clock 295 #define SYSCTL_DCGCEMAC 0x400FE89C // Ethernet MAC Deep-Sleep Mode 297 #define SYSCTL_PCWD 0x400FE900 // Watchdog Timer Power Control 298 #define SYSCTL_PCTIMER 0x400FE904 // 16/32-Bit General-Purpose Timer 300 #define SYSCTL_PCGPIO 0x400FE908 // General-Purpose Input/Output 302 #define SYSCTL_PCDMA 0x400FE90C // Micro Direct Memory Access Power 304 #define SYSCTL_PCEPI 0x400FE910 // External Peripheral Interface 306 #define SYSCTL_PCHIB 0x400FE914 // Hibernation Power Control 307 #define SYSCTL_PCUART 0x400FE918 // Universal Asynchronous 310 #define SYSCTL_PCSSI 0x400FE91C // Synchronous Serial Interface 312 #define SYSCTL_PCI2C 0x400FE920 // Inter-Integrated Circuit Power 314 #define SYSCTL_PCUSB 0x400FE928 // Universal Serial Bus Power 316 #define SYSCTL_PCEPHY 0x400FE930 // Ethernet PHY Power Control 317 #define SYSCTL_PCCAN 0x400FE934 // Controller Area Network Power 319 #define SYSCTL_PCADC 0x400FE938 // Analog-to-Digital Converter 321 #define SYSCTL_PCACMP 0x400FE93C // Analog Comparator Power Control 322 #define SYSCTL_PCPWM 0x400FE940 // Pulse Width Modulator Power 324 #define SYSCTL_PCQEI 0x400FE944 // Quadrature Encoder Interface 326 #define SYSCTL_PCEEPROM 0x400FE958 // EEPROM Power Control 327 #define SYSCTL_PCCCM 0x400FE974 // CRC and Cryptographic Modules 329 #define SYSCTL_PCLCD 0x400FE990 // LCD Controller Power Control 330 #define SYSCTL_PCOWIRE 0x400FE998 // 1-Wire Power Control 331 #define SYSCTL_PCEMAC 0x400FE99C // Ethernet MAC Power Control 332 #define SYSCTL_PRWD 0x400FEA00 // Watchdog Timer Peripheral Ready 333 #define SYSCTL_PRTIMER 0x400FEA04 // 16/32-Bit General-Purpose Timer 335 #define SYSCTL_PRGPIO 0x400FEA08 // General-Purpose Input/Output 337 #define SYSCTL_PRDMA 0x400FEA0C // Micro Direct Memory Access 339 #define SYSCTL_PREPI 0x400FEA10 // EPI Peripheral Ready 340 #define SYSCTL_PRHIB 0x400FEA14 // Hibernation Peripheral Ready 341 #define SYSCTL_PRUART 0x400FEA18 // Universal Asynchronous 344 #define SYSCTL_PRSSI 0x400FEA1C // Synchronous Serial Interface 346 #define SYSCTL_PRI2C 0x400FEA20 // Inter-Integrated Circuit 348 #define SYSCTL_PRUSB 0x400FEA28 // Universal Serial Bus Peripheral 350 #define SYSCTL_PREPHY 0x400FEA30 // Ethernet PHY Peripheral Ready 351 #define SYSCTL_PRCAN 0x400FEA34 // Controller Area Network 353 #define SYSCTL_PRADC 0x400FEA38 // Analog-to-Digital Converter 355 #define SYSCTL_PRACMP 0x400FEA3C // Analog Comparator Peripheral 357 #define SYSCTL_PRPWM 0x400FEA40 // Pulse Width Modulator Peripheral 359 #define SYSCTL_PRQEI 0x400FEA44 // Quadrature Encoder Interface 361 #define SYSCTL_PREEPROM 0x400FEA58 // EEPROM Peripheral Ready 362 #define SYSCTL_PRCCM 0x400FEA74 // CRC and Cryptographic Modules 364 #define SYSCTL_PRLCD 0x400FEA90 // LCD Controller Peripheral Ready 365 #define SYSCTL_PROWIRE 0x400FEA98 // 1-Wire Peripheral Ready 366 #define SYSCTL_PREMAC 0x400FEA9C // Ethernet MAC Peripheral Ready 367 #define SYSCTL_UNIQUEID0 0x400FEF20 // Unique ID 0 368 #define SYSCTL_UNIQUEID1 0x400FEF24 // Unique ID 1 369 #define SYSCTL_UNIQUEID2 0x400FEF28 // Unique ID 2 370 #define SYSCTL_UNIQUEID3 0x400FEF2C // Unique ID 3 379 #define SYSCTL_DID0_VER_M 0x70000000 // DID0 Version 380 #define SYSCTL_DID0_VER_1 0x10000000 // Second version of the DID0 382 #define SYSCTL_DID0_CLASS_M 0x00FF0000 // Device Class 383 #define SYSCTL_DID0_CLASS_MSP432E4 \ 384 0x000C0000 // MSP432E4 microcontrollers 385 #define SYSCTL_DID0_MAJ_M 0x0000FF00 // Major Revision 386 #define SYSCTL_DID0_MAJ_REVA 0x00000000 // Revision A (initial device) 387 #define SYSCTL_DID0_MAJ_REVB 0x00000100 // Revision B (first base layer 389 #define SYSCTL_DID0_MAJ_REVC 0x00000200 // Revision C (second base layer 391 #define SYSCTL_DID0_MIN_M 0x000000FF // Minor Revision 392 #define SYSCTL_DID0_MIN_0 0x00000000 // Initial device, or a major 394 #define SYSCTL_DID0_MIN_1 0x00000001 // First metal layer change 395 #define SYSCTL_DID0_MIN_2 0x00000002 // Second metal layer change 402 #define SYSCTL_DID1_VER_M 0xF0000000 // DID1 Version 403 #define SYSCTL_DID1_FAM_M 0x0F000000 // Family 404 #define SYSCTL_DID1_FAM_MSP432E4 \ 405 0x00000000 // MSP432E4 family of 407 #define SYSCTL_DID1_PRTNO_M 0x00FF0000 // Part Number 408 #define SYSCTL_DID1_PRTNO_MSP432E401Y \ 409 0x002D0000 // MSP432E401Y 410 #define SYSCTL_DID1_PRTNO_MSP432E411Y \ 411 0x00320000 // MSP432E411Y 412 #define SYSCTL_DID1_PINCNT_M 0x0000E000 // Package Pin Count 413 #define SYSCTL_DID1_PINCNT_128 0x0000C000 // 128-pin TQFP package 414 #define SYSCTL_DID1_PINCNT_212 0x0000E000 // 212-pin BGA package 415 #define SYSCTL_DID1_TEMP_M 0x000000E0 // Temperature Range 416 #define SYSCTL_DID1_TEMP_C 0x00000000 // Commercial temperature range 417 #define SYSCTL_DID1_TEMP_I 0x00000020 // Industrial temperature range 418 #define SYSCTL_DID1_TEMP_E 0x00000040 // Extended temperature range 419 #define SYSCTL_DID1_TEMP_IE 0x00000060 // Available in both industrial 423 #define SYSCTL_DID1_PKG_M 0x00000018 // Package Type 424 #define SYSCTL_DID1_PKG_QFP 0x00000008 // QFP package 425 #define SYSCTL_DID1_PKG_BGA 0x00000010 // BGA package 426 #define SYSCTL_DID1_ROHS 0x00000004 // RoHS-Compliance 427 #define SYSCTL_DID1_QUAL_M 0x00000003 // Qualification Status 428 #define SYSCTL_DID1_QUAL_ES 0x00000000 // Engineering Sample (unqualified) 429 #define SYSCTL_DID1_QUAL_PP 0x00000001 // Pilot Production (unqualified) 430 #define SYSCTL_DID1_QUAL_FQ 0x00000002 // Fully Qualified 437 #define SYSCTL_PTBOCTL_VDDA_UBOR_M \ 438 0x00000300 // VDDA under BOR Event Action 439 #define SYSCTL_PTBOCTL_VDDA_UBOR_NONE \ 440 0x00000000 // No Action 441 #define SYSCTL_PTBOCTL_VDDA_UBOR_SYSINT \ 442 0x00000100 // System control interrupt 443 #define SYSCTL_PTBOCTL_VDDA_UBOR_NMI \ 445 #define SYSCTL_PTBOCTL_VDDA_UBOR_RST \ 447 #define SYSCTL_PTBOCTL_VDD_UBOR_M \ 448 0x00000003 // VDD (VDDS) under BOR Event 450 #define SYSCTL_PTBOCTL_VDD_UBOR_NONE \ 451 0x00000000 // No Action 452 #define SYSCTL_PTBOCTL_VDD_UBOR_SYSINT \ 453 0x00000001 // System control interrupt 454 #define SYSCTL_PTBOCTL_VDD_UBOR_NMI \ 456 #define SYSCTL_PTBOCTL_VDD_UBOR_RST \ 464 #define SYSCTL_RIS_MOSCPUPRIS 0x00000100 // MOSC Power Up Raw Interrupt 466 #define SYSCTL_RIS_PLLLRIS 0x00000040 // PLL Lock Raw Interrupt Status 467 #define SYSCTL_RIS_MOFRIS 0x00000008 // Main Oscillator Failure Raw 469 #define SYSCTL_RIS_BORRIS 0x00000002 // Brown-Out Reset Raw Interrupt 477 #define SYSCTL_IMC_MOSCPUPIM 0x00000100 // MOSC Power Up Interrupt Mask 478 #define SYSCTL_IMC_PLLLIM 0x00000040 // PLL Lock Interrupt Mask 479 #define SYSCTL_IMC_MOFIM 0x00000008 // Main Oscillator Failure 481 #define SYSCTL_IMC_BORIM 0x00000002 // Brown-Out Reset Interrupt Mask 488 #define SYSCTL_MISC_MOSCPUPMIS 0x00000100 // MOSC Power Up Masked Interrupt 490 #define SYSCTL_MISC_PLLLMIS 0x00000040 // PLL Lock Masked Interrupt Status 491 #define SYSCTL_MISC_MOFMIS 0x00000008 // Main Oscillator Failure Masked 493 #define SYSCTL_MISC_BORMIS 0x00000002 // BOR Masked Interrupt Status 500 #define SYSCTL_RESC_MOSCFAIL 0x00010000 // MOSC Failure Reset 501 #define SYSCTL_RESC_HSSR 0x00001000 // HSSR Reset 502 #define SYSCTL_RESC_WDT1 0x00000020 // Watchdog Timer 1 Reset 503 #define SYSCTL_RESC_SW 0x00000010 // Software Reset 504 #define SYSCTL_RESC_WDT0 0x00000008 // Watchdog Timer 0 Reset 505 #define SYSCTL_RESC_BOR 0x00000004 // Brown-Out Reset 506 #define SYSCTL_RESC_POR 0x00000002 // Power-On Reset 507 #define SYSCTL_RESC_EXT 0x00000001 // External Reset 514 #define SYSCTL_PWRTC_VDDA_UBOR 0x00000010 // VDDA Under BOR Status 515 #define SYSCTL_PWRTC_VDD_UBOR 0x00000001 // VDD Under BOR Status 522 #define SYSCTL_NMIC_MOSCFAIL 0x00010000 // MOSC Failure NMI 523 #define SYSCTL_NMIC_TAMPER 0x00000200 // Tamper Event NMI 524 #define SYSCTL_NMIC_WDT1 0x00000020 // Watch Dog Timer (WDT) 1 NMI 525 #define SYSCTL_NMIC_WDT0 0x00000008 // Watch Dog Timer (WDT) 0 NMI 526 #define SYSCTL_NMIC_POWER 0x00000004 // Power/Brown Out Event NMI 527 #define SYSCTL_NMIC_EXTERNAL 0x00000001 // External Pin NMI 534 #define SYSCTL_MOSCCTL_OSCRNG 0x00000010 // Oscillator Range 535 #define SYSCTL_MOSCCTL_PWRDN 0x00000008 // Power Down 536 #define SYSCTL_MOSCCTL_NOXTAL 0x00000004 // No Crystal Connected 537 #define SYSCTL_MOSCCTL_MOSCIM 0x00000002 // MOSC Failure Action 538 #define SYSCTL_MOSCCTL_CVAL 0x00000001 // Clock Validation for MOSC 546 #define SYSCTL_RSCLKCFG_MEMTIMU 0x80000000 // Memory Timing Register Update 547 #define SYSCTL_RSCLKCFG_NEWFREQ 0x40000000 // New PLLFREQ Accept 548 #define SYSCTL_RSCLKCFG_ACG 0x20000000 // Auto Clock Gating 549 #define SYSCTL_RSCLKCFG_USEPLL 0x10000000 // Use PLL 550 #define SYSCTL_RSCLKCFG_PLLSRC_M \ 551 0x0F000000 // PLL Source 552 #define SYSCTL_RSCLKCFG_PLLSRC_PIOSC \ 553 0x00000000 // PIOSC is PLL input clock source 554 #define SYSCTL_RSCLKCFG_PLLSRC_MOSC \ 555 0x03000000 // MOSC is the PLL input clock 557 #define SYSCTL_RSCLKCFG_OSCSRC_M \ 558 0x00F00000 // Oscillator Source 559 #define SYSCTL_RSCLKCFG_OSCSRC_PIOSC \ 560 0x00000000 // PIOSC is oscillator source 561 #define SYSCTL_RSCLKCFG_OSCSRC_LFIOSC \ 562 0x00200000 // LFIOSC is oscillator source 563 #define SYSCTL_RSCLKCFG_OSCSRC_MOSC \ 564 0x00300000 // MOSC is oscillator source 565 #define SYSCTL_RSCLKCFG_OSCSRC_RTC \ 566 0x00400000 // Hibernation Module RTC 568 #define SYSCTL_RSCLKCFG_OSYSDIV_M \ 569 0x000FFC00 // Oscillator System Clock Divisor 570 #define SYSCTL_RSCLKCFG_PSYSDIV_M \ 571 0x000003FF // PLL System Clock Divisor 572 #define SYSCTL_RSCLKCFG_OSYSDIV_S \ 574 #define SYSCTL_RSCLKCFG_PSYSDIV_S \ 582 #define SYSCTL_MEMTIM0_EBCHT_M 0x03C00000 // EEPROM Clock High Time 583 #define SYSCTL_MEMTIM0_EBCHT_0_5 \ 584 0x00000000 // 1/2 system clock period 585 #define SYSCTL_MEMTIM0_EBCHT_1 0x00400000 // 1 system clock period 586 #define SYSCTL_MEMTIM0_EBCHT_1_5 \ 587 0x00800000 // 1.5 system clock periods 588 #define SYSCTL_MEMTIM0_EBCHT_2 0x00C00000 // 2 system clock periods 589 #define SYSCTL_MEMTIM0_EBCHT_2_5 \ 590 0x01000000 // 2.5 system clock periods 591 #define SYSCTL_MEMTIM0_EBCHT_3 0x01400000 // 3 system clock periods 592 #define SYSCTL_MEMTIM0_EBCHT_3_5 \ 593 0x01800000 // 3.5 system clock periods 594 #define SYSCTL_MEMTIM0_EBCHT_4 0x01C00000 // 4 system clock periods 595 #define SYSCTL_MEMTIM0_EBCHT_4_5 \ 596 0x02000000 // 4.5 system clock periods 597 #define SYSCTL_MEMTIM0_EBCE 0x00200000 // EEPROM Bank Clock Edge 598 #define SYSCTL_MEMTIM0_MB1 0x00100010 // Must be one 599 #define SYSCTL_MEMTIM0_EWS_M 0x000F0000 // EEPROM Wait States 600 #define SYSCTL_MEMTIM0_FBCHT_M 0x000003C0 // Flash Bank Clock High Time 601 #define SYSCTL_MEMTIM0_FBCHT_0_5 \ 602 0x00000000 // 1/2 system clock period 603 #define SYSCTL_MEMTIM0_FBCHT_1 0x00000040 // 1 system clock period 604 #define SYSCTL_MEMTIM0_FBCHT_1_5 \ 605 0x00000080 // 1.5 system clock periods 606 #define SYSCTL_MEMTIM0_FBCHT_2 0x000000C0 // 2 system clock periods 607 #define SYSCTL_MEMTIM0_FBCHT_2_5 \ 608 0x00000100 // 2.5 system clock periods 609 #define SYSCTL_MEMTIM0_FBCHT_3 0x00000140 // 3 system clock periods 610 #define SYSCTL_MEMTIM0_FBCHT_3_5 \ 611 0x00000180 // 3.5 system clock periods 612 #define SYSCTL_MEMTIM0_FBCHT_4 0x000001C0 // 4 system clock periods 613 #define SYSCTL_MEMTIM0_FBCHT_4_5 \ 614 0x00000200 // 4.5 system clock periods 615 #define SYSCTL_MEMTIM0_FBCE 0x00000020 // Flash Bank Clock Edge 616 #define SYSCTL_MEMTIM0_FWS_M 0x0000000F // Flash Wait State 617 #define SYSCTL_MEMTIM0_EWS_S 16 618 #define SYSCTL_MEMTIM0_FWS_S 0 626 #define SYSCTL_ALTCLKCFG_ALTCLK_M \ 627 0x0000000F // Alternate Clock Source 628 #define SYSCTL_ALTCLKCFG_ALTCLK_PIOSC \ 630 #define SYSCTL_ALTCLKCFG_ALTCLK_RTCOSC \ 631 0x00000003 // Hibernation Module Real-time 633 #define SYSCTL_ALTCLKCFG_ALTCLK_LFIOSC \ 634 0x00000004 // Low-frequency internal 643 #define SYSCTL_DSCLKCFG_PIOSCPD 0x80000000 // PIOSC Power Down 644 #define SYSCTL_DSCLKCFG_MOSCDPD 0x40000000 // MOSC Disable Power Down 645 #define SYSCTL_DSCLKCFG_DSOSCSRC_M \ 646 0x00F00000 // Deep Sleep Oscillator Source 647 #define SYSCTL_DSCLKCFG_DSOSCSRC_PIOSC \ 649 #define SYSCTL_DSCLKCFG_DSOSCSRC_LFIOSC \ 651 #define SYSCTL_DSCLKCFG_DSOSCSRC_MOSC \ 653 #define SYSCTL_DSCLKCFG_DSOSCSRC_RTC \ 654 0x00400000 // Hibernation Module RTCOSC 655 #define SYSCTL_DSCLKCFG_DSSYSDIV_M \ 656 0x000003FF // Deep Sleep Clock Divisor 657 #define SYSCTL_DSCLKCFG_DSSYSDIV_S \ 665 #define SYSCTL_DIVSCLK_EN 0x80000000 // DIVSCLK Enable 666 #define SYSCTL_DIVSCLK_SRC_M 0x00030000 // Clock Source 667 #define SYSCTL_DIVSCLK_SRC_SYSCLK \ 668 0x00000000 // System Clock 669 #define SYSCTL_DIVSCLK_SRC_PIOSC \ 671 #define SYSCTL_DIVSCLK_SRC_MOSC 0x00020000 // MOSC 672 #define SYSCTL_DIVSCLK_DIV_M 0x000000FF // Divisor Value 673 #define SYSCTL_DIVSCLK_DIV_S 0 680 #define SYSCTL_SYSPROP_FPU 0x00000001 // FPU Present 688 #define SYSCTL_PIOSCCAL_UTEN 0x80000000 // Use User Trim Value 689 #define SYSCTL_PIOSCCAL_CAL 0x00000200 // Start Calibration 690 #define SYSCTL_PIOSCCAL_UPDATE 0x00000100 // Update Trim 691 #define SYSCTL_PIOSCCAL_UT_M 0x0000007F // User Trim Value 692 #define SYSCTL_PIOSCCAL_UT_S 0 700 #define SYSCTL_PIOSCSTAT_DT_M 0x007F0000 // Default Trim Value 701 #define SYSCTL_PIOSCSTAT_CR_M 0x00000300 // Calibration Result 702 #define SYSCTL_PIOSCSTAT_CRNONE 0x00000000 // Calibration has not been 704 #define SYSCTL_PIOSCSTAT_CRPASS 0x00000100 // The last calibration operation 706 #define SYSCTL_PIOSCSTAT_CRFAIL 0x00000200 // The last calibration operation 708 #define SYSCTL_PIOSCSTAT_CT_M 0x0000007F // Calibration Trim Value 709 #define SYSCTL_PIOSCSTAT_DT_S 16 710 #define SYSCTL_PIOSCSTAT_CT_S 0 718 #define SYSCTL_PLLFREQ0_PLLPWR 0x00800000 // PLL Power 719 #define SYSCTL_PLLFREQ0_MFRAC_M 0x000FFC00 // PLL M Fractional Value 720 #define SYSCTL_PLLFREQ0_MINT_M 0x000003FF // PLL M Integer Value 721 #define SYSCTL_PLLFREQ0_MFRAC_S 10 722 #define SYSCTL_PLLFREQ0_MINT_S 0 730 #define SYSCTL_PLLFREQ1_Q_M 0x00001F00 // PLL Q Value 731 #define SYSCTL_PLLFREQ1_N_M 0x0000001F // PLL N Value 732 #define SYSCTL_PLLFREQ1_Q_S 8 733 #define SYSCTL_PLLFREQ1_N_S 0 740 #define SYSCTL_PLLSTAT_LOCK 0x00000001 // PLL Lock 748 #define SYSCTL_SLPPWRCFG_FLASHPM_M \ 749 0x00000030 // Flash Power Modes 750 #define SYSCTL_SLPPWRCFG_FLASHPM_NRM \ 751 0x00000000 // Active Mode 752 #define SYSCTL_SLPPWRCFG_FLASHPM_SLP \ 753 0x00000020 // Low Power Mode 754 #define SYSCTL_SLPPWRCFG_SRAMPM_M \ 755 0x00000003 // SRAM Power Modes 756 #define SYSCTL_SLPPWRCFG_SRAMPM_NRM \ 757 0x00000000 // Active Mode 758 #define SYSCTL_SLPPWRCFG_SRAMPM_SBY \ 759 0x00000001 // Standby Mode 760 #define SYSCTL_SLPPWRCFG_SRAMPM_LP \ 761 0x00000003 // Low Power Mode 769 #define SYSCTL_DSLPPWRCFG_LDOSM 0x00000200 // LDO Sleep Mode 770 #define SYSCTL_DSLPPWRCFG_TSPD 0x00000100 // Temperature Sense Power Down 771 #define SYSCTL_DSLPPWRCFG_FLASHPM_M \ 772 0x00000030 // Flash Power Modes 773 #define SYSCTL_DSLPPWRCFG_FLASHPM_NRM \ 774 0x00000000 // Active Mode 775 #define SYSCTL_DSLPPWRCFG_FLASHPM_SLP \ 776 0x00000020 // Low Power Mode 777 #define SYSCTL_DSLPPWRCFG_SRAMPM_M \ 778 0x00000003 // SRAM Power Modes 779 #define SYSCTL_DSLPPWRCFG_SRAMPM_NRM \ 780 0x00000000 // Active Mode 781 #define SYSCTL_DSLPPWRCFG_SRAMPM_SBY \ 782 0x00000001 // Standby Mode 783 #define SYSCTL_DSLPPWRCFG_SRAMPM_LP \ 784 0x00000003 // Low Power Mode 791 #define SYSCTL_NVMSTAT_FWB 0x00000001 // 32 Word Flash Write Buffer 800 #define SYSCTL_LDOSPCTL_VADJEN 0x80000000 // Voltage Adjust Enable 801 #define SYSCTL_LDOSPCTL_VLDO_M 0x000000FF // LDO Output Voltage 802 #define SYSCTL_LDOSPCTL_VLDO_0_90V \ 804 #define SYSCTL_LDOSPCTL_VLDO_0_95V \ 806 #define SYSCTL_LDOSPCTL_VLDO_1_00V \ 808 #define SYSCTL_LDOSPCTL_VLDO_1_05V \ 810 #define SYSCTL_LDOSPCTL_VLDO_1_10V \ 812 #define SYSCTL_LDOSPCTL_VLDO_1_15V \ 814 #define SYSCTL_LDOSPCTL_VLDO_1_20V \ 823 #define SYSCTL_LDODPCTL_VADJEN 0x80000000 // Voltage Adjust Enable 824 #define SYSCTL_LDODPCTL_VLDO_M 0x000000FF // LDO Output Voltage 825 #define SYSCTL_LDODPCTL_VLDO_0_90V \ 827 #define SYSCTL_LDODPCTL_VLDO_0_95V \ 829 #define SYSCTL_LDODPCTL_VLDO_1_00V \ 831 #define SYSCTL_LDODPCTL_VLDO_1_05V \ 833 #define SYSCTL_LDODPCTL_VLDO_1_10V \ 835 #define SYSCTL_LDODPCTL_VLDO_1_15V \ 837 #define SYSCTL_LDODPCTL_VLDO_1_20V \ 846 #define SYSCTL_RESBEHAVCTL_WDOG1_M \ 847 0x000000C0 // Watchdog 1 Reset Operation 848 #define SYSCTL_RESBEHAVCTL_WDOG1_SYSRST \ 849 0x00000080 // Watchdog 1 issues a system 852 #define SYSCTL_RESBEHAVCTL_WDOG1_POR \ 853 0x000000C0 // Watchdog 1 issues a simulated 857 #define SYSCTL_RESBEHAVCTL_WDOG0_M \ 858 0x00000030 // Watchdog 0 Reset Operation 859 #define SYSCTL_RESBEHAVCTL_WDOG0_SYSRST \ 860 0x00000020 // Watchdog 0 issues a system 863 #define SYSCTL_RESBEHAVCTL_WDOG0_POR \ 864 0x00000030 // Watchdog 0 issues a simulated 868 #define SYSCTL_RESBEHAVCTL_BOR_M \ 869 0x0000000C // BOR Reset operation 870 #define SYSCTL_RESBEHAVCTL_BOR_SYSRST \ 871 0x00000008 // Brown Out Reset issues system 874 #define SYSCTL_RESBEHAVCTL_BOR_POR \ 875 0x0000000C // Brown Out Reset issues a 879 #define SYSCTL_RESBEHAVCTL_EXTRES_M \ 880 0x00000003 // External RST Pin Operation 881 #define SYSCTL_RESBEHAVCTL_EXTRES_SYSRST \ 882 0x00000002 // External RST assertion issues a 885 #define SYSCTL_RESBEHAVCTL_EXTRES_POR \ 886 0x00000003 // External RST assertion issues a 896 #define SYSCTL_HSSR_KEY_M 0xFF000000 // Write Key 897 #define SYSCTL_HSSR_CDOFF_M 0x00FFFFFF // Command Descriptor Pointer 898 #define SYSCTL_HSSR_KEY_S 24 899 #define SYSCTL_HSSR_CDOFF_S 0 906 #define SYSCTL_USBPDS_MEMSTAT_M 0x0000000C // Memory Array Power Status 907 #define SYSCTL_USBPDS_MEMSTAT_OFF \ 908 0x00000000 // Array OFF 909 #define SYSCTL_USBPDS_MEMSTAT_RETAIN \ 910 0x00000004 // SRAM Retention 911 #define SYSCTL_USBPDS_MEMSTAT_ON \ 912 0x0000000C // Array On 913 #define SYSCTL_USBPDS_PWRSTAT_M 0x00000003 // Power Domain Status 914 #define SYSCTL_USBPDS_PWRSTAT_OFF \ 916 #define SYSCTL_USBPDS_PWRSTAT_ON \ 924 #define SYSCTL_USBMPC_PWRCTL_M 0x00000003 // Memory Array Power Control 925 #define SYSCTL_USBMPC_PWRCTL_OFF \ 926 0x00000000 // Array OFF 927 #define SYSCTL_USBMPC_PWRCTL_RETAIN \ 928 0x00000001 // SRAM Retention 929 #define SYSCTL_USBMPC_PWRCTL_ON 0x00000003 // Array On 936 #define SYSCTL_EMACPDS_MEMSTAT_M \ 937 0x0000000C // Memory Array Power Status 938 #define SYSCTL_EMACPDS_MEMSTAT_OFF \ 939 0x00000000 // Array OFF 940 #define SYSCTL_EMACPDS_MEMSTAT_ON \ 941 0x0000000C // Array On 942 #define SYSCTL_EMACPDS_PWRSTAT_M \ 943 0x00000003 // Power Domain Status 944 #define SYSCTL_EMACPDS_PWRSTAT_OFF \ 946 #define SYSCTL_EMACPDS_PWRSTAT_ON \ 954 #define SYSCTL_EMACMPC_PWRCTL_M 0x00000003 // Memory Array Power Control 955 #define SYSCTL_EMACMPC_PWRCTL_OFF \ 956 0x00000000 // Array OFF 957 #define SYSCTL_EMACMPC_PWRCTL_ON \ 958 0x00000003 // Array On 965 #define SYSCTL_LCDMPC_PWRCTL_M 0x00000003 // Memory Array Power Control 966 #define SYSCTL_LCDMPC_PWRCTL_OFF \ 967 0x00000000 // Array OFF 968 #define SYSCTL_LCDMPC_PWRCTL_ON 0x00000003 // Array On 975 #define SYSCTL_PPWD_P1 0x00000002 // Watchdog Timer 1 Present 976 #define SYSCTL_PPWD_P0 0x00000001 // Watchdog Timer 0 Present 983 #define SYSCTL_PPTIMER_P7 0x00000080 // 16/32-Bit General-Purpose Timer 985 #define SYSCTL_PPTIMER_P6 0x00000040 // 16/32-Bit General-Purpose Timer 987 #define SYSCTL_PPTIMER_P5 0x00000020 // 16/32-Bit General-Purpose Timer 989 #define SYSCTL_PPTIMER_P4 0x00000010 // 16/32-Bit General-Purpose Timer 991 #define SYSCTL_PPTIMER_P3 0x00000008 // 16/32-Bit General-Purpose Timer 993 #define SYSCTL_PPTIMER_P2 0x00000004 // 16/32-Bit General-Purpose Timer 995 #define SYSCTL_PPTIMER_P1 0x00000002 // 16/32-Bit General-Purpose Timer 997 #define SYSCTL_PPTIMER_P0 0x00000001 // 16/32-Bit General-Purpose Timer 1005 #define SYSCTL_PPGPIO_P17 0x00020000 // GPIO Port T Present 1006 #define SYSCTL_PPGPIO_P16 0x00010000 // GPIO Port S Present 1007 #define SYSCTL_PPGPIO_P15 0x00008000 // GPIO Port R Present 1008 #define SYSCTL_PPGPIO_P14 0x00004000 // GPIO Port Q Present 1009 #define SYSCTL_PPGPIO_P13 0x00002000 // GPIO Port P Present 1010 #define SYSCTL_PPGPIO_P12 0x00001000 // GPIO Port N Present 1011 #define SYSCTL_PPGPIO_P11 0x00000800 // GPIO Port M Present 1012 #define SYSCTL_PPGPIO_P10 0x00000400 // GPIO Port L Present 1013 #define SYSCTL_PPGPIO_P9 0x00000200 // GPIO Port K Present 1014 #define SYSCTL_PPGPIO_P8 0x00000100 // GPIO Port J Present 1015 #define SYSCTL_PPGPIO_P7 0x00000080 // GPIO Port H Present 1016 #define SYSCTL_PPGPIO_P6 0x00000040 // GPIO Port G Present 1017 #define SYSCTL_PPGPIO_P5 0x00000020 // GPIO Port F Present 1018 #define SYSCTL_PPGPIO_P4 0x00000010 // GPIO Port E Present 1019 #define SYSCTL_PPGPIO_P3 0x00000008 // GPIO Port D Present 1020 #define SYSCTL_PPGPIO_P2 0x00000004 // GPIO Port C Present 1021 #define SYSCTL_PPGPIO_P1 0x00000002 // GPIO Port B Present 1022 #define SYSCTL_PPGPIO_P0 0x00000001 // GPIO Port A Present 1029 #define SYSCTL_PPDMA_P0 0x00000001 // uDMA Module Present 1036 #define SYSCTL_PPEPI_P0 0x00000001 // EPI Module Present 1043 #define SYSCTL_PPHIB_P0 0x00000001 // Hibernation Module Present 1050 #define SYSCTL_PPUART_P7 0x00000080 // UART Module 7 Present 1051 #define SYSCTL_PPUART_P6 0x00000040 // UART Module 6 Present 1052 #define SYSCTL_PPUART_P5 0x00000020 // UART Module 5 Present 1053 #define SYSCTL_PPUART_P4 0x00000010 // UART Module 4 Present 1054 #define SYSCTL_PPUART_P3 0x00000008 // UART Module 3 Present 1055 #define SYSCTL_PPUART_P2 0x00000004 // UART Module 2 Present 1056 #define SYSCTL_PPUART_P1 0x00000002 // UART Module 1 Present 1057 #define SYSCTL_PPUART_P0 0x00000001 // UART Module 0 Present 1064 #define SYSCTL_PPSSI_P3 0x00000008 // SSI Module 3 Present 1065 #define SYSCTL_PPSSI_P2 0x00000004 // SSI Module 2 Present 1066 #define SYSCTL_PPSSI_P1 0x00000002 // SSI Module 1 Present 1067 #define SYSCTL_PPSSI_P0 0x00000001 // SSI Module 0 Present 1074 #define SYSCTL_PPI2C_P9 0x00000200 // I2C Module 9 Present 1075 #define SYSCTL_PPI2C_P8 0x00000100 // I2C Module 8 Present 1076 #define SYSCTL_PPI2C_P7 0x00000080 // I2C Module 7 Present 1077 #define SYSCTL_PPI2C_P6 0x00000040 // I2C Module 6 Present 1078 #define SYSCTL_PPI2C_P5 0x00000020 // I2C Module 5 Present 1079 #define SYSCTL_PPI2C_P4 0x00000010 // I2C Module 4 Present 1080 #define SYSCTL_PPI2C_P3 0x00000008 // I2C Module 3 Present 1081 #define SYSCTL_PPI2C_P2 0x00000004 // I2C Module 2 Present 1082 #define SYSCTL_PPI2C_P1 0x00000002 // I2C Module 1 Present 1083 #define SYSCTL_PPI2C_P0 0x00000001 // I2C Module 0 Present 1090 #define SYSCTL_PPUSB_P0 0x00000001 // USB Module Present 1097 #define SYSCTL_PPEPHY_P0 0x00000001 // Ethernet PHY Module Present 1104 #define SYSCTL_PPCAN_P1 0x00000002 // CAN Module 1 Present 1105 #define SYSCTL_PPCAN_P0 0x00000001 // CAN Module 0 Present 1112 #define SYSCTL_PPADC_P1 0x00000002 // ADC Module 1 Present 1113 #define SYSCTL_PPADC_P0 0x00000001 // ADC Module 0 Present 1120 #define SYSCTL_PPACMP_P0 0x00000001 // Analog Comparator Module Present 1127 #define SYSCTL_PPPWM_P1 0x00000002 // PWM Module 1 Present 1128 #define SYSCTL_PPPWM_P0 0x00000001 // PWM Module 0 Present 1135 #define SYSCTL_PPQEI_P1 0x00000002 // QEI Module 1 Present 1136 #define SYSCTL_PPQEI_P0 0x00000001 // QEI Module 0 Present 1144 #define SYSCTL_PPEEPROM_P0 0x00000001 // EEPROM Module Present 1151 #define SYSCTL_PPCCM_P0 0x00000001 // CRC and Cryptographic Modules 1159 #define SYSCTL_PPLCD_P0 0x00000001 // LCD Module Present 1166 #define SYSCTL_PPOWIRE_P0 0x00000001 // 1-Wire Module Present 1173 #define SYSCTL_PPEMAC_P0 0x00000001 // Ethernet Controller Module 1181 #define SYSCTL_SRWD_R1 0x00000002 // Watchdog Timer 1 Software Reset 1182 #define SYSCTL_SRWD_R0 0x00000001 // Watchdog Timer 0 Software Reset 1189 #define SYSCTL_SRTIMER_R7 0x00000080 // 16/32-Bit General-Purpose Timer 1191 #define SYSCTL_SRTIMER_R6 0x00000040 // 16/32-Bit General-Purpose Timer 1193 #define SYSCTL_SRTIMER_R5 0x00000020 // 16/32-Bit General-Purpose Timer 1195 #define SYSCTL_SRTIMER_R4 0x00000010 // 16/32-Bit General-Purpose Timer 1197 #define SYSCTL_SRTIMER_R3 0x00000008 // 16/32-Bit General-Purpose Timer 1199 #define SYSCTL_SRTIMER_R2 0x00000004 // 16/32-Bit General-Purpose Timer 1201 #define SYSCTL_SRTIMER_R1 0x00000002 // 16/32-Bit General-Purpose Timer 1203 #define SYSCTL_SRTIMER_R0 0x00000001 // 16/32-Bit General-Purpose Timer 1211 #define SYSCTL_SRGPIO_R17 0x00020000 // GPIO Port T Software Reset 1212 #define SYSCTL_SRGPIO_R16 0x00010000 // GPIO Port S Software Reset 1213 #define SYSCTL_SRGPIO_R15 0x00008000 // GPIO Port R Software Reset 1214 #define SYSCTL_SRGPIO_R14 0x00004000 // GPIO Port Q Software Reset 1215 #define SYSCTL_SRGPIO_R13 0x00002000 // GPIO Port P Software Reset 1216 #define SYSCTL_SRGPIO_R12 0x00001000 // GPIO Port N Software Reset 1217 #define SYSCTL_SRGPIO_R11 0x00000800 // GPIO Port M Software Reset 1218 #define SYSCTL_SRGPIO_R10 0x00000400 // GPIO Port L Software Reset 1219 #define SYSCTL_SRGPIO_R9 0x00000200 // GPIO Port K Software Reset 1220 #define SYSCTL_SRGPIO_R8 0x00000100 // GPIO Port J Software Reset 1221 #define SYSCTL_SRGPIO_R7 0x00000080 // GPIO Port H Software Reset 1222 #define SYSCTL_SRGPIO_R6 0x00000040 // GPIO Port G Software Reset 1223 #define SYSCTL_SRGPIO_R5 0x00000020 // GPIO Port F Software Reset 1224 #define SYSCTL_SRGPIO_R4 0x00000010 // GPIO Port E Software Reset 1225 #define SYSCTL_SRGPIO_R3 0x00000008 // GPIO Port D Software Reset 1226 #define SYSCTL_SRGPIO_R2 0x00000004 // GPIO Port C Software Reset 1227 #define SYSCTL_SRGPIO_R1 0x00000002 // GPIO Port B Software Reset 1228 #define SYSCTL_SRGPIO_R0 0x00000001 // GPIO Port A Software Reset 1235 #define SYSCTL_SRDMA_R0 0x00000001 // uDMA Module Software Reset 1242 #define SYSCTL_SREPI_R0 0x00000001 // EPI Module Software Reset 1249 #define SYSCTL_SRHIB_R0 0x00000001 // Hibernation Module Software 1257 #define SYSCTL_SRUART_R7 0x00000080 // UART Module 7 Software Reset 1258 #define SYSCTL_SRUART_R6 0x00000040 // UART Module 6 Software Reset 1259 #define SYSCTL_SRUART_R5 0x00000020 // UART Module 5 Software Reset 1260 #define SYSCTL_SRUART_R4 0x00000010 // UART Module 4 Software Reset 1261 #define SYSCTL_SRUART_R3 0x00000008 // UART Module 3 Software Reset 1262 #define SYSCTL_SRUART_R2 0x00000004 // UART Module 2 Software Reset 1263 #define SYSCTL_SRUART_R1 0x00000002 // UART Module 1 Software Reset 1264 #define SYSCTL_SRUART_R0 0x00000001 // UART Module 0 Software Reset 1271 #define SYSCTL_SRSSI_R3 0x00000008 // SSI Module 3 Software Reset 1272 #define SYSCTL_SRSSI_R2 0x00000004 // SSI Module 2 Software Reset 1273 #define SYSCTL_SRSSI_R1 0x00000002 // SSI Module 1 Software Reset 1274 #define SYSCTL_SRSSI_R0 0x00000001 // SSI Module 0 Software Reset 1281 #define SYSCTL_SRI2C_R9 0x00000200 // I2C Module 9 Software Reset 1282 #define SYSCTL_SRI2C_R8 0x00000100 // I2C Module 8 Software Reset 1283 #define SYSCTL_SRI2C_R7 0x00000080 // I2C Module 7 Software Reset 1284 #define SYSCTL_SRI2C_R6 0x00000040 // I2C Module 6 Software Reset 1285 #define SYSCTL_SRI2C_R5 0x00000020 // I2C Module 5 Software Reset 1286 #define SYSCTL_SRI2C_R4 0x00000010 // I2C Module 4 Software Reset 1287 #define SYSCTL_SRI2C_R3 0x00000008 // I2C Module 3 Software Reset 1288 #define SYSCTL_SRI2C_R2 0x00000004 // I2C Module 2 Software Reset 1289 #define SYSCTL_SRI2C_R1 0x00000002 // I2C Module 1 Software Reset 1290 #define SYSCTL_SRI2C_R0 0x00000001 // I2C Module 0 Software Reset 1297 #define SYSCTL_SRUSB_R0 0x00000001 // USB Module Software Reset 1304 #define SYSCTL_SREPHY_R0 0x00000001 // Ethernet PHY Module Software 1312 #define SYSCTL_SRCAN_R1 0x00000002 // CAN Module 1 Software Reset 1313 #define SYSCTL_SRCAN_R0 0x00000001 // CAN Module 0 Software Reset 1320 #define SYSCTL_SRADC_R1 0x00000002 // ADC Module 1 Software Reset 1321 #define SYSCTL_SRADC_R0 0x00000001 // ADC Module 0 Software Reset 1328 #define SYSCTL_SRACMP_R0 0x00000001 // Analog Comparator Module 0 1336 #define SYSCTL_SRPWM_R1 0x00000002 // PWM Module 1 Software Reset 1337 #define SYSCTL_SRPWM_R0 0x00000001 // PWM Module 0 Software Reset 1344 #define SYSCTL_SRQEI_R1 0x00000002 // QEI Module 1 Software Reset 1345 #define SYSCTL_SRQEI_R0 0x00000001 // QEI Module 0 Software Reset 1353 #define SYSCTL_SREEPROM_R0 0x00000001 // EEPROM Module Software Reset 1360 #define SYSCTL_SRCCM_R0 0x00000001 // CRC and Cryptographic Modules 1368 #define SYSCTL_SRLCD_R0 0x00000001 // LCD Module 0 Software Reset 1375 #define SYSCTL_SROWIRE_R0 0x00000001 // 1-Wire Module Software Reset 1382 #define SYSCTL_SREMAC_R0 0x00000001 // Ethernet Controller MAC Module 0 1390 #define SYSCTL_RCGCWD_R1 0x00000002 // Watchdog Timer 1 Run Mode Clock 1392 #define SYSCTL_RCGCWD_R0 0x00000001 // Watchdog Timer 0 Run Mode Clock 1401 #define SYSCTL_RCGCTIMER_R7 0x00000080 // 16/32-Bit General-Purpose Timer 1403 #define SYSCTL_RCGCTIMER_R6 0x00000040 // 16/32-Bit General-Purpose Timer 1405 #define SYSCTL_RCGCTIMER_R5 0x00000020 // 16/32-Bit General-Purpose Timer 1407 #define SYSCTL_RCGCTIMER_R4 0x00000010 // 16/32-Bit General-Purpose Timer 1409 #define SYSCTL_RCGCTIMER_R3 0x00000008 // 16/32-Bit General-Purpose Timer 1411 #define SYSCTL_RCGCTIMER_R2 0x00000004 // 16/32-Bit General-Purpose Timer 1413 #define SYSCTL_RCGCTIMER_R1 0x00000002 // 16/32-Bit General-Purpose Timer 1415 #define SYSCTL_RCGCTIMER_R0 0x00000001 // 16/32-Bit General-Purpose Timer 1424 #define SYSCTL_RCGCGPIO_R17 0x00020000 // GPIO Port T Run Mode Clock 1426 #define SYSCTL_RCGCGPIO_R16 0x00010000 // GPIO Port S Run Mode Clock 1428 #define SYSCTL_RCGCGPIO_R15 0x00008000 // GPIO Port R Run Mode Clock 1430 #define SYSCTL_RCGCGPIO_R14 0x00004000 // GPIO Port Q Run Mode Clock 1432 #define SYSCTL_RCGCGPIO_R13 0x00002000 // GPIO Port P Run Mode Clock 1434 #define SYSCTL_RCGCGPIO_R12 0x00001000 // GPIO Port N Run Mode Clock 1436 #define SYSCTL_RCGCGPIO_R11 0x00000800 // GPIO Port M Run Mode Clock 1438 #define SYSCTL_RCGCGPIO_R10 0x00000400 // GPIO Port L Run Mode Clock 1440 #define SYSCTL_RCGCGPIO_R9 0x00000200 // GPIO Port K Run Mode Clock 1442 #define SYSCTL_RCGCGPIO_R8 0x00000100 // GPIO Port J Run Mode Clock 1444 #define SYSCTL_RCGCGPIO_R7 0x00000080 // GPIO Port H Run Mode Clock 1446 #define SYSCTL_RCGCGPIO_R6 0x00000040 // GPIO Port G Run Mode Clock 1448 #define SYSCTL_RCGCGPIO_R5 0x00000020 // GPIO Port F Run Mode Clock 1450 #define SYSCTL_RCGCGPIO_R4 0x00000010 // GPIO Port E Run Mode Clock 1452 #define SYSCTL_RCGCGPIO_R3 0x00000008 // GPIO Port D Run Mode Clock 1454 #define SYSCTL_RCGCGPIO_R2 0x00000004 // GPIO Port C Run Mode Clock 1456 #define SYSCTL_RCGCGPIO_R1 0x00000002 // GPIO Port B Run Mode Clock 1458 #define SYSCTL_RCGCGPIO_R0 0x00000001 // GPIO Port A Run Mode Clock 1466 #define SYSCTL_RCGCDMA_R0 0x00000001 // uDMA Module Run Mode Clock 1474 #define SYSCTL_RCGCEPI_R0 0x00000001 // EPI Module Run Mode Clock Gating 1482 #define SYSCTL_RCGCHIB_R0 0x00000001 // Hibernation Module Run Mode 1491 #define SYSCTL_RCGCUART_R7 0x00000080 // UART Module 7 Run Mode Clock 1493 #define SYSCTL_RCGCUART_R6 0x00000040 // UART Module 6 Run Mode Clock 1495 #define SYSCTL_RCGCUART_R5 0x00000020 // UART Module 5 Run Mode Clock 1497 #define SYSCTL_RCGCUART_R4 0x00000010 // UART Module 4 Run Mode Clock 1499 #define SYSCTL_RCGCUART_R3 0x00000008 // UART Module 3 Run Mode Clock 1501 #define SYSCTL_RCGCUART_R2 0x00000004 // UART Module 2 Run Mode Clock 1503 #define SYSCTL_RCGCUART_R1 0x00000002 // UART Module 1 Run Mode Clock 1505 #define SYSCTL_RCGCUART_R0 0x00000001 // UART Module 0 Run Mode Clock 1513 #define SYSCTL_RCGCSSI_R3 0x00000008 // SSI Module 3 Run Mode Clock 1515 #define SYSCTL_RCGCSSI_R2 0x00000004 // SSI Module 2 Run Mode Clock 1517 #define SYSCTL_RCGCSSI_R1 0x00000002 // SSI Module 1 Run Mode Clock 1519 #define SYSCTL_RCGCSSI_R0 0x00000001 // SSI Module 0 Run Mode Clock 1527 #define SYSCTL_RCGCI2C_R9 0x00000200 // I2C Module 9 Run Mode Clock 1529 #define SYSCTL_RCGCI2C_R8 0x00000100 // I2C Module 8 Run Mode Clock 1531 #define SYSCTL_RCGCI2C_R7 0x00000080 // I2C Module 7 Run Mode Clock 1533 #define SYSCTL_RCGCI2C_R6 0x00000040 // I2C Module 6 Run Mode Clock 1535 #define SYSCTL_RCGCI2C_R5 0x00000020 // I2C Module 5 Run Mode Clock 1537 #define SYSCTL_RCGCI2C_R4 0x00000010 // I2C Module 4 Run Mode Clock 1539 #define SYSCTL_RCGCI2C_R3 0x00000008 // I2C Module 3 Run Mode Clock 1541 #define SYSCTL_RCGCI2C_R2 0x00000004 // I2C Module 2 Run Mode Clock 1543 #define SYSCTL_RCGCI2C_R1 0x00000002 // I2C Module 1 Run Mode Clock 1545 #define SYSCTL_RCGCI2C_R0 0x00000001 // I2C Module 0 Run Mode Clock 1553 #define SYSCTL_RCGCUSB_R0 0x00000001 // USB Module Run Mode Clock Gating 1562 #define SYSCTL_RCGCEPHY_R0 0x00000001 // Ethernet PHY Module Run Mode 1570 #define SYSCTL_RCGCCAN_R1 0x00000002 // CAN Module 1 Run Mode Clock 1572 #define SYSCTL_RCGCCAN_R0 0x00000001 // CAN Module 0 Run Mode Clock 1580 #define SYSCTL_RCGCADC_R1 0x00000002 // ADC Module 1 Run Mode Clock 1582 #define SYSCTL_RCGCADC_R0 0x00000001 // ADC Module 0 Run Mode Clock 1591 #define SYSCTL_RCGCACMP_R0 0x00000001 // Analog Comparator Module 0 Run 1599 #define SYSCTL_RCGCPWM_R1 0x00000002 // PWM Module 1 Run Mode Clock 1601 #define SYSCTL_RCGCPWM_R0 0x00000001 // PWM Module 0 Run Mode Clock 1609 #define SYSCTL_RCGCQEI_R1 0x00000002 // QEI Module 1 Run Mode Clock 1611 #define SYSCTL_RCGCQEI_R0 0x00000001 // QEI Module 0 Run Mode Clock 1620 #define SYSCTL_RCGCEEPROM_R0 0x00000001 // EEPROM Module Run Mode Clock 1628 #define SYSCTL_RCGCCCM_R0 0x00000001 // CRC and Cryptographic Modules 1636 #define SYSCTL_RCGCLCD_R0 0x00000001 // LCD Controller Module 0 Run Mode 1645 #define SYSCTL_RCGCOWIRE_R0 0x00000001 // 1-Wire Module 0 Run Mode Clock 1654 #define SYSCTL_RCGCEMAC_R0 0x00000001 // Ethernet MAC Module 0 Run Mode 1662 #define SYSCTL_SCGCWD_S1 0x00000002 // Watchdog Timer 1 Sleep Mode 1664 #define SYSCTL_SCGCWD_S0 0x00000001 // Watchdog Timer 0 Sleep Mode 1673 #define SYSCTL_SCGCTIMER_S7 0x00000080 // 16/32-Bit General-Purpose Timer 1676 #define SYSCTL_SCGCTIMER_S6 0x00000040 // 16/32-Bit General-Purpose Timer 1679 #define SYSCTL_SCGCTIMER_S5 0x00000020 // 16/32-Bit General-Purpose Timer 1682 #define SYSCTL_SCGCTIMER_S4 0x00000010 // 16/32-Bit General-Purpose Timer 1685 #define SYSCTL_SCGCTIMER_S3 0x00000008 // 16/32-Bit General-Purpose Timer 1688 #define SYSCTL_SCGCTIMER_S2 0x00000004 // 16/32-Bit General-Purpose Timer 1691 #define SYSCTL_SCGCTIMER_S1 0x00000002 // 16/32-Bit General-Purpose Timer 1694 #define SYSCTL_SCGCTIMER_S0 0x00000001 // 16/32-Bit General-Purpose Timer 1704 #define SYSCTL_SCGCGPIO_S17 0x00020000 // GPIO Port T Sleep Mode Clock 1706 #define SYSCTL_SCGCGPIO_S16 0x00010000 // GPIO Port S Sleep Mode Clock 1708 #define SYSCTL_SCGCGPIO_S15 0x00008000 // GPIO Port R Sleep Mode Clock 1710 #define SYSCTL_SCGCGPIO_S14 0x00004000 // GPIO Port Q Sleep Mode Clock 1712 #define SYSCTL_SCGCGPIO_S13 0x00002000 // GPIO Port P Sleep Mode Clock 1714 #define SYSCTL_SCGCGPIO_S12 0x00001000 // GPIO Port N Sleep Mode Clock 1716 #define SYSCTL_SCGCGPIO_S11 0x00000800 // GPIO Port M Sleep Mode Clock 1718 #define SYSCTL_SCGCGPIO_S10 0x00000400 // GPIO Port L Sleep Mode Clock 1720 #define SYSCTL_SCGCGPIO_S9 0x00000200 // GPIO Port K Sleep Mode Clock 1722 #define SYSCTL_SCGCGPIO_S8 0x00000100 // GPIO Port J Sleep Mode Clock 1724 #define SYSCTL_SCGCGPIO_S7 0x00000080 // GPIO Port H Sleep Mode Clock 1726 #define SYSCTL_SCGCGPIO_S6 0x00000040 // GPIO Port G Sleep Mode Clock 1728 #define SYSCTL_SCGCGPIO_S5 0x00000020 // GPIO Port F Sleep Mode Clock 1730 #define SYSCTL_SCGCGPIO_S4 0x00000010 // GPIO Port E Sleep Mode Clock 1732 #define SYSCTL_SCGCGPIO_S3 0x00000008 // GPIO Port D Sleep Mode Clock 1734 #define SYSCTL_SCGCGPIO_S2 0x00000004 // GPIO Port C Sleep Mode Clock 1736 #define SYSCTL_SCGCGPIO_S1 0x00000002 // GPIO Port B Sleep Mode Clock 1738 #define SYSCTL_SCGCGPIO_S0 0x00000001 // GPIO Port A Sleep Mode Clock 1746 #define SYSCTL_SCGCDMA_S0 0x00000001 // uDMA Module Sleep Mode Clock 1754 #define SYSCTL_SCGCEPI_S0 0x00000001 // EPI Module Sleep Mode Clock 1762 #define SYSCTL_SCGCHIB_S0 0x00000001 // Hibernation Module Sleep Mode 1771 #define SYSCTL_SCGCUART_S7 0x00000080 // UART Module 7 Sleep Mode Clock 1773 #define SYSCTL_SCGCUART_S6 0x00000040 // UART Module 6 Sleep Mode Clock 1775 #define SYSCTL_SCGCUART_S5 0x00000020 // UART Module 5 Sleep Mode Clock 1777 #define SYSCTL_SCGCUART_S4 0x00000010 // UART Module 4 Sleep Mode Clock 1779 #define SYSCTL_SCGCUART_S3 0x00000008 // UART Module 3 Sleep Mode Clock 1781 #define SYSCTL_SCGCUART_S2 0x00000004 // UART Module 2 Sleep Mode Clock 1783 #define SYSCTL_SCGCUART_S1 0x00000002 // UART Module 1 Sleep Mode Clock 1785 #define SYSCTL_SCGCUART_S0 0x00000001 // UART Module 0 Sleep Mode Clock 1793 #define SYSCTL_SCGCSSI_S3 0x00000008 // SSI Module 3 Sleep Mode Clock 1795 #define SYSCTL_SCGCSSI_S2 0x00000004 // SSI Module 2 Sleep Mode Clock 1797 #define SYSCTL_SCGCSSI_S1 0x00000002 // SSI Module 1 Sleep Mode Clock 1799 #define SYSCTL_SCGCSSI_S0 0x00000001 // SSI Module 0 Sleep Mode Clock 1807 #define SYSCTL_SCGCI2C_S9 0x00000200 // I2C Module 9 Sleep Mode Clock 1809 #define SYSCTL_SCGCI2C_S8 0x00000100 // I2C Module 8 Sleep Mode Clock 1811 #define SYSCTL_SCGCI2C_S7 0x00000080 // I2C Module 7 Sleep Mode Clock 1813 #define SYSCTL_SCGCI2C_S6 0x00000040 // I2C Module 6 Sleep Mode Clock 1815 #define SYSCTL_SCGCI2C_S5 0x00000020 // I2C Module 5 Sleep Mode Clock 1817 #define SYSCTL_SCGCI2C_S4 0x00000010 // I2C Module 4 Sleep Mode Clock 1819 #define SYSCTL_SCGCI2C_S3 0x00000008 // I2C Module 3 Sleep Mode Clock 1821 #define SYSCTL_SCGCI2C_S2 0x00000004 // I2C Module 2 Sleep Mode Clock 1823 #define SYSCTL_SCGCI2C_S1 0x00000002 // I2C Module 1 Sleep Mode Clock 1825 #define SYSCTL_SCGCI2C_S0 0x00000001 // I2C Module 0 Sleep Mode Clock 1833 #define SYSCTL_SCGCUSB_S0 0x00000001 // USB Module Sleep Mode Clock 1842 #define SYSCTL_SCGCEPHY_S0 0x00000001 // PHY Module Sleep Mode Clock 1850 #define SYSCTL_SCGCCAN_S1 0x00000002 // CAN Module 1 Sleep Mode Clock 1852 #define SYSCTL_SCGCCAN_S0 0x00000001 // CAN Module 0 Sleep Mode Clock 1860 #define SYSCTL_SCGCADC_S1 0x00000002 // ADC Module 1 Sleep Mode Clock 1862 #define SYSCTL_SCGCADC_S0 0x00000001 // ADC Module 0 Sleep Mode Clock 1871 #define SYSCTL_SCGCACMP_S0 0x00000001 // Analog Comparator Module 0 Sleep 1879 #define SYSCTL_SCGCPWM_S1 0x00000002 // PWM Module 1 Sleep Mode Clock 1881 #define SYSCTL_SCGCPWM_S0 0x00000001 // PWM Module 0 Sleep Mode Clock 1889 #define SYSCTL_SCGCQEI_S1 0x00000002 // QEI Module 1 Sleep Mode Clock 1891 #define SYSCTL_SCGCQEI_S0 0x00000001 // QEI Module 0 Sleep Mode Clock 1900 #define SYSCTL_SCGCEEPROM_S0 0x00000001 // EEPROM Module Sleep Mode Clock 1908 #define SYSCTL_SCGCCCM_S0 0x00000001 // CRC and Cryptographic Modules 1916 #define SYSCTL_SCGCLCD_S0 0x00000001 // LCD Controller Module 0 Sleep 1925 #define SYSCTL_SCGCOWIRE_S0 0x00000001 // 1-Wire Module 0 Sleep Mode Clock 1934 #define SYSCTL_SCGCEMAC_S0 0x00000001 // Ethernet MAC Module 0 Sleep Mode 1942 #define SYSCTL_DCGCWD_D1 0x00000002 // Watchdog Timer 1 Deep-Sleep Mode 1944 #define SYSCTL_DCGCWD_D0 0x00000001 // Watchdog Timer 0 Deep-Sleep Mode 1953 #define SYSCTL_DCGCTIMER_D7 0x00000080 // 16/32-Bit General-Purpose Timer 1956 #define SYSCTL_DCGCTIMER_D6 0x00000040 // 16/32-Bit General-Purpose Timer 1959 #define SYSCTL_DCGCTIMER_D5 0x00000020 // 16/32-Bit General-Purpose Timer 1962 #define SYSCTL_DCGCTIMER_D4 0x00000010 // 16/32-Bit General-Purpose Timer 1965 #define SYSCTL_DCGCTIMER_D3 0x00000008 // 16/32-Bit General-Purpose Timer 1968 #define SYSCTL_DCGCTIMER_D2 0x00000004 // 16/32-Bit General-Purpose Timer 1971 #define SYSCTL_DCGCTIMER_D1 0x00000002 // 16/32-Bit General-Purpose Timer 1974 #define SYSCTL_DCGCTIMER_D0 0x00000001 // 16/32-Bit General-Purpose Timer 1984 #define SYSCTL_DCGCGPIO_D17 0x00020000 // GPIO Port T Deep-Sleep Mode 1986 #define SYSCTL_DCGCGPIO_D16 0x00010000 // GPIO Port S Deep-Sleep Mode 1988 #define SYSCTL_DCGCGPIO_D15 0x00008000 // GPIO Port R Deep-Sleep Mode 1990 #define SYSCTL_DCGCGPIO_D14 0x00004000 // GPIO Port Q Deep-Sleep Mode 1992 #define SYSCTL_DCGCGPIO_D13 0x00002000 // GPIO Port P Deep-Sleep Mode 1994 #define SYSCTL_DCGCGPIO_D12 0x00001000 // GPIO Port N Deep-Sleep Mode 1996 #define SYSCTL_DCGCGPIO_D11 0x00000800 // GPIO Port M Deep-Sleep Mode 1998 #define SYSCTL_DCGCGPIO_D10 0x00000400 // GPIO Port L Deep-Sleep Mode 2000 #define SYSCTL_DCGCGPIO_D9 0x00000200 // GPIO Port K Deep-Sleep Mode 2002 #define SYSCTL_DCGCGPIO_D8 0x00000100 // GPIO Port J Deep-Sleep Mode 2004 #define SYSCTL_DCGCGPIO_D7 0x00000080 // GPIO Port H Deep-Sleep Mode 2006 #define SYSCTL_DCGCGPIO_D6 0x00000040 // GPIO Port G Deep-Sleep Mode 2008 #define SYSCTL_DCGCGPIO_D5 0x00000020 // GPIO Port F Deep-Sleep Mode 2010 #define SYSCTL_DCGCGPIO_D4 0x00000010 // GPIO Port E Deep-Sleep Mode 2012 #define SYSCTL_DCGCGPIO_D3 0x00000008 // GPIO Port D Deep-Sleep Mode 2014 #define SYSCTL_DCGCGPIO_D2 0x00000004 // GPIO Port C Deep-Sleep Mode 2016 #define SYSCTL_DCGCGPIO_D1 0x00000002 // GPIO Port B Deep-Sleep Mode 2018 #define SYSCTL_DCGCGPIO_D0 0x00000001 // GPIO Port A Deep-Sleep Mode 2026 #define SYSCTL_DCGCDMA_D0 0x00000001 // uDMA Module Deep-Sleep Mode 2034 #define SYSCTL_DCGCEPI_D0 0x00000001 // EPI Module Deep-Sleep Mode Clock 2042 #define SYSCTL_DCGCHIB_D0 0x00000001 // Hibernation Module Deep-Sleep 2051 #define SYSCTL_DCGCUART_D7 0x00000080 // UART Module 7 Deep-Sleep Mode 2053 #define SYSCTL_DCGCUART_D6 0x00000040 // UART Module 6 Deep-Sleep Mode 2055 #define SYSCTL_DCGCUART_D5 0x00000020 // UART Module 5 Deep-Sleep Mode 2057 #define SYSCTL_DCGCUART_D4 0x00000010 // UART Module 4 Deep-Sleep Mode 2059 #define SYSCTL_DCGCUART_D3 0x00000008 // UART Module 3 Deep-Sleep Mode 2061 #define SYSCTL_DCGCUART_D2 0x00000004 // UART Module 2 Deep-Sleep Mode 2063 #define SYSCTL_DCGCUART_D1 0x00000002 // UART Module 1 Deep-Sleep Mode 2065 #define SYSCTL_DCGCUART_D0 0x00000001 // UART Module 0 Deep-Sleep Mode 2073 #define SYSCTL_DCGCSSI_D3 0x00000008 // SSI Module 3 Deep-Sleep Mode 2075 #define SYSCTL_DCGCSSI_D2 0x00000004 // SSI Module 2 Deep-Sleep Mode 2077 #define SYSCTL_DCGCSSI_D1 0x00000002 // SSI Module 1 Deep-Sleep Mode 2079 #define SYSCTL_DCGCSSI_D0 0x00000001 // SSI Module 0 Deep-Sleep Mode 2087 #define SYSCTL_DCGCI2C_D9 0x00000200 // I2C Module 9 Deep-Sleep Mode 2089 #define SYSCTL_DCGCI2C_D8 0x00000100 // I2C Module 8 Deep-Sleep Mode 2091 #define SYSCTL_DCGCI2C_D7 0x00000080 // I2C Module 7 Deep-Sleep Mode 2093 #define SYSCTL_DCGCI2C_D6 0x00000040 // I2C Module 6 Deep-Sleep Mode 2095 #define SYSCTL_DCGCI2C_D5 0x00000020 // I2C Module 5 Deep-Sleep Mode 2097 #define SYSCTL_DCGCI2C_D4 0x00000010 // I2C Module 4 Deep-Sleep Mode 2099 #define SYSCTL_DCGCI2C_D3 0x00000008 // I2C Module 3 Deep-Sleep Mode 2101 #define SYSCTL_DCGCI2C_D2 0x00000004 // I2C Module 2 Deep-Sleep Mode 2103 #define SYSCTL_DCGCI2C_D1 0x00000002 // I2C Module 1 Deep-Sleep Mode 2105 #define SYSCTL_DCGCI2C_D0 0x00000001 // I2C Module 0 Deep-Sleep Mode 2113 #define SYSCTL_DCGCUSB_D0 0x00000001 // USB Module Deep-Sleep Mode Clock 2122 #define SYSCTL_DCGCEPHY_D0 0x00000001 // PHY Module Deep-Sleep Mode Clock 2130 #define SYSCTL_DCGCCAN_D1 0x00000002 // CAN Module 1 Deep-Sleep Mode 2132 #define SYSCTL_DCGCCAN_D0 0x00000001 // CAN Module 0 Deep-Sleep Mode 2140 #define SYSCTL_DCGCADC_D1 0x00000002 // ADC Module 1 Deep-Sleep Mode 2142 #define SYSCTL_DCGCADC_D0 0x00000001 // ADC Module 0 Deep-Sleep Mode 2151 #define SYSCTL_DCGCACMP_D0 0x00000001 // Analog Comparator Module 0 2160 #define SYSCTL_DCGCPWM_D1 0x00000002 // PWM Module 1 Deep-Sleep Mode 2162 #define SYSCTL_DCGCPWM_D0 0x00000001 // PWM Module 0 Deep-Sleep Mode 2170 #define SYSCTL_DCGCQEI_D1 0x00000002 // QEI Module 1 Deep-Sleep Mode 2172 #define SYSCTL_DCGCQEI_D0 0x00000001 // QEI Module 0 Deep-Sleep Mode 2181 #define SYSCTL_DCGCEEPROM_D0 0x00000001 // EEPROM Module Deep-Sleep Mode 2189 #define SYSCTL_DCGCCCM_D0 0x00000001 // CRC and Cryptographic Modules 2198 #define SYSCTL_DCGCLCD_D0 0x00000001 // LCD Controller Module 0 2208 #define SYSCTL_DCGCOWIRE_D0 0x00000001 // 1-Wire Module 0 Deep-Sleep Mode 2217 #define SYSCTL_DCGCEMAC_D0 0x00000001 // Ethernet MAC Module 0 Deep-Sleep 2225 #define SYSCTL_PCWD_P1 0x00000002 // Watchdog Timer 1 Power Control 2226 #define SYSCTL_PCWD_P0 0x00000001 // Watchdog Timer 0 Power Control 2233 #define SYSCTL_PCTIMER_P7 0x00000080 // General-Purpose Timer 7 Power 2235 #define SYSCTL_PCTIMER_P6 0x00000040 // General-Purpose Timer 6 Power 2237 #define SYSCTL_PCTIMER_P5 0x00000020 // General-Purpose Timer 5 Power 2239 #define SYSCTL_PCTIMER_P4 0x00000010 // General-Purpose Timer 4 Power 2241 #define SYSCTL_PCTIMER_P3 0x00000008 // General-Purpose Timer 3 Power 2243 #define SYSCTL_PCTIMER_P2 0x00000004 // General-Purpose Timer 2 Power 2245 #define SYSCTL_PCTIMER_P1 0x00000002 // General-Purpose Timer 1 Power 2247 #define SYSCTL_PCTIMER_P0 0x00000001 // General-Purpose Timer 0 Power 2255 #define SYSCTL_PCGPIO_P17 0x00020000 // GPIO Port T Power Control 2256 #define SYSCTL_PCGPIO_P16 0x00010000 // GPIO Port S Power Control 2257 #define SYSCTL_PCGPIO_P15 0x00008000 // GPIO Port R Power Control 2258 #define SYSCTL_PCGPIO_P14 0x00004000 // GPIO Port Q Power Control 2259 #define SYSCTL_PCGPIO_P13 0x00002000 // GPIO Port P Power Control 2260 #define SYSCTL_PCGPIO_P12 0x00001000 // GPIO Port N Power Control 2261 #define SYSCTL_PCGPIO_P11 0x00000800 // GPIO Port M Power Control 2262 #define SYSCTL_PCGPIO_P10 0x00000400 // GPIO Port L Power Control 2263 #define SYSCTL_PCGPIO_P9 0x00000200 // GPIO Port K Power Control 2264 #define SYSCTL_PCGPIO_P8 0x00000100 // GPIO Port J Power Control 2265 #define SYSCTL_PCGPIO_P7 0x00000080 // GPIO Port H Power Control 2266 #define SYSCTL_PCGPIO_P6 0x00000040 // GPIO Port G Power Control 2267 #define SYSCTL_PCGPIO_P5 0x00000020 // GPIO Port F Power Control 2268 #define SYSCTL_PCGPIO_P4 0x00000010 // GPIO Port E Power Control 2269 #define SYSCTL_PCGPIO_P3 0x00000008 // GPIO Port D Power Control 2270 #define SYSCTL_PCGPIO_P2 0x00000004 // GPIO Port C Power Control 2271 #define SYSCTL_PCGPIO_P1 0x00000002 // GPIO Port B Power Control 2272 #define SYSCTL_PCGPIO_P0 0x00000001 // GPIO Port A Power Control 2279 #define SYSCTL_PCDMA_P0 0x00000001 // uDMA Module Power Control 2286 #define SYSCTL_PCEPI_P0 0x00000001 // EPI Module Power Control 2293 #define SYSCTL_PCHIB_P0 0x00000001 // Hibernation Module Power Control 2300 #define SYSCTL_PCUART_P7 0x00000080 // UART Module 7 Power Control 2301 #define SYSCTL_PCUART_P6 0x00000040 // UART Module 6 Power Control 2302 #define SYSCTL_PCUART_P5 0x00000020 // UART Module 5 Power Control 2303 #define SYSCTL_PCUART_P4 0x00000010 // UART Module 4 Power Control 2304 #define SYSCTL_PCUART_P3 0x00000008 // UART Module 3 Power Control 2305 #define SYSCTL_PCUART_P2 0x00000004 // UART Module 2 Power Control 2306 #define SYSCTL_PCUART_P1 0x00000002 // UART Module 1 Power Control 2307 #define SYSCTL_PCUART_P0 0x00000001 // UART Module 0 Power Control 2314 #define SYSCTL_PCSSI_P3 0x00000008 // SSI Module 3 Power Control 2315 #define SYSCTL_PCSSI_P2 0x00000004 // SSI Module 2 Power Control 2316 #define SYSCTL_PCSSI_P1 0x00000002 // SSI Module 1 Power Control 2317 #define SYSCTL_PCSSI_P0 0x00000001 // SSI Module 0 Power Control 2324 #define SYSCTL_PCI2C_P9 0x00000200 // I2C Module 9 Power Control 2325 #define SYSCTL_PCI2C_P8 0x00000100 // I2C Module 8 Power Control 2326 #define SYSCTL_PCI2C_P7 0x00000080 // I2C Module 7 Power Control 2327 #define SYSCTL_PCI2C_P6 0x00000040 // I2C Module 6 Power Control 2328 #define SYSCTL_PCI2C_P5 0x00000020 // I2C Module 5 Power Control 2329 #define SYSCTL_PCI2C_P4 0x00000010 // I2C Module 4 Power Control 2330 #define SYSCTL_PCI2C_P3 0x00000008 // I2C Module 3 Power Control 2331 #define SYSCTL_PCI2C_P2 0x00000004 // I2C Module 2 Power Control 2332 #define SYSCTL_PCI2C_P1 0x00000002 // I2C Module 1 Power Control 2333 #define SYSCTL_PCI2C_P0 0x00000001 // I2C Module 0 Power Control 2340 #define SYSCTL_PCUSB_P0 0x00000001 // USB Module Power Control 2347 #define SYSCTL_PCEPHY_P0 0x00000001 // Ethernet PHY Module Power 2355 #define SYSCTL_PCCAN_P1 0x00000002 // CAN Module 1 Power Control 2356 #define SYSCTL_PCCAN_P0 0x00000001 // CAN Module 0 Power Control 2363 #define SYSCTL_PCADC_P1 0x00000002 // ADC Module 1 Power Control 2364 #define SYSCTL_PCADC_P0 0x00000001 // ADC Module 0 Power Control 2371 #define SYSCTL_PCACMP_P0 0x00000001 // Analog Comparator Module 0 Power 2379 #define SYSCTL_PCPWM_P0 0x00000001 // PWM Module 0 Power Control 2386 #define SYSCTL_PCQEI_P0 0x00000001 // QEI Module 0 Power Control 2394 #define SYSCTL_PCEEPROM_P0 0x00000001 // EEPROM Module 0 Power Control 2401 #define SYSCTL_PCCCM_P0 0x00000001 // CRC and Cryptographic Modules 2409 #define SYSCTL_PCLCD_P0 0x00000001 // LCD Controller Module 0 Power 2417 #define SYSCTL_PCOWIRE_P0 0x00000001 // 1-Wire Module 0 Power Control 2424 #define SYSCTL_PCEMAC_P0 0x00000001 // Ethernet MAC Module 0 Power 2432 #define SYSCTL_PRWD_R1 0x00000002 // Watchdog Timer 1 Peripheral 2434 #define SYSCTL_PRWD_R0 0x00000001 // Watchdog Timer 0 Peripheral 2442 #define SYSCTL_PRTIMER_R7 0x00000080 // 16/32-Bit General-Purpose Timer 2444 #define SYSCTL_PRTIMER_R6 0x00000040 // 16/32-Bit General-Purpose Timer 2446 #define SYSCTL_PRTIMER_R5 0x00000020 // 16/32-Bit General-Purpose Timer 2448 #define SYSCTL_PRTIMER_R4 0x00000010 // 16/32-Bit General-Purpose Timer 2450 #define SYSCTL_PRTIMER_R3 0x00000008 // 16/32-Bit General-Purpose Timer 2452 #define SYSCTL_PRTIMER_R2 0x00000004 // 16/32-Bit General-Purpose Timer 2454 #define SYSCTL_PRTIMER_R1 0x00000002 // 16/32-Bit General-Purpose Timer 2456 #define SYSCTL_PRTIMER_R0 0x00000001 // 16/32-Bit General-Purpose Timer 2464 #define SYSCTL_PRGPIO_R17 0x00020000 // GPIO Port T Peripheral Ready 2465 #define SYSCTL_PRGPIO_R16 0x00010000 // GPIO Port S Peripheral Ready 2466 #define SYSCTL_PRGPIO_R15 0x00008000 // GPIO Port R Peripheral Ready 2467 #define SYSCTL_PRGPIO_R14 0x00004000 // GPIO Port Q Peripheral Ready 2468 #define SYSCTL_PRGPIO_R13 0x00002000 // GPIO Port P Peripheral Ready 2469 #define SYSCTL_PRGPIO_R12 0x00001000 // GPIO Port N Peripheral Ready 2470 #define SYSCTL_PRGPIO_R11 0x00000800 // GPIO Port M Peripheral Ready 2471 #define SYSCTL_PRGPIO_R10 0x00000400 // GPIO Port L Peripheral Ready 2472 #define SYSCTL_PRGPIO_R9 0x00000200 // GPIO Port K Peripheral Ready 2473 #define SYSCTL_PRGPIO_R8 0x00000100 // GPIO Port J Peripheral Ready 2474 #define SYSCTL_PRGPIO_R7 0x00000080 // GPIO Port H Peripheral Ready 2475 #define SYSCTL_PRGPIO_R6 0x00000040 // GPIO Port G Peripheral Ready 2476 #define SYSCTL_PRGPIO_R5 0x00000020 // GPIO Port F Peripheral Ready 2477 #define SYSCTL_PRGPIO_R4 0x00000010 // GPIO Port E Peripheral Ready 2478 #define SYSCTL_PRGPIO_R3 0x00000008 // GPIO Port D Peripheral Ready 2479 #define SYSCTL_PRGPIO_R2 0x00000004 // GPIO Port C Peripheral Ready 2480 #define SYSCTL_PRGPIO_R1 0x00000002 // GPIO Port B Peripheral Ready 2481 #define SYSCTL_PRGPIO_R0 0x00000001 // GPIO Port A Peripheral Ready 2488 #define SYSCTL_PRDMA_R0 0x00000001 // uDMA Module Peripheral Ready 2495 #define SYSCTL_PREPI_R0 0x00000001 // EPI Module Peripheral Ready 2502 #define SYSCTL_PRHIB_R0 0x00000001 // Hibernation Module Peripheral 2510 #define SYSCTL_PRUART_R7 0x00000080 // UART Module 7 Peripheral Ready 2511 #define SYSCTL_PRUART_R6 0x00000040 // UART Module 6 Peripheral Ready 2512 #define SYSCTL_PRUART_R5 0x00000020 // UART Module 5 Peripheral Ready 2513 #define SYSCTL_PRUART_R4 0x00000010 // UART Module 4 Peripheral Ready 2514 #define SYSCTL_PRUART_R3 0x00000008 // UART Module 3 Peripheral Ready 2515 #define SYSCTL_PRUART_R2 0x00000004 // UART Module 2 Peripheral Ready 2516 #define SYSCTL_PRUART_R1 0x00000002 // UART Module 1 Peripheral Ready 2517 #define SYSCTL_PRUART_R0 0x00000001 // UART Module 0 Peripheral Ready 2524 #define SYSCTL_PRSSI_R3 0x00000008 // SSI Module 3 Peripheral Ready 2525 #define SYSCTL_PRSSI_R2 0x00000004 // SSI Module 2 Peripheral Ready 2526 #define SYSCTL_PRSSI_R1 0x00000002 // SSI Module 1 Peripheral Ready 2527 #define SYSCTL_PRSSI_R0 0x00000001 // SSI Module 0 Peripheral Ready 2534 #define SYSCTL_PRI2C_R9 0x00000200 // I2C Module 9 Peripheral Ready 2535 #define SYSCTL_PRI2C_R8 0x00000100 // I2C Module 8 Peripheral Ready 2536 #define SYSCTL_PRI2C_R7 0x00000080 // I2C Module 7 Peripheral Ready 2537 #define SYSCTL_PRI2C_R6 0x00000040 // I2C Module 6 Peripheral Ready 2538 #define SYSCTL_PRI2C_R5 0x00000020 // I2C Module 5 Peripheral Ready 2539 #define SYSCTL_PRI2C_R4 0x00000010 // I2C Module 4 Peripheral Ready 2540 #define SYSCTL_PRI2C_R3 0x00000008 // I2C Module 3 Peripheral Ready 2541 #define SYSCTL_PRI2C_R2 0x00000004 // I2C Module 2 Peripheral Ready 2542 #define SYSCTL_PRI2C_R1 0x00000002 // I2C Module 1 Peripheral Ready 2543 #define SYSCTL_PRI2C_R0 0x00000001 // I2C Module 0 Peripheral Ready 2550 #define SYSCTL_PRUSB_R0 0x00000001 // USB Module Peripheral Ready 2557 #define SYSCTL_PREPHY_R0 0x00000001 // Ethernet PHY Module Peripheral 2565 #define SYSCTL_PRCAN_R1 0x00000002 // CAN Module 1 Peripheral Ready 2566 #define SYSCTL_PRCAN_R0 0x00000001 // CAN Module 0 Peripheral Ready 2573 #define SYSCTL_PRADC_R1 0x00000002 // ADC Module 1 Peripheral Ready 2574 #define SYSCTL_PRADC_R0 0x00000001 // ADC Module 0 Peripheral Ready 2581 #define SYSCTL_PRACMP_R0 0x00000001 // Analog Comparator Module 0 2589 #define SYSCTL_PRPWM_R1 0x00000002 // PWM Module 1 Peripheral Ready 2590 #define SYSCTL_PRPWM_R0 0x00000001 // PWM Module 0 Peripheral Ready 2597 #define SYSCTL_PRQEI_R1 0x00000002 // QEI Module 1 Peripheral Ready 2598 #define SYSCTL_PRQEI_R0 0x00000001 // QEI Module 0 Peripheral Ready 2606 #define SYSCTL_PREEPROM_R0 0x00000001 // EEPROM Module Peripheral Ready 2613 #define SYSCTL_PRCCM_R0 0x00000001 // CRC and Cryptographic Modules 2621 #define SYSCTL_PRLCD_R0 0x00000001 // LCD Controller Module 0 2629 #define SYSCTL_PROWIRE_R0 0x00000001 // 1-Wire Module 0 Peripheral Ready 2636 #define SYSCTL_PREMAC_R0 0x00000001 // Ethernet MAC Module 0 Peripheral 2645 #define SYSCTL_UNIQUEID0_ID_M 0xFFFFFFFF // Unique ID 2646 #define SYSCTL_UNIQUEID0_ID_S 0 2654 #define SYSCTL_UNIQUEID1_ID_M 0xFFFFFFFF // Unique ID 2655 #define SYSCTL_UNIQUEID1_ID_S 0 2663 #define SYSCTL_UNIQUEID2_ID_M 0xFFFFFFFF // Unique ID 2664 #define SYSCTL_UNIQUEID2_ID_S 0 2672 #define SYSCTL_UNIQUEID3_ID_M 0xFFFFFFFF // Unique ID 2673 #define SYSCTL_UNIQUEID3_ID_S 0 2685 #endif // __HW_SYSCTL_H__
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