hw_sysctl.h
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1 //*****************************************************************************
2 //
3 // hw_sysctl.h - Macros used when accessing the system control hardware.
4 //
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37 
38 #ifndef __HW_SYSCTL_H__
39 #define __HW_SYSCTL_H__
40 
41 //*****************************************************************************
42 //
43 // The following are defines for the System Control register addresses.
44 //
45 //*****************************************************************************
46 #define SYSCTL_DID0 0x400FE000 // Device Identification 0
47 #define SYSCTL_DID1 0x400FE004 // Device Identification 1
48 #define SYSCTL_PTBOCTL 0x400FE038 // Power-Temp Brown Out Control
49 #define SYSCTL_RIS 0x400FE050 // Raw Interrupt Status
50 #define SYSCTL_IMC 0x400FE054 // Interrupt Mask Control
51 #define SYSCTL_MISC 0x400FE058 // Masked Interrupt Status and
52  // Clear
53 #define SYSCTL_RESC 0x400FE05C // Reset Cause
54 #define SYSCTL_PWRTC 0x400FE060 // Power-Temperature Cause
55 #define SYSCTL_NMIC 0x400FE064 // NMI Cause Register
56 #define SYSCTL_MOSCCTL 0x400FE07C // Main Oscillator Control
57 #define SYSCTL_RSCLKCFG 0x400FE0B0 // Run and Sleep Mode Configuration
58  // Register
59 #define SYSCTL_MEMTIM0 0x400FE0C0 // Memory Timing Parameter Register
60  // 0 for Main Flash and EEPROM
61 #define SYSCTL_ALTCLKCFG 0x400FE138 // Alternate Clock Configuration
62 #define SYSCTL_DSLPCLKCFG 0x400FE144 // Deep Sleep Clock Configuration
63 #define SYSCTL_DSCLKCFG 0x400FE144 // Deep Sleep Clock Configuration
64  // Register
65 #define SYSCTL_DIVSCLK 0x400FE148 // Divisor and Source Clock
66  // Configuration
67 #define SYSCTL_SYSPROP 0x400FE14C // System Properties
68 #define SYSCTL_PIOSCCAL 0x400FE150 // Precision Internal Oscillator
69  // Calibration
70 #define SYSCTL_PIOSCSTAT 0x400FE154 // Precision Internal Oscillator
71  // Statistics
72 #define SYSCTL_PLLFREQ0 0x400FE160 // PLL Frequency 0
73 #define SYSCTL_PLLFREQ1 0x400FE164 // PLL Frequency 1
74 #define SYSCTL_PLLSTAT 0x400FE168 // PLL Status
75 #define SYSCTL_SLPPWRCFG 0x400FE188 // Sleep Power Configuration
76 #define SYSCTL_DSLPPWRCFG 0x400FE18C // Deep-Sleep Power Configuration
77 #define SYSCTL_DC9 0x400FE190 // Device Capabilities 9
78 #define SYSCTL_NVMSTAT 0x400FE1A0 // Non-Volatile Memory Information
79 #define SYSCTL_LDOSPCTL 0x400FE1B4 // LDO Sleep Power Control
80 #define SYSCTL_LDODPCTL 0x400FE1BC // LDO Deep-Sleep Power Control
81 #define SYSCTL_RESBEHAVCTL 0x400FE1D8 // Reset Behavior Control Register
82 #define SYSCTL_HSSR 0x400FE1F4 // Hardware System Service Request
83 #define SYSCTL_USBPDS 0x400FE280 // USB Power Domain Status
84 #define SYSCTL_USBMPC 0x400FE284 // USB Memory Power Control
85 #define SYSCTL_EMACPDS 0x400FE288 // Ethernet MAC Power Domain Status
86 #define SYSCTL_EMACMPC 0x400FE28C // Ethernet MAC Memory Power
87  // Control
88 #define SYSCTL_LCDMPC 0x400FE294 // LCD Memory Power Control
89 #define SYSCTL_PPWD 0x400FE300 // Watchdog Timer Peripheral
90  // Present
91 #define SYSCTL_PPTIMER 0x400FE304 // 16/32-Bit General-Purpose Timer
92  // Peripheral Present
93 #define SYSCTL_PPGPIO 0x400FE308 // General-Purpose Input/Output
94  // Peripheral Present
95 #define SYSCTL_PPDMA 0x400FE30C // Micro Direct Memory Access
96  // Peripheral Present
97 #define SYSCTL_PPEPI 0x400FE310 // EPI Peripheral Present
98 #define SYSCTL_PPHIB 0x400FE314 // Hibernation Peripheral Present
99 #define SYSCTL_PPUART 0x400FE318 // Universal Asynchronous
100  // Receiver/Transmitter Peripheral
101  // Present
102 #define SYSCTL_PPSSI 0x400FE31C // Synchronous Serial Interface
103  // Peripheral Present
104 #define SYSCTL_PPI2C 0x400FE320 // Inter-Integrated Circuit
105  // Peripheral Present
106 #define SYSCTL_PPUSB 0x400FE328 // Universal Serial Bus Peripheral
107  // Present
108 #define SYSCTL_PPEPHY 0x400FE330 // Ethernet PHY Peripheral Present
109 #define SYSCTL_PPCAN 0x400FE334 // Controller Area Network
110  // Peripheral Present
111 #define SYSCTL_PPADC 0x400FE338 // Analog-to-Digital Converter
112  // Peripheral Present
113 #define SYSCTL_PPACMP 0x400FE33C // Analog Comparator Peripheral
114  // Present
115 #define SYSCTL_PPPWM 0x400FE340 // Pulse Width Modulator Peripheral
116  // Present
117 #define SYSCTL_PPQEI 0x400FE344 // Quadrature Encoder Interface
118  // Peripheral Present
119 #define SYSCTL_PPEEPROM 0x400FE358 // EEPROM Peripheral Present
120 #define SYSCTL_PPCCM 0x400FE374 // CRC and Cryptographic Modules
121  // Peripheral Present
122 #define SYSCTL_PPLCD 0x400FE390 // LCD Peripheral Present
123 #define SYSCTL_PPOWIRE 0x400FE398 // 1-Wire Peripheral Present
124 #define SYSCTL_PPEMAC 0x400FE39C // Ethernet MAC Peripheral Present
125 #define SYSCTL_SRWD 0x400FE500 // Watchdog Timer Software Reset
126 #define SYSCTL_SRTIMER 0x400FE504 // 16/32-Bit General-Purpose Timer
127  // Software Reset
128 #define SYSCTL_SRGPIO 0x400FE508 // General-Purpose Input/Output
129  // Software Reset
130 #define SYSCTL_SRDMA 0x400FE50C // Micro Direct Memory Access
131  // Software Reset
132 #define SYSCTL_SREPI 0x400FE510 // EPI Software Reset
133 #define SYSCTL_SRHIB 0x400FE514 // Hibernation Software Reset
134 #define SYSCTL_SRUART 0x400FE518 // Universal Asynchronous
135  // Receiver/Transmitter Software
136  // Reset
137 #define SYSCTL_SRSSI 0x400FE51C // Synchronous Serial Interface
138  // Software Reset
139 #define SYSCTL_SRI2C 0x400FE520 // Inter-Integrated Circuit
140  // Software Reset
141 #define SYSCTL_SRUSB 0x400FE528 // Universal Serial Bus Software
142  // Reset
143 #define SYSCTL_SREPHY 0x400FE530 // Ethernet PHY Software Reset
144 #define SYSCTL_SRCAN 0x400FE534 // Controller Area Network Software
145  // Reset
146 #define SYSCTL_SRADC 0x400FE538 // Analog-to-Digital Converter
147  // Software Reset
148 #define SYSCTL_SRACMP 0x400FE53C // Analog Comparator Software Reset
149 #define SYSCTL_SRPWM 0x400FE540 // Pulse Width Modulator Software
150  // Reset
151 #define SYSCTL_SRQEI 0x400FE544 // Quadrature Encoder Interface
152  // Software Reset
153 #define SYSCTL_SREEPROM 0x400FE558 // EEPROM Software Reset
154 #define SYSCTL_SRCCM 0x400FE574 // CRC and Cryptographic Modules
155  // Software Reset
156 #define SYSCTL_SRLCD 0x400FE590 // LCD Controller Software Reset
157 #define SYSCTL_SROWIRE 0x400FE598 // 1-Wire Software Reset
158 #define SYSCTL_SREMAC 0x400FE59C // Ethernet MAC Software Reset
159 #define SYSCTL_RCGCWD 0x400FE600 // Watchdog Timer Run Mode Clock
160  // Gating Control
161 #define SYSCTL_RCGCTIMER 0x400FE604 // 16/32-Bit General-Purpose Timer
162  // Run Mode Clock Gating Control
163 #define SYSCTL_RCGCGPIO 0x400FE608 // General-Purpose Input/Output Run
164  // Mode Clock Gating Control
165 #define SYSCTL_RCGCDMA 0x400FE60C // Micro Direct Memory Access Run
166  // Mode Clock Gating Control
167 #define SYSCTL_RCGCEPI 0x400FE610 // EPI Run Mode Clock Gating
168  // Control
169 #define SYSCTL_RCGCHIB 0x400FE614 // Hibernation Run Mode Clock
170  // Gating Control
171 #define SYSCTL_RCGCUART 0x400FE618 // Universal Asynchronous
172  // Receiver/Transmitter Run Mode
173  // Clock Gating Control
174 #define SYSCTL_RCGCSSI 0x400FE61C // Synchronous Serial Interface Run
175  // Mode Clock Gating Control
176 #define SYSCTL_RCGCI2C 0x400FE620 // Inter-Integrated Circuit Run
177  // Mode Clock Gating Control
178 #define SYSCTL_RCGCUSB 0x400FE628 // Universal Serial Bus Run Mode
179  // Clock Gating Control
180 #define SYSCTL_RCGCEPHY 0x400FE630 // Ethernet PHY Run Mode Clock
181  // Gating Control
182 #define SYSCTL_RCGCCAN 0x400FE634 // Controller Area Network Run Mode
183  // Clock Gating Control
184 #define SYSCTL_RCGCADC 0x400FE638 // Analog-to-Digital Converter Run
185  // Mode Clock Gating Control
186 #define SYSCTL_RCGCACMP 0x400FE63C // Analog Comparator Run Mode Clock
187  // Gating Control
188 #define SYSCTL_RCGCPWM 0x400FE640 // Pulse Width Modulator Run Mode
189  // Clock Gating Control
190 #define SYSCTL_RCGCQEI 0x400FE644 // Quadrature Encoder Interface Run
191  // Mode Clock Gating Control
192 #define SYSCTL_RCGCEEPROM 0x400FE658 // EEPROM Run Mode Clock Gating
193  // Control
194 #define SYSCTL_RCGCCCM 0x400FE674 // CRC and Cryptographic Modules
195  // Run Mode Clock Gating Control
196 #define SYSCTL_RCGCLCD 0x400FE690 // LCD Controller Run Mode Clock
197  // Gating Control
198 #define SYSCTL_RCGCOWIRE 0x400FE698 // 1-Wire Run Mode Clock Gating
199  // Control
200 #define SYSCTL_RCGCEMAC 0x400FE69C // Ethernet MAC Run Mode Clock
201  // Gating Control
202 #define SYSCTL_SCGCWD 0x400FE700 // Watchdog Timer Sleep Mode Clock
203  // Gating Control
204 #define SYSCTL_SCGCTIMER 0x400FE704 // 16/32-Bit General-Purpose Timer
205  // Sleep Mode Clock Gating Control
206 #define SYSCTL_SCGCGPIO 0x400FE708 // General-Purpose Input/Output
207  // Sleep Mode Clock Gating Control
208 #define SYSCTL_SCGCDMA 0x400FE70C // Micro Direct Memory Access Sleep
209  // Mode Clock Gating Control
210 #define SYSCTL_SCGCEPI 0x400FE710 // EPI Sleep Mode Clock Gating
211  // Control
212 #define SYSCTL_SCGCHIB 0x400FE714 // Hibernation Sleep Mode Clock
213  // Gating Control
214 #define SYSCTL_SCGCUART 0x400FE718 // Universal Asynchronous
215  // Receiver/Transmitter Sleep Mode
216  // Clock Gating Control
217 #define SYSCTL_SCGCSSI 0x400FE71C // Synchronous Serial Interface
218  // Sleep Mode Clock Gating Control
219 #define SYSCTL_SCGCI2C 0x400FE720 // Inter-Integrated Circuit Sleep
220  // Mode Clock Gating Control
221 #define SYSCTL_SCGCUSB 0x400FE728 // Universal Serial Bus Sleep Mode
222  // Clock Gating Control
223 #define SYSCTL_SCGCEPHY 0x400FE730 // Ethernet PHY Sleep Mode Clock
224  // Gating Control
225 #define SYSCTL_SCGCCAN 0x400FE734 // Controller Area Network Sleep
226  // Mode Clock Gating Control
227 #define SYSCTL_SCGCADC 0x400FE738 // Analog-to-Digital Converter
228  // Sleep Mode Clock Gating Control
229 #define SYSCTL_SCGCACMP 0x400FE73C // Analog Comparator Sleep Mode
230  // Clock Gating Control
231 #define SYSCTL_SCGCPWM 0x400FE740 // Pulse Width Modulator Sleep Mode
232  // Clock Gating Control
233 #define SYSCTL_SCGCQEI 0x400FE744 // Quadrature Encoder Interface
234  // Sleep Mode Clock Gating Control
235 #define SYSCTL_SCGCEEPROM 0x400FE758 // EEPROM Sleep Mode Clock Gating
236  // Control
237 #define SYSCTL_SCGCCCM 0x400FE774 // CRC and Cryptographic Modules
238  // Sleep Mode Clock Gating Control
239 #define SYSCTL_SCGCLCD 0x400FE790 // LCD Controller Sleep Mode Clock
240  // Gating Control
241 #define SYSCTL_SCGCOWIRE 0x400FE798 // 1-Wire Sleep Mode Clock Gating
242  // Control
243 #define SYSCTL_SCGCEMAC 0x400FE79C // Ethernet MAC Sleep Mode Clock
244  // Gating Control
245 #define SYSCTL_DCGCWD 0x400FE800 // Watchdog Timer Deep-Sleep Mode
246  // Clock Gating Control
247 #define SYSCTL_DCGCTIMER 0x400FE804 // 16/32-Bit General-Purpose Timer
248  // Deep-Sleep Mode Clock Gating
249  // Control
250 #define SYSCTL_DCGCGPIO 0x400FE808 // General-Purpose Input/Output
251  // Deep-Sleep Mode Clock Gating
252  // Control
253 #define SYSCTL_DCGCDMA 0x400FE80C // Micro Direct Memory Access
254  // Deep-Sleep Mode Clock Gating
255  // Control
256 #define SYSCTL_DCGCEPI 0x400FE810 // EPI Deep-Sleep Mode Clock Gating
257  // Control
258 #define SYSCTL_DCGCHIB 0x400FE814 // Hibernation Deep-Sleep Mode
259  // Clock Gating Control
260 #define SYSCTL_DCGCUART 0x400FE818 // Universal Asynchronous
261  // Receiver/Transmitter Deep-Sleep
262  // Mode Clock Gating Control
263 #define SYSCTL_DCGCSSI 0x400FE81C // Synchronous Serial Interface
264  // Deep-Sleep Mode Clock Gating
265  // Control
266 #define SYSCTL_DCGCI2C 0x400FE820 // Inter-Integrated Circuit
267  // Deep-Sleep Mode Clock Gating
268  // Control
269 #define SYSCTL_DCGCUSB 0x400FE828 // Universal Serial Bus Deep-Sleep
270  // Mode Clock Gating Control
271 #define SYSCTL_DCGCEPHY 0x400FE830 // Ethernet PHY Deep-Sleep Mode
272  // Clock Gating Control
273 #define SYSCTL_DCGCCAN 0x400FE834 // Controller Area Network
274  // Deep-Sleep Mode Clock Gating
275  // Control
276 #define SYSCTL_DCGCADC 0x400FE838 // Analog-to-Digital Converter
277  // Deep-Sleep Mode Clock Gating
278  // Control
279 #define SYSCTL_DCGCACMP 0x400FE83C // Analog Comparator Deep-Sleep
280  // Mode Clock Gating Control
281 #define SYSCTL_DCGCPWM 0x400FE840 // Pulse Width Modulator Deep-Sleep
282  // Mode Clock Gating Control
283 #define SYSCTL_DCGCQEI 0x400FE844 // Quadrature Encoder Interface
284  // Deep-Sleep Mode Clock Gating
285  // Control
286 #define SYSCTL_DCGCEEPROM 0x400FE858 // EEPROM Deep-Sleep Mode Clock
287  // Gating Control
288 #define SYSCTL_DCGCCCM 0x400FE874 // CRC and Cryptographic Modules
289  // Deep-Sleep Mode Clock Gating
290  // Control
291 #define SYSCTL_DCGCLCD 0x400FE890 // LCD Controller Deep-Sleep Mode
292  // Clock Gating Control
293 #define SYSCTL_DCGCOWIRE 0x400FE898 // 1-Wire Deep-Sleep Mode Clock
294  // Gating Control
295 #define SYSCTL_DCGCEMAC 0x400FE89C // Ethernet MAC Deep-Sleep Mode
296  // Clock Gating Control
297 #define SYSCTL_PCWD 0x400FE900 // Watchdog Timer Power Control
298 #define SYSCTL_PCTIMER 0x400FE904 // 16/32-Bit General-Purpose Timer
299  // Power Control
300 #define SYSCTL_PCGPIO 0x400FE908 // General-Purpose Input/Output
301  // Power Control
302 #define SYSCTL_PCDMA 0x400FE90C // Micro Direct Memory Access Power
303  // Control
304 #define SYSCTL_PCEPI 0x400FE910 // External Peripheral Interface
305  // Power Control
306 #define SYSCTL_PCHIB 0x400FE914 // Hibernation Power Control
307 #define SYSCTL_PCUART 0x400FE918 // Universal Asynchronous
308  // Receiver/Transmitter Power
309  // Control
310 #define SYSCTL_PCSSI 0x400FE91C // Synchronous Serial Interface
311  // Power Control
312 #define SYSCTL_PCI2C 0x400FE920 // Inter-Integrated Circuit Power
313  // Control
314 #define SYSCTL_PCUSB 0x400FE928 // Universal Serial Bus Power
315  // Control
316 #define SYSCTL_PCEPHY 0x400FE930 // Ethernet PHY Power Control
317 #define SYSCTL_PCCAN 0x400FE934 // Controller Area Network Power
318  // Control
319 #define SYSCTL_PCADC 0x400FE938 // Analog-to-Digital Converter
320  // Power Control
321 #define SYSCTL_PCACMP 0x400FE93C // Analog Comparator Power Control
322 #define SYSCTL_PCPWM 0x400FE940 // Pulse Width Modulator Power
323  // Control
324 #define SYSCTL_PCQEI 0x400FE944 // Quadrature Encoder Interface
325  // Power Control
326 #define SYSCTL_PCEEPROM 0x400FE958 // EEPROM Power Control
327 #define SYSCTL_PCCCM 0x400FE974 // CRC and Cryptographic Modules
328  // Power Control
329 #define SYSCTL_PCLCD 0x400FE990 // LCD Controller Power Control
330 #define SYSCTL_PCOWIRE 0x400FE998 // 1-Wire Power Control
331 #define SYSCTL_PCEMAC 0x400FE99C // Ethernet MAC Power Control
332 #define SYSCTL_PRWD 0x400FEA00 // Watchdog Timer Peripheral Ready
333 #define SYSCTL_PRTIMER 0x400FEA04 // 16/32-Bit General-Purpose Timer
334  // Peripheral Ready
335 #define SYSCTL_PRGPIO 0x400FEA08 // General-Purpose Input/Output
336  // Peripheral Ready
337 #define SYSCTL_PRDMA 0x400FEA0C // Micro Direct Memory Access
338  // Peripheral Ready
339 #define SYSCTL_PREPI 0x400FEA10 // EPI Peripheral Ready
340 #define SYSCTL_PRHIB 0x400FEA14 // Hibernation Peripheral Ready
341 #define SYSCTL_PRUART 0x400FEA18 // Universal Asynchronous
342  // Receiver/Transmitter Peripheral
343  // Ready
344 #define SYSCTL_PRSSI 0x400FEA1C // Synchronous Serial Interface
345  // Peripheral Ready
346 #define SYSCTL_PRI2C 0x400FEA20 // Inter-Integrated Circuit
347  // Peripheral Ready
348 #define SYSCTL_PRUSB 0x400FEA28 // Universal Serial Bus Peripheral
349  // Ready
350 #define SYSCTL_PREPHY 0x400FEA30 // Ethernet PHY Peripheral Ready
351 #define SYSCTL_PRCAN 0x400FEA34 // Controller Area Network
352  // Peripheral Ready
353 #define SYSCTL_PRADC 0x400FEA38 // Analog-to-Digital Converter
354  // Peripheral Ready
355 #define SYSCTL_PRACMP 0x400FEA3C // Analog Comparator Peripheral
356  // Ready
357 #define SYSCTL_PRPWM 0x400FEA40 // Pulse Width Modulator Peripheral
358  // Ready
359 #define SYSCTL_PRQEI 0x400FEA44 // Quadrature Encoder Interface
360  // Peripheral Ready
361 #define SYSCTL_PREEPROM 0x400FEA58 // EEPROM Peripheral Ready
362 #define SYSCTL_PRCCM 0x400FEA74 // CRC and Cryptographic Modules
363  // Peripheral Ready
364 #define SYSCTL_PRLCD 0x400FEA90 // LCD Controller Peripheral Ready
365 #define SYSCTL_PROWIRE 0x400FEA98 // 1-Wire Peripheral Ready
366 #define SYSCTL_PREMAC 0x400FEA9C // Ethernet MAC Peripheral Ready
367 #define SYSCTL_UNIQUEID0 0x400FEF20 // Unique ID 0
368 #define SYSCTL_UNIQUEID1 0x400FEF24 // Unique ID 1
369 #define SYSCTL_UNIQUEID2 0x400FEF28 // Unique ID 2
370 #define SYSCTL_UNIQUEID3 0x400FEF2C // Unique ID 3
371 // #define SYSCTL_CCMCGREQ 0x44030204 // Cryptographic Modules Clock
372 // // Gating Request
373 
374 //*****************************************************************************
375 //
376 // The following are defines for the bit fields in the SYSCTL_DID0 register.
377 //
378 //*****************************************************************************
379 #define SYSCTL_DID0_VER_M 0x70000000 // DID0 Version
380 #define SYSCTL_DID0_VER_1 0x10000000 // Second version of the DID0
381  // register format.
382 #define SYSCTL_DID0_CLASS_M 0x00FF0000 // Device Class
383 #define SYSCTL_DID0_CLASS_MSP432E4 \
384  0x000C0000 // MSP432E4 microcontrollers
385 #define SYSCTL_DID0_MAJ_M 0x0000FF00 // Major Revision
386 #define SYSCTL_DID0_MAJ_REVA 0x00000000 // Revision A (initial device)
387 #define SYSCTL_DID0_MAJ_REVB 0x00000100 // Revision B (first base layer
388  // revision)
389 #define SYSCTL_DID0_MAJ_REVC 0x00000200 // Revision C (second base layer
390  // revision)
391 #define SYSCTL_DID0_MIN_M 0x000000FF // Minor Revision
392 #define SYSCTL_DID0_MIN_0 0x00000000 // Initial device, or a major
393  // revision update
394 #define SYSCTL_DID0_MIN_1 0x00000001 // First metal layer change
395 #define SYSCTL_DID0_MIN_2 0x00000002 // Second metal layer change
396 
397 //*****************************************************************************
398 //
399 // The following are defines for the bit fields in the SYSCTL_DID1 register.
400 //
401 //*****************************************************************************
402 #define SYSCTL_DID1_VER_M 0xF0000000 // DID1 Version
403 #define SYSCTL_DID1_FAM_M 0x0F000000 // Family
404 #define SYSCTL_DID1_FAM_MSP432E4 \
405  0x00000000 // MSP432E4 family of
406  // microcontollers
407 #define SYSCTL_DID1_PRTNO_M 0x00FF0000 // Part Number
408 #define SYSCTL_DID1_PRTNO_MSP432E401Y \
409  0x002D0000 // MSP432E401Y
410 #define SYSCTL_DID1_PRTNO_MSP432E411Y \
411  0x00320000 // MSP432E411Y
412 #define SYSCTL_DID1_PINCNT_M 0x0000E000 // Package Pin Count
413 #define SYSCTL_DID1_PINCNT_128 0x0000C000 // 128-pin TQFP package
414 #define SYSCTL_DID1_PINCNT_212 0x0000E000 // 212-pin BGA package
415 #define SYSCTL_DID1_TEMP_M 0x000000E0 // Temperature Range
416 #define SYSCTL_DID1_TEMP_C 0x00000000 // Commercial temperature range
417 #define SYSCTL_DID1_TEMP_I 0x00000020 // Industrial temperature range
418 #define SYSCTL_DID1_TEMP_E 0x00000040 // Extended temperature range
419 #define SYSCTL_DID1_TEMP_IE 0x00000060 // Available in both industrial
420  // temperature range (-40C to 85C)
421  // and extended temperature range
422  // (-40C to 105C) devices. See
423 #define SYSCTL_DID1_PKG_M 0x00000018 // Package Type
424 #define SYSCTL_DID1_PKG_QFP 0x00000008 // QFP package
425 #define SYSCTL_DID1_PKG_BGA 0x00000010 // BGA package
426 #define SYSCTL_DID1_ROHS 0x00000004 // RoHS-Compliance
427 #define SYSCTL_DID1_QUAL_M 0x00000003 // Qualification Status
428 #define SYSCTL_DID1_QUAL_ES 0x00000000 // Engineering Sample (unqualified)
429 #define SYSCTL_DID1_QUAL_PP 0x00000001 // Pilot Production (unqualified)
430 #define SYSCTL_DID1_QUAL_FQ 0x00000002 // Fully Qualified
431 
432 //*****************************************************************************
433 //
434 // The following are defines for the bit fields in the SYSCTL_PTBOCTL register.
435 //
436 //*****************************************************************************
437 #define SYSCTL_PTBOCTL_VDDA_UBOR_M \
438  0x00000300 // VDDA under BOR Event Action
439 #define SYSCTL_PTBOCTL_VDDA_UBOR_NONE \
440  0x00000000 // No Action
441 #define SYSCTL_PTBOCTL_VDDA_UBOR_SYSINT \
442  0x00000100 // System control interrupt
443 #define SYSCTL_PTBOCTL_VDDA_UBOR_NMI \
444  0x00000200 // NMI
445 #define SYSCTL_PTBOCTL_VDDA_UBOR_RST \
446  0x00000300 // Reset
447 #define SYSCTL_PTBOCTL_VDD_UBOR_M \
448  0x00000003 // VDD (VDDS) under BOR Event
449  // Action
450 #define SYSCTL_PTBOCTL_VDD_UBOR_NONE \
451  0x00000000 // No Action
452 #define SYSCTL_PTBOCTL_VDD_UBOR_SYSINT \
453  0x00000001 // System control interrupt
454 #define SYSCTL_PTBOCTL_VDD_UBOR_NMI \
455  0x00000002 // NMI
456 #define SYSCTL_PTBOCTL_VDD_UBOR_RST \
457  0x00000003 // Reset
458 
459 //*****************************************************************************
460 //
461 // The following are defines for the bit fields in the SYSCTL_RIS register.
462 //
463 //*****************************************************************************
464 #define SYSCTL_RIS_MOSCPUPRIS 0x00000100 // MOSC Power Up Raw Interrupt
465  // Status
466 #define SYSCTL_RIS_PLLLRIS 0x00000040 // PLL Lock Raw Interrupt Status
467 #define SYSCTL_RIS_MOFRIS 0x00000008 // Main Oscillator Failure Raw
468  // Interrupt Status
469 #define SYSCTL_RIS_BORRIS 0x00000002 // Brown-Out Reset Raw Interrupt
470  // Status
471 
472 //*****************************************************************************
473 //
474 // The following are defines for the bit fields in the SYSCTL_IMC register.
475 //
476 //*****************************************************************************
477 #define SYSCTL_IMC_MOSCPUPIM 0x00000100 // MOSC Power Up Interrupt Mask
478 #define SYSCTL_IMC_PLLLIM 0x00000040 // PLL Lock Interrupt Mask
479 #define SYSCTL_IMC_MOFIM 0x00000008 // Main Oscillator Failure
480  // Interrupt Mask
481 #define SYSCTL_IMC_BORIM 0x00000002 // Brown-Out Reset Interrupt Mask
482 
483 //*****************************************************************************
484 //
485 // The following are defines for the bit fields in the SYSCTL_MISC register.
486 //
487 //*****************************************************************************
488 #define SYSCTL_MISC_MOSCPUPMIS 0x00000100 // MOSC Power Up Masked Interrupt
489  // Status
490 #define SYSCTL_MISC_PLLLMIS 0x00000040 // PLL Lock Masked Interrupt Status
491 #define SYSCTL_MISC_MOFMIS 0x00000008 // Main Oscillator Failure Masked
492  // Interrupt Status
493 #define SYSCTL_MISC_BORMIS 0x00000002 // BOR Masked Interrupt Status
494 
495 //*****************************************************************************
496 //
497 // The following are defines for the bit fields in the SYSCTL_RESC register.
498 //
499 //*****************************************************************************
500 #define SYSCTL_RESC_MOSCFAIL 0x00010000 // MOSC Failure Reset
501 #define SYSCTL_RESC_HSSR 0x00001000 // HSSR Reset
502 #define SYSCTL_RESC_WDT1 0x00000020 // Watchdog Timer 1 Reset
503 #define SYSCTL_RESC_SW 0x00000010 // Software Reset
504 #define SYSCTL_RESC_WDT0 0x00000008 // Watchdog Timer 0 Reset
505 #define SYSCTL_RESC_BOR 0x00000004 // Brown-Out Reset
506 #define SYSCTL_RESC_POR 0x00000002 // Power-On Reset
507 #define SYSCTL_RESC_EXT 0x00000001 // External Reset
508 
509 //*****************************************************************************
510 //
511 // The following are defines for the bit fields in the SYSCTL_PWRTC register.
512 //
513 //*****************************************************************************
514 #define SYSCTL_PWRTC_VDDA_UBOR 0x00000010 // VDDA Under BOR Status
515 #define SYSCTL_PWRTC_VDD_UBOR 0x00000001 // VDD Under BOR Status
516 
517 //*****************************************************************************
518 //
519 // The following are defines for the bit fields in the SYSCTL_NMIC register.
520 //
521 //*****************************************************************************
522 #define SYSCTL_NMIC_MOSCFAIL 0x00010000 // MOSC Failure NMI
523 #define SYSCTL_NMIC_TAMPER 0x00000200 // Tamper Event NMI
524 #define SYSCTL_NMIC_WDT1 0x00000020 // Watch Dog Timer (WDT) 1 NMI
525 #define SYSCTL_NMIC_WDT0 0x00000008 // Watch Dog Timer (WDT) 0 NMI
526 #define SYSCTL_NMIC_POWER 0x00000004 // Power/Brown Out Event NMI
527 #define SYSCTL_NMIC_EXTERNAL 0x00000001 // External Pin NMI
528 
529 //*****************************************************************************
530 //
531 // The following are defines for the bit fields in the SYSCTL_MOSCCTL register.
532 //
533 //*****************************************************************************
534 #define SYSCTL_MOSCCTL_OSCRNG 0x00000010 // Oscillator Range
535 #define SYSCTL_MOSCCTL_PWRDN 0x00000008 // Power Down
536 #define SYSCTL_MOSCCTL_NOXTAL 0x00000004 // No Crystal Connected
537 #define SYSCTL_MOSCCTL_MOSCIM 0x00000002 // MOSC Failure Action
538 #define SYSCTL_MOSCCTL_CVAL 0x00000001 // Clock Validation for MOSC
539 
540 //*****************************************************************************
541 //
542 // The following are defines for the bit fields in the SYSCTL_RSCLKCFG
543 // register.
544 //
545 //*****************************************************************************
546 #define SYSCTL_RSCLKCFG_MEMTIMU 0x80000000 // Memory Timing Register Update
547 #define SYSCTL_RSCLKCFG_NEWFREQ 0x40000000 // New PLLFREQ Accept
548 #define SYSCTL_RSCLKCFG_ACG 0x20000000 // Auto Clock Gating
549 #define SYSCTL_RSCLKCFG_USEPLL 0x10000000 // Use PLL
550 #define SYSCTL_RSCLKCFG_PLLSRC_M \
551  0x0F000000 // PLL Source
552 #define SYSCTL_RSCLKCFG_PLLSRC_PIOSC \
553  0x00000000 // PIOSC is PLL input clock source
554 #define SYSCTL_RSCLKCFG_PLLSRC_MOSC \
555  0x03000000 // MOSC is the PLL input clock
556  // source
557 #define SYSCTL_RSCLKCFG_OSCSRC_M \
558  0x00F00000 // Oscillator Source
559 #define SYSCTL_RSCLKCFG_OSCSRC_PIOSC \
560  0x00000000 // PIOSC is oscillator source
561 #define SYSCTL_RSCLKCFG_OSCSRC_LFIOSC \
562  0x00200000 // LFIOSC is oscillator source
563 #define SYSCTL_RSCLKCFG_OSCSRC_MOSC \
564  0x00300000 // MOSC is oscillator source
565 #define SYSCTL_RSCLKCFG_OSCSRC_RTC \
566  0x00400000 // Hibernation Module RTC
567  // Oscillator (RTCOSC)
568 #define SYSCTL_RSCLKCFG_OSYSDIV_M \
569  0x000FFC00 // Oscillator System Clock Divisor
570 #define SYSCTL_RSCLKCFG_PSYSDIV_M \
571  0x000003FF // PLL System Clock Divisor
572 #define SYSCTL_RSCLKCFG_OSYSDIV_S \
573  10
574 #define SYSCTL_RSCLKCFG_PSYSDIV_S \
575  0
576 
577 //*****************************************************************************
578 //
579 // The following are defines for the bit fields in the SYSCTL_MEMTIM0 register.
580 //
581 //*****************************************************************************
582 #define SYSCTL_MEMTIM0_EBCHT_M 0x03C00000 // EEPROM Clock High Time
583 #define SYSCTL_MEMTIM0_EBCHT_0_5 \
584  0x00000000 // 1/2 system clock period
585 #define SYSCTL_MEMTIM0_EBCHT_1 0x00400000 // 1 system clock period
586 #define SYSCTL_MEMTIM0_EBCHT_1_5 \
587  0x00800000 // 1.5 system clock periods
588 #define SYSCTL_MEMTIM0_EBCHT_2 0x00C00000 // 2 system clock periods
589 #define SYSCTL_MEMTIM0_EBCHT_2_5 \
590  0x01000000 // 2.5 system clock periods
591 #define SYSCTL_MEMTIM0_EBCHT_3 0x01400000 // 3 system clock periods
592 #define SYSCTL_MEMTIM0_EBCHT_3_5 \
593  0x01800000 // 3.5 system clock periods
594 #define SYSCTL_MEMTIM0_EBCHT_4 0x01C00000 // 4 system clock periods
595 #define SYSCTL_MEMTIM0_EBCHT_4_5 \
596  0x02000000 // 4.5 system clock periods
597 #define SYSCTL_MEMTIM0_EBCE 0x00200000 // EEPROM Bank Clock Edge
598 #define SYSCTL_MEMTIM0_MB1 0x00100010 // Must be one
599 #define SYSCTL_MEMTIM0_EWS_M 0x000F0000 // EEPROM Wait States
600 #define SYSCTL_MEMTIM0_FBCHT_M 0x000003C0 // Flash Bank Clock High Time
601 #define SYSCTL_MEMTIM0_FBCHT_0_5 \
602  0x00000000 // 1/2 system clock period
603 #define SYSCTL_MEMTIM0_FBCHT_1 0x00000040 // 1 system clock period
604 #define SYSCTL_MEMTIM0_FBCHT_1_5 \
605  0x00000080 // 1.5 system clock periods
606 #define SYSCTL_MEMTIM0_FBCHT_2 0x000000C0 // 2 system clock periods
607 #define SYSCTL_MEMTIM0_FBCHT_2_5 \
608  0x00000100 // 2.5 system clock periods
609 #define SYSCTL_MEMTIM0_FBCHT_3 0x00000140 // 3 system clock periods
610 #define SYSCTL_MEMTIM0_FBCHT_3_5 \
611  0x00000180 // 3.5 system clock periods
612 #define SYSCTL_MEMTIM0_FBCHT_4 0x000001C0 // 4 system clock periods
613 #define SYSCTL_MEMTIM0_FBCHT_4_5 \
614  0x00000200 // 4.5 system clock periods
615 #define SYSCTL_MEMTIM0_FBCE 0x00000020 // Flash Bank Clock Edge
616 #define SYSCTL_MEMTIM0_FWS_M 0x0000000F // Flash Wait State
617 #define SYSCTL_MEMTIM0_EWS_S 16
618 #define SYSCTL_MEMTIM0_FWS_S 0
619 
620 //*****************************************************************************
621 //
622 // The following are defines for the bit fields in the SYSCTL_ALTCLKCFG
623 // register.
624 //
625 //*****************************************************************************
626 #define SYSCTL_ALTCLKCFG_ALTCLK_M \
627  0x0000000F // Alternate Clock Source
628 #define SYSCTL_ALTCLKCFG_ALTCLK_PIOSC \
629  0x00000000 // PIOSC
630 #define SYSCTL_ALTCLKCFG_ALTCLK_RTCOSC \
631  0x00000003 // Hibernation Module Real-time
632  // clock output (RTCOSC)
633 #define SYSCTL_ALTCLKCFG_ALTCLK_LFIOSC \
634  0x00000004 // Low-frequency internal
635  // oscillator (LFIOSC)
636 
637 //*****************************************************************************
638 //
639 // The following are defines for the bit fields in the SYSCTL_DSCLKCFG
640 // register.
641 //
642 //*****************************************************************************
643 #define SYSCTL_DSCLKCFG_PIOSCPD 0x80000000 // PIOSC Power Down
644 #define SYSCTL_DSCLKCFG_MOSCDPD 0x40000000 // MOSC Disable Power Down
645 #define SYSCTL_DSCLKCFG_DSOSCSRC_M \
646  0x00F00000 // Deep Sleep Oscillator Source
647 #define SYSCTL_DSCLKCFG_DSOSCSRC_PIOSC \
648  0x00000000 // PIOSC
649 #define SYSCTL_DSCLKCFG_DSOSCSRC_LFIOSC \
650  0x00200000 // LFIOSC
651 #define SYSCTL_DSCLKCFG_DSOSCSRC_MOSC \
652  0x00300000 // MOSC
653 #define SYSCTL_DSCLKCFG_DSOSCSRC_RTC \
654  0x00400000 // Hibernation Module RTCOSC
655 #define SYSCTL_DSCLKCFG_DSSYSDIV_M \
656  0x000003FF // Deep Sleep Clock Divisor
657 #define SYSCTL_DSCLKCFG_DSSYSDIV_S \
658  0
659 
660 //*****************************************************************************
661 //
662 // The following are defines for the bit fields in the SYSCTL_DIVSCLK register.
663 //
664 //*****************************************************************************
665 #define SYSCTL_DIVSCLK_EN 0x80000000 // DIVSCLK Enable
666 #define SYSCTL_DIVSCLK_SRC_M 0x00030000 // Clock Source
667 #define SYSCTL_DIVSCLK_SRC_SYSCLK \
668  0x00000000 // System Clock
669 #define SYSCTL_DIVSCLK_SRC_PIOSC \
670  0x00010000 // PIOSC
671 #define SYSCTL_DIVSCLK_SRC_MOSC 0x00020000 // MOSC
672 #define SYSCTL_DIVSCLK_DIV_M 0x000000FF // Divisor Value
673 #define SYSCTL_DIVSCLK_DIV_S 0
674 
675 //*****************************************************************************
676 //
677 // The following are defines for the bit fields in the SYSCTL_SYSPROP register.
678 //
679 //*****************************************************************************
680 #define SYSCTL_SYSPROP_FPU 0x00000001 // FPU Present
681 
682 //*****************************************************************************
683 //
684 // The following are defines for the bit fields in the SYSCTL_PIOSCCAL
685 // register.
686 //
687 //*****************************************************************************
688 #define SYSCTL_PIOSCCAL_UTEN 0x80000000 // Use User Trim Value
689 #define SYSCTL_PIOSCCAL_CAL 0x00000200 // Start Calibration
690 #define SYSCTL_PIOSCCAL_UPDATE 0x00000100 // Update Trim
691 #define SYSCTL_PIOSCCAL_UT_M 0x0000007F // User Trim Value
692 #define SYSCTL_PIOSCCAL_UT_S 0
693 
694 //*****************************************************************************
695 //
696 // The following are defines for the bit fields in the SYSCTL_PIOSCSTAT
697 // register.
698 //
699 //*****************************************************************************
700 #define SYSCTL_PIOSCSTAT_DT_M 0x007F0000 // Default Trim Value
701 #define SYSCTL_PIOSCSTAT_CR_M 0x00000300 // Calibration Result
702 #define SYSCTL_PIOSCSTAT_CRNONE 0x00000000 // Calibration has not been
703  // attempted
704 #define SYSCTL_PIOSCSTAT_CRPASS 0x00000100 // The last calibration operation
705  // completed to meet 1% accuracy
706 #define SYSCTL_PIOSCSTAT_CRFAIL 0x00000200 // The last calibration operation
707  // failed to meet 1% accuracy
708 #define SYSCTL_PIOSCSTAT_CT_M 0x0000007F // Calibration Trim Value
709 #define SYSCTL_PIOSCSTAT_DT_S 16
710 #define SYSCTL_PIOSCSTAT_CT_S 0
711 
712 //*****************************************************************************
713 //
714 // The following are defines for the bit fields in the SYSCTL_PLLFREQ0
715 // register.
716 //
717 //*****************************************************************************
718 #define SYSCTL_PLLFREQ0_PLLPWR 0x00800000 // PLL Power
719 #define SYSCTL_PLLFREQ0_MFRAC_M 0x000FFC00 // PLL M Fractional Value
720 #define SYSCTL_PLLFREQ0_MINT_M 0x000003FF // PLL M Integer Value
721 #define SYSCTL_PLLFREQ0_MFRAC_S 10
722 #define SYSCTL_PLLFREQ0_MINT_S 0
723 
724 //*****************************************************************************
725 //
726 // The following are defines for the bit fields in the SYSCTL_PLLFREQ1
727 // register.
728 //
729 //*****************************************************************************
730 #define SYSCTL_PLLFREQ1_Q_M 0x00001F00 // PLL Q Value
731 #define SYSCTL_PLLFREQ1_N_M 0x0000001F // PLL N Value
732 #define SYSCTL_PLLFREQ1_Q_S 8
733 #define SYSCTL_PLLFREQ1_N_S 0
734 
735 //*****************************************************************************
736 //
737 // The following are defines for the bit fields in the SYSCTL_PLLSTAT register.
738 //
739 //*****************************************************************************
740 #define SYSCTL_PLLSTAT_LOCK 0x00000001 // PLL Lock
741 
742 //*****************************************************************************
743 //
744 // The following are defines for the bit fields in the SYSCTL_SLPPWRCFG
745 // register.
746 //
747 //*****************************************************************************
748 #define SYSCTL_SLPPWRCFG_FLASHPM_M \
749  0x00000030 // Flash Power Modes
750 #define SYSCTL_SLPPWRCFG_FLASHPM_NRM \
751  0x00000000 // Active Mode
752 #define SYSCTL_SLPPWRCFG_FLASHPM_SLP \
753  0x00000020 // Low Power Mode
754 #define SYSCTL_SLPPWRCFG_SRAMPM_M \
755  0x00000003 // SRAM Power Modes
756 #define SYSCTL_SLPPWRCFG_SRAMPM_NRM \
757  0x00000000 // Active Mode
758 #define SYSCTL_SLPPWRCFG_SRAMPM_SBY \
759  0x00000001 // Standby Mode
760 #define SYSCTL_SLPPWRCFG_SRAMPM_LP \
761  0x00000003 // Low Power Mode
762 
763 //*****************************************************************************
764 //
765 // The following are defines for the bit fields in the SYSCTL_DSLPPWRCFG
766 // register.
767 //
768 //*****************************************************************************
769 #define SYSCTL_DSLPPWRCFG_LDOSM 0x00000200 // LDO Sleep Mode
770 #define SYSCTL_DSLPPWRCFG_TSPD 0x00000100 // Temperature Sense Power Down
771 #define SYSCTL_DSLPPWRCFG_FLASHPM_M \
772  0x00000030 // Flash Power Modes
773 #define SYSCTL_DSLPPWRCFG_FLASHPM_NRM \
774  0x00000000 // Active Mode
775 #define SYSCTL_DSLPPWRCFG_FLASHPM_SLP \
776  0x00000020 // Low Power Mode
777 #define SYSCTL_DSLPPWRCFG_SRAMPM_M \
778  0x00000003 // SRAM Power Modes
779 #define SYSCTL_DSLPPWRCFG_SRAMPM_NRM \
780  0x00000000 // Active Mode
781 #define SYSCTL_DSLPPWRCFG_SRAMPM_SBY \
782  0x00000001 // Standby Mode
783 #define SYSCTL_DSLPPWRCFG_SRAMPM_LP \
784  0x00000003 // Low Power Mode
785 
786 //*****************************************************************************
787 //
788 // The following are defines for the bit fields in the SYSCTL_NVMSTAT register.
789 //
790 //*****************************************************************************
791 #define SYSCTL_NVMSTAT_FWB 0x00000001 // 32 Word Flash Write Buffer
792  // Available
793 
794 //*****************************************************************************
795 //
796 // The following are defines for the bit fields in the SYSCTL_LDOSPCTL
797 // register.
798 //
799 //*****************************************************************************
800 #define SYSCTL_LDOSPCTL_VADJEN 0x80000000 // Voltage Adjust Enable
801 #define SYSCTL_LDOSPCTL_VLDO_M 0x000000FF // LDO Output Voltage
802 #define SYSCTL_LDOSPCTL_VLDO_0_90V \
803  0x00000012 // 0.90 V
804 #define SYSCTL_LDOSPCTL_VLDO_0_95V \
805  0x00000013 // 0.95 V
806 #define SYSCTL_LDOSPCTL_VLDO_1_00V \
807  0x00000014 // 1.00 V
808 #define SYSCTL_LDOSPCTL_VLDO_1_05V \
809  0x00000015 // 1.05 V
810 #define SYSCTL_LDOSPCTL_VLDO_1_10V \
811  0x00000016 // 1.10 V
812 #define SYSCTL_LDOSPCTL_VLDO_1_15V \
813  0x00000017 // 1.15 V
814 #define SYSCTL_LDOSPCTL_VLDO_1_20V \
815  0x00000018 // 1.20 V
816 
817 //*****************************************************************************
818 //
819 // The following are defines for the bit fields in the SYSCTL_LDODPCTL
820 // register.
821 //
822 //*****************************************************************************
823 #define SYSCTL_LDODPCTL_VADJEN 0x80000000 // Voltage Adjust Enable
824 #define SYSCTL_LDODPCTL_VLDO_M 0x000000FF // LDO Output Voltage
825 #define SYSCTL_LDODPCTL_VLDO_0_90V \
826  0x00000012 // 0.90 V
827 #define SYSCTL_LDODPCTL_VLDO_0_95V \
828  0x00000013 // 0.95 V
829 #define SYSCTL_LDODPCTL_VLDO_1_00V \
830  0x00000014 // 1.00 V
831 #define SYSCTL_LDODPCTL_VLDO_1_05V \
832  0x00000015 // 1.05 V
833 #define SYSCTL_LDODPCTL_VLDO_1_10V \
834  0x00000016 // 1.10 V
835 #define SYSCTL_LDODPCTL_VLDO_1_15V \
836  0x00000017 // 1.15 V
837 #define SYSCTL_LDODPCTL_VLDO_1_20V \
838  0x00000018 // 1.20 V
839 
840 //*****************************************************************************
841 //
842 // The following are defines for the bit fields in the SYSCTL_RESBEHAVCTL
843 // register.
844 //
845 //*****************************************************************************
846 #define SYSCTL_RESBEHAVCTL_WDOG1_M \
847  0x000000C0 // Watchdog 1 Reset Operation
848 #define SYSCTL_RESBEHAVCTL_WDOG1_SYSRST \
849  0x00000080 // Watchdog 1 issues a system
850  // reset. The application starts
851  // within 10 us
852 #define SYSCTL_RESBEHAVCTL_WDOG1_POR \
853  0x000000C0 // Watchdog 1 issues a simulated
854  // POR sequence. Application starts
855  // less than 500 us after
856  // deassertion (Default)
857 #define SYSCTL_RESBEHAVCTL_WDOG0_M \
858  0x00000030 // Watchdog 0 Reset Operation
859 #define SYSCTL_RESBEHAVCTL_WDOG0_SYSRST \
860  0x00000020 // Watchdog 0 issues a system
861  // reset. The application starts
862  // within 10 us
863 #define SYSCTL_RESBEHAVCTL_WDOG0_POR \
864  0x00000030 // Watchdog 0 issues a simulated
865  // POR sequence. Application starts
866  // less than 500 us after
867  // deassertion (Default)
868 #define SYSCTL_RESBEHAVCTL_BOR_M \
869  0x0000000C // BOR Reset operation
870 #define SYSCTL_RESBEHAVCTL_BOR_SYSRST \
871  0x00000008 // Brown Out Reset issues system
872  // reset. The application starts
873  // within 10 us
874 #define SYSCTL_RESBEHAVCTL_BOR_POR \
875  0x0000000C // Brown Out Reset issues a
876  // simulated POR sequence. The
877  // application starts less than 500
878  // us after deassertion (Default)
879 #define SYSCTL_RESBEHAVCTL_EXTRES_M \
880  0x00000003 // External RST Pin Operation
881 #define SYSCTL_RESBEHAVCTL_EXTRES_SYSRST \
882  0x00000002 // External RST assertion issues a
883  // system reset. The application
884  // starts within 10 us
885 #define SYSCTL_RESBEHAVCTL_EXTRES_POR \
886  0x00000003 // External RST assertion issues a
887  // simulated POR sequence.
888  // Application starts less than 500
889  // us after deassertion (Default)
890 
891 //*****************************************************************************
892 //
893 // The following are defines for the bit fields in the SYSCTL_HSSR register.
894 //
895 //*****************************************************************************
896 #define SYSCTL_HSSR_KEY_M 0xFF000000 // Write Key
897 #define SYSCTL_HSSR_CDOFF_M 0x00FFFFFF // Command Descriptor Pointer
898 #define SYSCTL_HSSR_KEY_S 24
899 #define SYSCTL_HSSR_CDOFF_S 0
900 
901 //*****************************************************************************
902 //
903 // The following are defines for the bit fields in the SYSCTL_USBPDS register.
904 //
905 //*****************************************************************************
906 #define SYSCTL_USBPDS_MEMSTAT_M 0x0000000C // Memory Array Power Status
907 #define SYSCTL_USBPDS_MEMSTAT_OFF \
908  0x00000000 // Array OFF
909 #define SYSCTL_USBPDS_MEMSTAT_RETAIN \
910  0x00000004 // SRAM Retention
911 #define SYSCTL_USBPDS_MEMSTAT_ON \
912  0x0000000C // Array On
913 #define SYSCTL_USBPDS_PWRSTAT_M 0x00000003 // Power Domain Status
914 #define SYSCTL_USBPDS_PWRSTAT_OFF \
915  0x00000000 // OFF
916 #define SYSCTL_USBPDS_PWRSTAT_ON \
917  0x00000003 // ON
918 
919 //*****************************************************************************
920 //
921 // The following are defines for the bit fields in the SYSCTL_USBMPC register.
922 //
923 //*****************************************************************************
924 #define SYSCTL_USBMPC_PWRCTL_M 0x00000003 // Memory Array Power Control
925 #define SYSCTL_USBMPC_PWRCTL_OFF \
926  0x00000000 // Array OFF
927 #define SYSCTL_USBMPC_PWRCTL_RETAIN \
928  0x00000001 // SRAM Retention
929 #define SYSCTL_USBMPC_PWRCTL_ON 0x00000003 // Array On
930 
931 //*****************************************************************************
932 //
933 // The following are defines for the bit fields in the SYSCTL_EMACPDS register.
934 //
935 //*****************************************************************************
936 #define SYSCTL_EMACPDS_MEMSTAT_M \
937  0x0000000C // Memory Array Power Status
938 #define SYSCTL_EMACPDS_MEMSTAT_OFF \
939  0x00000000 // Array OFF
940 #define SYSCTL_EMACPDS_MEMSTAT_ON \
941  0x0000000C // Array On
942 #define SYSCTL_EMACPDS_PWRSTAT_M \
943  0x00000003 // Power Domain Status
944 #define SYSCTL_EMACPDS_PWRSTAT_OFF \
945  0x00000000 // OFF
946 #define SYSCTL_EMACPDS_PWRSTAT_ON \
947  0x00000003 // ON
948 
949 //*****************************************************************************
950 //
951 // The following are defines for the bit fields in the SYSCTL_EMACMPC register.
952 //
953 //*****************************************************************************
954 #define SYSCTL_EMACMPC_PWRCTL_M 0x00000003 // Memory Array Power Control
955 #define SYSCTL_EMACMPC_PWRCTL_OFF \
956  0x00000000 // Array OFF
957 #define SYSCTL_EMACMPC_PWRCTL_ON \
958  0x00000003 // Array On
959 
960 //*****************************************************************************
961 //
962 // The following are defines for the bit fields in the SYSCTL_LCDMPC register.
963 //
964 //*****************************************************************************
965 #define SYSCTL_LCDMPC_PWRCTL_M 0x00000003 // Memory Array Power Control
966 #define SYSCTL_LCDMPC_PWRCTL_OFF \
967  0x00000000 // Array OFF
968 #define SYSCTL_LCDMPC_PWRCTL_ON 0x00000003 // Array On
969 
970 //*****************************************************************************
971 //
972 // The following are defines for the bit fields in the SYSCTL_PPWD register.
973 //
974 //*****************************************************************************
975 #define SYSCTL_PPWD_P1 0x00000002 // Watchdog Timer 1 Present
976 #define SYSCTL_PPWD_P0 0x00000001 // Watchdog Timer 0 Present
977 
978 //*****************************************************************************
979 //
980 // The following are defines for the bit fields in the SYSCTL_PPTIMER register.
981 //
982 //*****************************************************************************
983 #define SYSCTL_PPTIMER_P7 0x00000080 // 16/32-Bit General-Purpose Timer
984  // 7 Present
985 #define SYSCTL_PPTIMER_P6 0x00000040 // 16/32-Bit General-Purpose Timer
986  // 6 Present
987 #define SYSCTL_PPTIMER_P5 0x00000020 // 16/32-Bit General-Purpose Timer
988  // 5 Present
989 #define SYSCTL_PPTIMER_P4 0x00000010 // 16/32-Bit General-Purpose Timer
990  // 4 Present
991 #define SYSCTL_PPTIMER_P3 0x00000008 // 16/32-Bit General-Purpose Timer
992  // 3 Present
993 #define SYSCTL_PPTIMER_P2 0x00000004 // 16/32-Bit General-Purpose Timer
994  // 2 Present
995 #define SYSCTL_PPTIMER_P1 0x00000002 // 16/32-Bit General-Purpose Timer
996  // 1 Present
997 #define SYSCTL_PPTIMER_P0 0x00000001 // 16/32-Bit General-Purpose Timer
998  // 0 Present
999 
1000 //*****************************************************************************
1001 //
1002 // The following are defines for the bit fields in the SYSCTL_PPGPIO register.
1003 //
1004 //*****************************************************************************
1005 #define SYSCTL_PPGPIO_P17 0x00020000 // GPIO Port T Present
1006 #define SYSCTL_PPGPIO_P16 0x00010000 // GPIO Port S Present
1007 #define SYSCTL_PPGPIO_P15 0x00008000 // GPIO Port R Present
1008 #define SYSCTL_PPGPIO_P14 0x00004000 // GPIO Port Q Present
1009 #define SYSCTL_PPGPIO_P13 0x00002000 // GPIO Port P Present
1010 #define SYSCTL_PPGPIO_P12 0x00001000 // GPIO Port N Present
1011 #define SYSCTL_PPGPIO_P11 0x00000800 // GPIO Port M Present
1012 #define SYSCTL_PPGPIO_P10 0x00000400 // GPIO Port L Present
1013 #define SYSCTL_PPGPIO_P9 0x00000200 // GPIO Port K Present
1014 #define SYSCTL_PPGPIO_P8 0x00000100 // GPIO Port J Present
1015 #define SYSCTL_PPGPIO_P7 0x00000080 // GPIO Port H Present
1016 #define SYSCTL_PPGPIO_P6 0x00000040 // GPIO Port G Present
1017 #define SYSCTL_PPGPIO_P5 0x00000020 // GPIO Port F Present
1018 #define SYSCTL_PPGPIO_P4 0x00000010 // GPIO Port E Present
1019 #define SYSCTL_PPGPIO_P3 0x00000008 // GPIO Port D Present
1020 #define SYSCTL_PPGPIO_P2 0x00000004 // GPIO Port C Present
1021 #define SYSCTL_PPGPIO_P1 0x00000002 // GPIO Port B Present
1022 #define SYSCTL_PPGPIO_P0 0x00000001 // GPIO Port A Present
1023 
1024 //*****************************************************************************
1025 //
1026 // The following are defines for the bit fields in the SYSCTL_PPDMA register.
1027 //
1028 //*****************************************************************************
1029 #define SYSCTL_PPDMA_P0 0x00000001 // uDMA Module Present
1030 
1031 //*****************************************************************************
1032 //
1033 // The following are defines for the bit fields in the SYSCTL_PPEPI register.
1034 //
1035 //*****************************************************************************
1036 #define SYSCTL_PPEPI_P0 0x00000001 // EPI Module Present
1037 
1038 //*****************************************************************************
1039 //
1040 // The following are defines for the bit fields in the SYSCTL_PPHIB register.
1041 //
1042 //*****************************************************************************
1043 #define SYSCTL_PPHIB_P0 0x00000001 // Hibernation Module Present
1044 
1045 //*****************************************************************************
1046 //
1047 // The following are defines for the bit fields in the SYSCTL_PPUART register.
1048 //
1049 //*****************************************************************************
1050 #define SYSCTL_PPUART_P7 0x00000080 // UART Module 7 Present
1051 #define SYSCTL_PPUART_P6 0x00000040 // UART Module 6 Present
1052 #define SYSCTL_PPUART_P5 0x00000020 // UART Module 5 Present
1053 #define SYSCTL_PPUART_P4 0x00000010 // UART Module 4 Present
1054 #define SYSCTL_PPUART_P3 0x00000008 // UART Module 3 Present
1055 #define SYSCTL_PPUART_P2 0x00000004 // UART Module 2 Present
1056 #define SYSCTL_PPUART_P1 0x00000002 // UART Module 1 Present
1057 #define SYSCTL_PPUART_P0 0x00000001 // UART Module 0 Present
1058 
1059 //*****************************************************************************
1060 //
1061 // The following are defines for the bit fields in the SYSCTL_PPSSI register.
1062 //
1063 //*****************************************************************************
1064 #define SYSCTL_PPSSI_P3 0x00000008 // SSI Module 3 Present
1065 #define SYSCTL_PPSSI_P2 0x00000004 // SSI Module 2 Present
1066 #define SYSCTL_PPSSI_P1 0x00000002 // SSI Module 1 Present
1067 #define SYSCTL_PPSSI_P0 0x00000001 // SSI Module 0 Present
1068 
1069 //*****************************************************************************
1070 //
1071 // The following are defines for the bit fields in the SYSCTL_PPI2C register.
1072 //
1073 //*****************************************************************************
1074 #define SYSCTL_PPI2C_P9 0x00000200 // I2C Module 9 Present
1075 #define SYSCTL_PPI2C_P8 0x00000100 // I2C Module 8 Present
1076 #define SYSCTL_PPI2C_P7 0x00000080 // I2C Module 7 Present
1077 #define SYSCTL_PPI2C_P6 0x00000040 // I2C Module 6 Present
1078 #define SYSCTL_PPI2C_P5 0x00000020 // I2C Module 5 Present
1079 #define SYSCTL_PPI2C_P4 0x00000010 // I2C Module 4 Present
1080 #define SYSCTL_PPI2C_P3 0x00000008 // I2C Module 3 Present
1081 #define SYSCTL_PPI2C_P2 0x00000004 // I2C Module 2 Present
1082 #define SYSCTL_PPI2C_P1 0x00000002 // I2C Module 1 Present
1083 #define SYSCTL_PPI2C_P0 0x00000001 // I2C Module 0 Present
1084 
1085 //*****************************************************************************
1086 //
1087 // The following are defines for the bit fields in the SYSCTL_PPUSB register.
1088 //
1089 //*****************************************************************************
1090 #define SYSCTL_PPUSB_P0 0x00000001 // USB Module Present
1091 
1092 //*****************************************************************************
1093 //
1094 // The following are defines for the bit fields in the SYSCTL_PPEPHY register.
1095 //
1096 //*****************************************************************************
1097 #define SYSCTL_PPEPHY_P0 0x00000001 // Ethernet PHY Module Present
1098 
1099 //*****************************************************************************
1100 //
1101 // The following are defines for the bit fields in the SYSCTL_PPCAN register.
1102 //
1103 //*****************************************************************************
1104 #define SYSCTL_PPCAN_P1 0x00000002 // CAN Module 1 Present
1105 #define SYSCTL_PPCAN_P0 0x00000001 // CAN Module 0 Present
1106 
1107 //*****************************************************************************
1108 //
1109 // The following are defines for the bit fields in the SYSCTL_PPADC register.
1110 //
1111 //*****************************************************************************
1112 #define SYSCTL_PPADC_P1 0x00000002 // ADC Module 1 Present
1113 #define SYSCTL_PPADC_P0 0x00000001 // ADC Module 0 Present
1114 
1115 //*****************************************************************************
1116 //
1117 // The following are defines for the bit fields in the SYSCTL_PPACMP register.
1118 //
1119 //*****************************************************************************
1120 #define SYSCTL_PPACMP_P0 0x00000001 // Analog Comparator Module Present
1121 
1122 //*****************************************************************************
1123 //
1124 // The following are defines for the bit fields in the SYSCTL_PPPWM register.
1125 //
1126 //*****************************************************************************
1127 #define SYSCTL_PPPWM_P1 0x00000002 // PWM Module 1 Present
1128 #define SYSCTL_PPPWM_P0 0x00000001 // PWM Module 0 Present
1129 
1130 //*****************************************************************************
1131 //
1132 // The following are defines for the bit fields in the SYSCTL_PPQEI register.
1133 //
1134 //*****************************************************************************
1135 #define SYSCTL_PPQEI_P1 0x00000002 // QEI Module 1 Present
1136 #define SYSCTL_PPQEI_P0 0x00000001 // QEI Module 0 Present
1137 
1138 //*****************************************************************************
1139 //
1140 // The following are defines for the bit fields in the SYSCTL_PPEEPROM
1141 // register.
1142 //
1143 //*****************************************************************************
1144 #define SYSCTL_PPEEPROM_P0 0x00000001 // EEPROM Module Present
1145 
1146 //*****************************************************************************
1147 //
1148 // The following are defines for the bit fields in the SYSCTL_PPCCM register.
1149 //
1150 //*****************************************************************************
1151 #define SYSCTL_PPCCM_P0 0x00000001 // CRC and Cryptographic Modules
1152  // Present
1153 
1154 //*****************************************************************************
1155 //
1156 // The following are defines for the bit fields in the SYSCTL_PPLCD register.
1157 //
1158 //*****************************************************************************
1159 #define SYSCTL_PPLCD_P0 0x00000001 // LCD Module Present
1160 
1161 //*****************************************************************************
1162 //
1163 // The following are defines for the bit fields in the SYSCTL_PPOWIRE register.
1164 //
1165 //*****************************************************************************
1166 #define SYSCTL_PPOWIRE_P0 0x00000001 // 1-Wire Module Present
1167 
1168 //*****************************************************************************
1169 //
1170 // The following are defines for the bit fields in the SYSCTL_PPEMAC register.
1171 //
1172 //*****************************************************************************
1173 #define SYSCTL_PPEMAC_P0 0x00000001 // Ethernet Controller Module
1174  // Present
1175 
1176 //*****************************************************************************
1177 //
1178 // The following are defines for the bit fields in the SYSCTL_SRWD register.
1179 //
1180 //*****************************************************************************
1181 #define SYSCTL_SRWD_R1 0x00000002 // Watchdog Timer 1 Software Reset
1182 #define SYSCTL_SRWD_R0 0x00000001 // Watchdog Timer 0 Software Reset
1183 
1184 //*****************************************************************************
1185 //
1186 // The following are defines for the bit fields in the SYSCTL_SRTIMER register.
1187 //
1188 //*****************************************************************************
1189 #define SYSCTL_SRTIMER_R7 0x00000080 // 16/32-Bit General-Purpose Timer
1190  // 7 Software Reset
1191 #define SYSCTL_SRTIMER_R6 0x00000040 // 16/32-Bit General-Purpose Timer
1192  // 6 Software Reset
1193 #define SYSCTL_SRTIMER_R5 0x00000020 // 16/32-Bit General-Purpose Timer
1194  // 5 Software Reset
1195 #define SYSCTL_SRTIMER_R4 0x00000010 // 16/32-Bit General-Purpose Timer
1196  // 4 Software Reset
1197 #define SYSCTL_SRTIMER_R3 0x00000008 // 16/32-Bit General-Purpose Timer
1198  // 3 Software Reset
1199 #define SYSCTL_SRTIMER_R2 0x00000004 // 16/32-Bit General-Purpose Timer
1200  // 2 Software Reset
1201 #define SYSCTL_SRTIMER_R1 0x00000002 // 16/32-Bit General-Purpose Timer
1202  // 1 Software Reset
1203 #define SYSCTL_SRTIMER_R0 0x00000001 // 16/32-Bit General-Purpose Timer
1204  // 0 Software Reset
1205 
1206 //*****************************************************************************
1207 //
1208 // The following are defines for the bit fields in the SYSCTL_SRGPIO register.
1209 //
1210 //*****************************************************************************
1211 #define SYSCTL_SRGPIO_R17 0x00020000 // GPIO Port T Software Reset
1212 #define SYSCTL_SRGPIO_R16 0x00010000 // GPIO Port S Software Reset
1213 #define SYSCTL_SRGPIO_R15 0x00008000 // GPIO Port R Software Reset
1214 #define SYSCTL_SRGPIO_R14 0x00004000 // GPIO Port Q Software Reset
1215 #define SYSCTL_SRGPIO_R13 0x00002000 // GPIO Port P Software Reset
1216 #define SYSCTL_SRGPIO_R12 0x00001000 // GPIO Port N Software Reset
1217 #define SYSCTL_SRGPIO_R11 0x00000800 // GPIO Port M Software Reset
1218 #define SYSCTL_SRGPIO_R10 0x00000400 // GPIO Port L Software Reset
1219 #define SYSCTL_SRGPIO_R9 0x00000200 // GPIO Port K Software Reset
1220 #define SYSCTL_SRGPIO_R8 0x00000100 // GPIO Port J Software Reset
1221 #define SYSCTL_SRGPIO_R7 0x00000080 // GPIO Port H Software Reset
1222 #define SYSCTL_SRGPIO_R6 0x00000040 // GPIO Port G Software Reset
1223 #define SYSCTL_SRGPIO_R5 0x00000020 // GPIO Port F Software Reset
1224 #define SYSCTL_SRGPIO_R4 0x00000010 // GPIO Port E Software Reset
1225 #define SYSCTL_SRGPIO_R3 0x00000008 // GPIO Port D Software Reset
1226 #define SYSCTL_SRGPIO_R2 0x00000004 // GPIO Port C Software Reset
1227 #define SYSCTL_SRGPIO_R1 0x00000002 // GPIO Port B Software Reset
1228 #define SYSCTL_SRGPIO_R0 0x00000001 // GPIO Port A Software Reset
1229 
1230 //*****************************************************************************
1231 //
1232 // The following are defines for the bit fields in the SYSCTL_SRDMA register.
1233 //
1234 //*****************************************************************************
1235 #define SYSCTL_SRDMA_R0 0x00000001 // uDMA Module Software Reset
1236 
1237 //*****************************************************************************
1238 //
1239 // The following are defines for the bit fields in the SYSCTL_SREPI register.
1240 //
1241 //*****************************************************************************
1242 #define SYSCTL_SREPI_R0 0x00000001 // EPI Module Software Reset
1243 
1244 //*****************************************************************************
1245 //
1246 // The following are defines for the bit fields in the SYSCTL_SRHIB register.
1247 //
1248 //*****************************************************************************
1249 #define SYSCTL_SRHIB_R0 0x00000001 // Hibernation Module Software
1250  // Reset
1251 
1252 //*****************************************************************************
1253 //
1254 // The following are defines for the bit fields in the SYSCTL_SRUART register.
1255 //
1256 //*****************************************************************************
1257 #define SYSCTL_SRUART_R7 0x00000080 // UART Module 7 Software Reset
1258 #define SYSCTL_SRUART_R6 0x00000040 // UART Module 6 Software Reset
1259 #define SYSCTL_SRUART_R5 0x00000020 // UART Module 5 Software Reset
1260 #define SYSCTL_SRUART_R4 0x00000010 // UART Module 4 Software Reset
1261 #define SYSCTL_SRUART_R3 0x00000008 // UART Module 3 Software Reset
1262 #define SYSCTL_SRUART_R2 0x00000004 // UART Module 2 Software Reset
1263 #define SYSCTL_SRUART_R1 0x00000002 // UART Module 1 Software Reset
1264 #define SYSCTL_SRUART_R0 0x00000001 // UART Module 0 Software Reset
1265 
1266 //*****************************************************************************
1267 //
1268 // The following are defines for the bit fields in the SYSCTL_SRSSI register.
1269 //
1270 //*****************************************************************************
1271 #define SYSCTL_SRSSI_R3 0x00000008 // SSI Module 3 Software Reset
1272 #define SYSCTL_SRSSI_R2 0x00000004 // SSI Module 2 Software Reset
1273 #define SYSCTL_SRSSI_R1 0x00000002 // SSI Module 1 Software Reset
1274 #define SYSCTL_SRSSI_R0 0x00000001 // SSI Module 0 Software Reset
1275 
1276 //*****************************************************************************
1277 //
1278 // The following are defines for the bit fields in the SYSCTL_SRI2C register.
1279 //
1280 //*****************************************************************************
1281 #define SYSCTL_SRI2C_R9 0x00000200 // I2C Module 9 Software Reset
1282 #define SYSCTL_SRI2C_R8 0x00000100 // I2C Module 8 Software Reset
1283 #define SYSCTL_SRI2C_R7 0x00000080 // I2C Module 7 Software Reset
1284 #define SYSCTL_SRI2C_R6 0x00000040 // I2C Module 6 Software Reset
1285 #define SYSCTL_SRI2C_R5 0x00000020 // I2C Module 5 Software Reset
1286 #define SYSCTL_SRI2C_R4 0x00000010 // I2C Module 4 Software Reset
1287 #define SYSCTL_SRI2C_R3 0x00000008 // I2C Module 3 Software Reset
1288 #define SYSCTL_SRI2C_R2 0x00000004 // I2C Module 2 Software Reset
1289 #define SYSCTL_SRI2C_R1 0x00000002 // I2C Module 1 Software Reset
1290 #define SYSCTL_SRI2C_R0 0x00000001 // I2C Module 0 Software Reset
1291 
1292 //*****************************************************************************
1293 //
1294 // The following are defines for the bit fields in the SYSCTL_SRUSB register.
1295 //
1296 //*****************************************************************************
1297 #define SYSCTL_SRUSB_R0 0x00000001 // USB Module Software Reset
1298 
1299 //*****************************************************************************
1300 //
1301 // The following are defines for the bit fields in the SYSCTL_SREPHY register.
1302 //
1303 //*****************************************************************************
1304 #define SYSCTL_SREPHY_R0 0x00000001 // Ethernet PHY Module Software
1305  // Reset
1306 
1307 //*****************************************************************************
1308 //
1309 // The following are defines for the bit fields in the SYSCTL_SRCAN register.
1310 //
1311 //*****************************************************************************
1312 #define SYSCTL_SRCAN_R1 0x00000002 // CAN Module 1 Software Reset
1313 #define SYSCTL_SRCAN_R0 0x00000001 // CAN Module 0 Software Reset
1314 
1315 //*****************************************************************************
1316 //
1317 // The following are defines for the bit fields in the SYSCTL_SRADC register.
1318 //
1319 //*****************************************************************************
1320 #define SYSCTL_SRADC_R1 0x00000002 // ADC Module 1 Software Reset
1321 #define SYSCTL_SRADC_R0 0x00000001 // ADC Module 0 Software Reset
1322 
1323 //*****************************************************************************
1324 //
1325 // The following are defines for the bit fields in the SYSCTL_SRACMP register.
1326 //
1327 //*****************************************************************************
1328 #define SYSCTL_SRACMP_R0 0x00000001 // Analog Comparator Module 0
1329  // Software Reset
1330 
1331 //*****************************************************************************
1332 //
1333 // The following are defines for the bit fields in the SYSCTL_SRPWM register.
1334 //
1335 //*****************************************************************************
1336 #define SYSCTL_SRPWM_R1 0x00000002 // PWM Module 1 Software Reset
1337 #define SYSCTL_SRPWM_R0 0x00000001 // PWM Module 0 Software Reset
1338 
1339 //*****************************************************************************
1340 //
1341 // The following are defines for the bit fields in the SYSCTL_SRQEI register.
1342 //
1343 //*****************************************************************************
1344 #define SYSCTL_SRQEI_R1 0x00000002 // QEI Module 1 Software Reset
1345 #define SYSCTL_SRQEI_R0 0x00000001 // QEI Module 0 Software Reset
1346 
1347 //*****************************************************************************
1348 //
1349 // The following are defines for the bit fields in the SYSCTL_SREEPROM
1350 // register.
1351 //
1352 //*****************************************************************************
1353 #define SYSCTL_SREEPROM_R0 0x00000001 // EEPROM Module Software Reset
1354 
1355 //*****************************************************************************
1356 //
1357 // The following are defines for the bit fields in the SYSCTL_SRCCM register.
1358 //
1359 //*****************************************************************************
1360 #define SYSCTL_SRCCM_R0 0x00000001 // CRC and Cryptographic Modules
1361  // Software Reset
1362 
1363 //*****************************************************************************
1364 //
1365 // The following are defines for the bit fields in the SYSCTL_SRLCD register.
1366 //
1367 //*****************************************************************************
1368 #define SYSCTL_SRLCD_R0 0x00000001 // LCD Module 0 Software Reset
1369 
1370 //*****************************************************************************
1371 //
1372 // The following are defines for the bit fields in the SYSCTL_SROWIRE register.
1373 //
1374 //*****************************************************************************
1375 #define SYSCTL_SROWIRE_R0 0x00000001 // 1-Wire Module Software Reset
1376 
1377 //*****************************************************************************
1378 //
1379 // The following are defines for the bit fields in the SYSCTL_SREMAC register.
1380 //
1381 //*****************************************************************************
1382 #define SYSCTL_SREMAC_R0 0x00000001 // Ethernet Controller MAC Module 0
1383  // Software Reset
1384 
1385 //*****************************************************************************
1386 //
1387 // The following are defines for the bit fields in the SYSCTL_RCGCWD register.
1388 //
1389 //*****************************************************************************
1390 #define SYSCTL_RCGCWD_R1 0x00000002 // Watchdog Timer 1 Run Mode Clock
1391  // Gating Control
1392 #define SYSCTL_RCGCWD_R0 0x00000001 // Watchdog Timer 0 Run Mode Clock
1393  // Gating Control
1394 
1395 //*****************************************************************************
1396 //
1397 // The following are defines for the bit fields in the SYSCTL_RCGCTIMER
1398 // register.
1399 //
1400 //*****************************************************************************
1401 #define SYSCTL_RCGCTIMER_R7 0x00000080 // 16/32-Bit General-Purpose Timer
1402  // 7 Run Mode Clock Gating Control
1403 #define SYSCTL_RCGCTIMER_R6 0x00000040 // 16/32-Bit General-Purpose Timer
1404  // 6 Run Mode Clock Gating Control
1405 #define SYSCTL_RCGCTIMER_R5 0x00000020 // 16/32-Bit General-Purpose Timer
1406  // 5 Run Mode Clock Gating Control
1407 #define SYSCTL_RCGCTIMER_R4 0x00000010 // 16/32-Bit General-Purpose Timer
1408  // 4 Run Mode Clock Gating Control
1409 #define SYSCTL_RCGCTIMER_R3 0x00000008 // 16/32-Bit General-Purpose Timer
1410  // 3 Run Mode Clock Gating Control
1411 #define SYSCTL_RCGCTIMER_R2 0x00000004 // 16/32-Bit General-Purpose Timer
1412  // 2 Run Mode Clock Gating Control
1413 #define SYSCTL_RCGCTIMER_R1 0x00000002 // 16/32-Bit General-Purpose Timer
1414  // 1 Run Mode Clock Gating Control
1415 #define SYSCTL_RCGCTIMER_R0 0x00000001 // 16/32-Bit General-Purpose Timer
1416  // 0 Run Mode Clock Gating Control
1417 
1418 //*****************************************************************************
1419 //
1420 // The following are defines for the bit fields in the SYSCTL_RCGCGPIO
1421 // register.
1422 //
1423 //*****************************************************************************
1424 #define SYSCTL_RCGCGPIO_R17 0x00020000 // GPIO Port T Run Mode Clock
1425  // Gating Control
1426 #define SYSCTL_RCGCGPIO_R16 0x00010000 // GPIO Port S Run Mode Clock
1427  // Gating Control
1428 #define SYSCTL_RCGCGPIO_R15 0x00008000 // GPIO Port R Run Mode Clock
1429  // Gating Control
1430 #define SYSCTL_RCGCGPIO_R14 0x00004000 // GPIO Port Q Run Mode Clock
1431  // Gating Control
1432 #define SYSCTL_RCGCGPIO_R13 0x00002000 // GPIO Port P Run Mode Clock
1433  // Gating Control
1434 #define SYSCTL_RCGCGPIO_R12 0x00001000 // GPIO Port N Run Mode Clock
1435  // Gating Control
1436 #define SYSCTL_RCGCGPIO_R11 0x00000800 // GPIO Port M Run Mode Clock
1437  // Gating Control
1438 #define SYSCTL_RCGCGPIO_R10 0x00000400 // GPIO Port L Run Mode Clock
1439  // Gating Control
1440 #define SYSCTL_RCGCGPIO_R9 0x00000200 // GPIO Port K Run Mode Clock
1441  // Gating Control
1442 #define SYSCTL_RCGCGPIO_R8 0x00000100 // GPIO Port J Run Mode Clock
1443  // Gating Control
1444 #define SYSCTL_RCGCGPIO_R7 0x00000080 // GPIO Port H Run Mode Clock
1445  // Gating Control
1446 #define SYSCTL_RCGCGPIO_R6 0x00000040 // GPIO Port G Run Mode Clock
1447  // Gating Control
1448 #define SYSCTL_RCGCGPIO_R5 0x00000020 // GPIO Port F Run Mode Clock
1449  // Gating Control
1450 #define SYSCTL_RCGCGPIO_R4 0x00000010 // GPIO Port E Run Mode Clock
1451  // Gating Control
1452 #define SYSCTL_RCGCGPIO_R3 0x00000008 // GPIO Port D Run Mode Clock
1453  // Gating Control
1454 #define SYSCTL_RCGCGPIO_R2 0x00000004 // GPIO Port C Run Mode Clock
1455  // Gating Control
1456 #define SYSCTL_RCGCGPIO_R1 0x00000002 // GPIO Port B Run Mode Clock
1457  // Gating Control
1458 #define SYSCTL_RCGCGPIO_R0 0x00000001 // GPIO Port A Run Mode Clock
1459  // Gating Control
1460 
1461 //*****************************************************************************
1462 //
1463 // The following are defines for the bit fields in the SYSCTL_RCGCDMA register.
1464 //
1465 //*****************************************************************************
1466 #define SYSCTL_RCGCDMA_R0 0x00000001 // uDMA Module Run Mode Clock
1467  // Gating Control
1468 
1469 //*****************************************************************************
1470 //
1471 // The following are defines for the bit fields in the SYSCTL_RCGCEPI register.
1472 //
1473 //*****************************************************************************
1474 #define SYSCTL_RCGCEPI_R0 0x00000001 // EPI Module Run Mode Clock Gating
1475  // Control
1476 
1477 //*****************************************************************************
1478 //
1479 // The following are defines for the bit fields in the SYSCTL_RCGCHIB register.
1480 //
1481 //*****************************************************************************
1482 #define SYSCTL_RCGCHIB_R0 0x00000001 // Hibernation Module Run Mode
1483  // Clock Gating Control
1484 
1485 //*****************************************************************************
1486 //
1487 // The following are defines for the bit fields in the SYSCTL_RCGCUART
1488 // register.
1489 //
1490 //*****************************************************************************
1491 #define SYSCTL_RCGCUART_R7 0x00000080 // UART Module 7 Run Mode Clock
1492  // Gating Control
1493 #define SYSCTL_RCGCUART_R6 0x00000040 // UART Module 6 Run Mode Clock
1494  // Gating Control
1495 #define SYSCTL_RCGCUART_R5 0x00000020 // UART Module 5 Run Mode Clock
1496  // Gating Control
1497 #define SYSCTL_RCGCUART_R4 0x00000010 // UART Module 4 Run Mode Clock
1498  // Gating Control
1499 #define SYSCTL_RCGCUART_R3 0x00000008 // UART Module 3 Run Mode Clock
1500  // Gating Control
1501 #define SYSCTL_RCGCUART_R2 0x00000004 // UART Module 2 Run Mode Clock
1502  // Gating Control
1503 #define SYSCTL_RCGCUART_R1 0x00000002 // UART Module 1 Run Mode Clock
1504  // Gating Control
1505 #define SYSCTL_RCGCUART_R0 0x00000001 // UART Module 0 Run Mode Clock
1506  // Gating Control
1507 
1508 //*****************************************************************************
1509 //
1510 // The following are defines for the bit fields in the SYSCTL_RCGCSSI register.
1511 //
1512 //*****************************************************************************
1513 #define SYSCTL_RCGCSSI_R3 0x00000008 // SSI Module 3 Run Mode Clock
1514  // Gating Control
1515 #define SYSCTL_RCGCSSI_R2 0x00000004 // SSI Module 2 Run Mode Clock
1516  // Gating Control
1517 #define SYSCTL_RCGCSSI_R1 0x00000002 // SSI Module 1 Run Mode Clock
1518  // Gating Control
1519 #define SYSCTL_RCGCSSI_R0 0x00000001 // SSI Module 0 Run Mode Clock
1520  // Gating Control
1521 
1522 //*****************************************************************************
1523 //
1524 // The following are defines for the bit fields in the SYSCTL_RCGCI2C register.
1525 //
1526 //*****************************************************************************
1527 #define SYSCTL_RCGCI2C_R9 0x00000200 // I2C Module 9 Run Mode Clock
1528  // Gating Control
1529 #define SYSCTL_RCGCI2C_R8 0x00000100 // I2C Module 8 Run Mode Clock
1530  // Gating Control
1531 #define SYSCTL_RCGCI2C_R7 0x00000080 // I2C Module 7 Run Mode Clock
1532  // Gating Control
1533 #define SYSCTL_RCGCI2C_R6 0x00000040 // I2C Module 6 Run Mode Clock
1534  // Gating Control
1535 #define SYSCTL_RCGCI2C_R5 0x00000020 // I2C Module 5 Run Mode Clock
1536  // Gating Control
1537 #define SYSCTL_RCGCI2C_R4 0x00000010 // I2C Module 4 Run Mode Clock
1538  // Gating Control
1539 #define SYSCTL_RCGCI2C_R3 0x00000008 // I2C Module 3 Run Mode Clock
1540  // Gating Control
1541 #define SYSCTL_RCGCI2C_R2 0x00000004 // I2C Module 2 Run Mode Clock
1542  // Gating Control
1543 #define SYSCTL_RCGCI2C_R1 0x00000002 // I2C Module 1 Run Mode Clock
1544  // Gating Control
1545 #define SYSCTL_RCGCI2C_R0 0x00000001 // I2C Module 0 Run Mode Clock
1546  // Gating Control
1547 
1548 //*****************************************************************************
1549 //
1550 // The following are defines for the bit fields in the SYSCTL_RCGCUSB register.
1551 //
1552 //*****************************************************************************
1553 #define SYSCTL_RCGCUSB_R0 0x00000001 // USB Module Run Mode Clock Gating
1554  // Control
1555 
1556 //*****************************************************************************
1557 //
1558 // The following are defines for the bit fields in the SYSCTL_RCGCEPHY
1559 // register.
1560 //
1561 //*****************************************************************************
1562 #define SYSCTL_RCGCEPHY_R0 0x00000001 // Ethernet PHY Module Run Mode
1563  // Clock Gating Control
1564 
1565 //*****************************************************************************
1566 //
1567 // The following are defines for the bit fields in the SYSCTL_RCGCCAN register.
1568 //
1569 //*****************************************************************************
1570 #define SYSCTL_RCGCCAN_R1 0x00000002 // CAN Module 1 Run Mode Clock
1571  // Gating Control
1572 #define SYSCTL_RCGCCAN_R0 0x00000001 // CAN Module 0 Run Mode Clock
1573  // Gating Control
1574 
1575 //*****************************************************************************
1576 //
1577 // The following are defines for the bit fields in the SYSCTL_RCGCADC register.
1578 //
1579 //*****************************************************************************
1580 #define SYSCTL_RCGCADC_R1 0x00000002 // ADC Module 1 Run Mode Clock
1581  // Gating Control
1582 #define SYSCTL_RCGCADC_R0 0x00000001 // ADC Module 0 Run Mode Clock
1583  // Gating Control
1584 
1585 //*****************************************************************************
1586 //
1587 // The following are defines for the bit fields in the SYSCTL_RCGCACMP
1588 // register.
1589 //
1590 //*****************************************************************************
1591 #define SYSCTL_RCGCACMP_R0 0x00000001 // Analog Comparator Module 0 Run
1592  // Mode Clock Gating Control
1593 
1594 //*****************************************************************************
1595 //
1596 // The following are defines for the bit fields in the SYSCTL_RCGCPWM register.
1597 //
1598 //*****************************************************************************
1599 #define SYSCTL_RCGCPWM_R1 0x00000002 // PWM Module 1 Run Mode Clock
1600  // Gating Control
1601 #define SYSCTL_RCGCPWM_R0 0x00000001 // PWM Module 0 Run Mode Clock
1602  // Gating Control
1603 
1604 //*****************************************************************************
1605 //
1606 // The following are defines for the bit fields in the SYSCTL_RCGCQEI register.
1607 //
1608 //*****************************************************************************
1609 #define SYSCTL_RCGCQEI_R1 0x00000002 // QEI Module 1 Run Mode Clock
1610  // Gating Control
1611 #define SYSCTL_RCGCQEI_R0 0x00000001 // QEI Module 0 Run Mode Clock
1612  // Gating Control
1613 
1614 //*****************************************************************************
1615 //
1616 // The following are defines for the bit fields in the SYSCTL_RCGCEEPROM
1617 // register.
1618 //
1619 //*****************************************************************************
1620 #define SYSCTL_RCGCEEPROM_R0 0x00000001 // EEPROM Module Run Mode Clock
1621  // Gating Control
1622 
1623 //*****************************************************************************
1624 //
1625 // The following are defines for the bit fields in the SYSCTL_RCGCCCM register.
1626 //
1627 //*****************************************************************************
1628 #define SYSCTL_RCGCCCM_R0 0x00000001 // CRC and Cryptographic Modules
1629  // Run Mode Clock Gating Control
1630 
1631 //*****************************************************************************
1632 //
1633 // The following are defines for the bit fields in the SYSCTL_RCGCLCD register.
1634 //
1635 //*****************************************************************************
1636 #define SYSCTL_RCGCLCD_R0 0x00000001 // LCD Controller Module 0 Run Mode
1637  // Clock Gating Control
1638 
1639 //*****************************************************************************
1640 //
1641 // The following are defines for the bit fields in the SYSCTL_RCGCOWIRE
1642 // register.
1643 //
1644 //*****************************************************************************
1645 #define SYSCTL_RCGCOWIRE_R0 0x00000001 // 1-Wire Module 0 Run Mode Clock
1646  // Gating Control
1647 
1648 //*****************************************************************************
1649 //
1650 // The following are defines for the bit fields in the SYSCTL_RCGCEMAC
1651 // register.
1652 //
1653 //*****************************************************************************
1654 #define SYSCTL_RCGCEMAC_R0 0x00000001 // Ethernet MAC Module 0 Run Mode
1655  // Clock Gating Control
1656 
1657 //*****************************************************************************
1658 //
1659 // The following are defines for the bit fields in the SYSCTL_SCGCWD register.
1660 //
1661 //*****************************************************************************
1662 #define SYSCTL_SCGCWD_S1 0x00000002 // Watchdog Timer 1 Sleep Mode
1663  // Clock Gating Control
1664 #define SYSCTL_SCGCWD_S0 0x00000001 // Watchdog Timer 0 Sleep Mode
1665  // Clock Gating Control
1666 
1667 //*****************************************************************************
1668 //
1669 // The following are defines for the bit fields in the SYSCTL_SCGCTIMER
1670 // register.
1671 //
1672 //*****************************************************************************
1673 #define SYSCTL_SCGCTIMER_S7 0x00000080 // 16/32-Bit General-Purpose Timer
1674  // 7 Sleep Mode Clock Gating
1675  // Control
1676 #define SYSCTL_SCGCTIMER_S6 0x00000040 // 16/32-Bit General-Purpose Timer
1677  // 6 Sleep Mode Clock Gating
1678  // Control
1679 #define SYSCTL_SCGCTIMER_S5 0x00000020 // 16/32-Bit General-Purpose Timer
1680  // 5 Sleep Mode Clock Gating
1681  // Control
1682 #define SYSCTL_SCGCTIMER_S4 0x00000010 // 16/32-Bit General-Purpose Timer
1683  // 4 Sleep Mode Clock Gating
1684  // Control
1685 #define SYSCTL_SCGCTIMER_S3 0x00000008 // 16/32-Bit General-Purpose Timer
1686  // 3 Sleep Mode Clock Gating
1687  // Control
1688 #define SYSCTL_SCGCTIMER_S2 0x00000004 // 16/32-Bit General-Purpose Timer
1689  // 2 Sleep Mode Clock Gating
1690  // Control
1691 #define SYSCTL_SCGCTIMER_S1 0x00000002 // 16/32-Bit General-Purpose Timer
1692  // 1 Sleep Mode Clock Gating
1693  // Control
1694 #define SYSCTL_SCGCTIMER_S0 0x00000001 // 16/32-Bit General-Purpose Timer
1695  // 0 Sleep Mode Clock Gating
1696  // Control
1697 
1698 //*****************************************************************************
1699 //
1700 // The following are defines for the bit fields in the SYSCTL_SCGCGPIO
1701 // register.
1702 //
1703 //*****************************************************************************
1704 #define SYSCTL_SCGCGPIO_S17 0x00020000 // GPIO Port T Sleep Mode Clock
1705  // Gating Control
1706 #define SYSCTL_SCGCGPIO_S16 0x00010000 // GPIO Port S Sleep Mode Clock
1707  // Gating Control
1708 #define SYSCTL_SCGCGPIO_S15 0x00008000 // GPIO Port R Sleep Mode Clock
1709  // Gating Control
1710 #define SYSCTL_SCGCGPIO_S14 0x00004000 // GPIO Port Q Sleep Mode Clock
1711  // Gating Control
1712 #define SYSCTL_SCGCGPIO_S13 0x00002000 // GPIO Port P Sleep Mode Clock
1713  // Gating Control
1714 #define SYSCTL_SCGCGPIO_S12 0x00001000 // GPIO Port N Sleep Mode Clock
1715  // Gating Control
1716 #define SYSCTL_SCGCGPIO_S11 0x00000800 // GPIO Port M Sleep Mode Clock
1717  // Gating Control
1718 #define SYSCTL_SCGCGPIO_S10 0x00000400 // GPIO Port L Sleep Mode Clock
1719  // Gating Control
1720 #define SYSCTL_SCGCGPIO_S9 0x00000200 // GPIO Port K Sleep Mode Clock
1721  // Gating Control
1722 #define SYSCTL_SCGCGPIO_S8 0x00000100 // GPIO Port J Sleep Mode Clock
1723  // Gating Control
1724 #define SYSCTL_SCGCGPIO_S7 0x00000080 // GPIO Port H Sleep Mode Clock
1725  // Gating Control
1726 #define SYSCTL_SCGCGPIO_S6 0x00000040 // GPIO Port G Sleep Mode Clock
1727  // Gating Control
1728 #define SYSCTL_SCGCGPIO_S5 0x00000020 // GPIO Port F Sleep Mode Clock
1729  // Gating Control
1730 #define SYSCTL_SCGCGPIO_S4 0x00000010 // GPIO Port E Sleep Mode Clock
1731  // Gating Control
1732 #define SYSCTL_SCGCGPIO_S3 0x00000008 // GPIO Port D Sleep Mode Clock
1733  // Gating Control
1734 #define SYSCTL_SCGCGPIO_S2 0x00000004 // GPIO Port C Sleep Mode Clock
1735  // Gating Control
1736 #define SYSCTL_SCGCGPIO_S1 0x00000002 // GPIO Port B Sleep Mode Clock
1737  // Gating Control
1738 #define SYSCTL_SCGCGPIO_S0 0x00000001 // GPIO Port A Sleep Mode Clock
1739  // Gating Control
1740 
1741 //*****************************************************************************
1742 //
1743 // The following are defines for the bit fields in the SYSCTL_SCGCDMA register.
1744 //
1745 //*****************************************************************************
1746 #define SYSCTL_SCGCDMA_S0 0x00000001 // uDMA Module Sleep Mode Clock
1747  // Gating Control
1748 
1749 //*****************************************************************************
1750 //
1751 // The following are defines for the bit fields in the SYSCTL_SCGCEPI register.
1752 //
1753 //*****************************************************************************
1754 #define SYSCTL_SCGCEPI_S0 0x00000001 // EPI Module Sleep Mode Clock
1755  // Gating Control
1756 
1757 //*****************************************************************************
1758 //
1759 // The following are defines for the bit fields in the SYSCTL_SCGCHIB register.
1760 //
1761 //*****************************************************************************
1762 #define SYSCTL_SCGCHIB_S0 0x00000001 // Hibernation Module Sleep Mode
1763  // Clock Gating Control
1764 
1765 //*****************************************************************************
1766 //
1767 // The following are defines for the bit fields in the SYSCTL_SCGCUART
1768 // register.
1769 //
1770 //*****************************************************************************
1771 #define SYSCTL_SCGCUART_S7 0x00000080 // UART Module 7 Sleep Mode Clock
1772  // Gating Control
1773 #define SYSCTL_SCGCUART_S6 0x00000040 // UART Module 6 Sleep Mode Clock
1774  // Gating Control
1775 #define SYSCTL_SCGCUART_S5 0x00000020 // UART Module 5 Sleep Mode Clock
1776  // Gating Control
1777 #define SYSCTL_SCGCUART_S4 0x00000010 // UART Module 4 Sleep Mode Clock
1778  // Gating Control
1779 #define SYSCTL_SCGCUART_S3 0x00000008 // UART Module 3 Sleep Mode Clock
1780  // Gating Control
1781 #define SYSCTL_SCGCUART_S2 0x00000004 // UART Module 2 Sleep Mode Clock
1782  // Gating Control
1783 #define SYSCTL_SCGCUART_S1 0x00000002 // UART Module 1 Sleep Mode Clock
1784  // Gating Control
1785 #define SYSCTL_SCGCUART_S0 0x00000001 // UART Module 0 Sleep Mode Clock
1786  // Gating Control
1787 
1788 //*****************************************************************************
1789 //
1790 // The following are defines for the bit fields in the SYSCTL_SCGCSSI register.
1791 //
1792 //*****************************************************************************
1793 #define SYSCTL_SCGCSSI_S3 0x00000008 // SSI Module 3 Sleep Mode Clock
1794  // Gating Control
1795 #define SYSCTL_SCGCSSI_S2 0x00000004 // SSI Module 2 Sleep Mode Clock
1796  // Gating Control
1797 #define SYSCTL_SCGCSSI_S1 0x00000002 // SSI Module 1 Sleep Mode Clock
1798  // Gating Control
1799 #define SYSCTL_SCGCSSI_S0 0x00000001 // SSI Module 0 Sleep Mode Clock
1800  // Gating Control
1801 
1802 //*****************************************************************************
1803 //
1804 // The following are defines for the bit fields in the SYSCTL_SCGCI2C register.
1805 //
1806 //*****************************************************************************
1807 #define SYSCTL_SCGCI2C_S9 0x00000200 // I2C Module 9 Sleep Mode Clock
1808  // Gating Control
1809 #define SYSCTL_SCGCI2C_S8 0x00000100 // I2C Module 8 Sleep Mode Clock
1810  // Gating Control
1811 #define SYSCTL_SCGCI2C_S7 0x00000080 // I2C Module 7 Sleep Mode Clock
1812  // Gating Control
1813 #define SYSCTL_SCGCI2C_S6 0x00000040 // I2C Module 6 Sleep Mode Clock
1814  // Gating Control
1815 #define SYSCTL_SCGCI2C_S5 0x00000020 // I2C Module 5 Sleep Mode Clock
1816  // Gating Control
1817 #define SYSCTL_SCGCI2C_S4 0x00000010 // I2C Module 4 Sleep Mode Clock
1818  // Gating Control
1819 #define SYSCTL_SCGCI2C_S3 0x00000008 // I2C Module 3 Sleep Mode Clock
1820  // Gating Control
1821 #define SYSCTL_SCGCI2C_S2 0x00000004 // I2C Module 2 Sleep Mode Clock
1822  // Gating Control
1823 #define SYSCTL_SCGCI2C_S1 0x00000002 // I2C Module 1 Sleep Mode Clock
1824  // Gating Control
1825 #define SYSCTL_SCGCI2C_S0 0x00000001 // I2C Module 0 Sleep Mode Clock
1826  // Gating Control
1827 
1828 //*****************************************************************************
1829 //
1830 // The following are defines for the bit fields in the SYSCTL_SCGCUSB register.
1831 //
1832 //*****************************************************************************
1833 #define SYSCTL_SCGCUSB_S0 0x00000001 // USB Module Sleep Mode Clock
1834  // Gating Control
1835 
1836 //*****************************************************************************
1837 //
1838 // The following are defines for the bit fields in the SYSCTL_SCGCEPHY
1839 // register.
1840 //
1841 //*****************************************************************************
1842 #define SYSCTL_SCGCEPHY_S0 0x00000001 // PHY Module Sleep Mode Clock
1843  // Gating Control
1844 
1845 //*****************************************************************************
1846 //
1847 // The following are defines for the bit fields in the SYSCTL_SCGCCAN register.
1848 //
1849 //*****************************************************************************
1850 #define SYSCTL_SCGCCAN_S1 0x00000002 // CAN Module 1 Sleep Mode Clock
1851  // Gating Control
1852 #define SYSCTL_SCGCCAN_S0 0x00000001 // CAN Module 0 Sleep Mode Clock
1853  // Gating Control
1854 
1855 //*****************************************************************************
1856 //
1857 // The following are defines for the bit fields in the SYSCTL_SCGCADC register.
1858 //
1859 //*****************************************************************************
1860 #define SYSCTL_SCGCADC_S1 0x00000002 // ADC Module 1 Sleep Mode Clock
1861  // Gating Control
1862 #define SYSCTL_SCGCADC_S0 0x00000001 // ADC Module 0 Sleep Mode Clock
1863  // Gating Control
1864 
1865 //*****************************************************************************
1866 //
1867 // The following are defines for the bit fields in the SYSCTL_SCGCACMP
1868 // register.
1869 //
1870 //*****************************************************************************
1871 #define SYSCTL_SCGCACMP_S0 0x00000001 // Analog Comparator Module 0 Sleep
1872  // Mode Clock Gating Control
1873 
1874 //*****************************************************************************
1875 //
1876 // The following are defines for the bit fields in the SYSCTL_SCGCPWM register.
1877 //
1878 //*****************************************************************************
1879 #define SYSCTL_SCGCPWM_S1 0x00000002 // PWM Module 1 Sleep Mode Clock
1880  // Gating Control
1881 #define SYSCTL_SCGCPWM_S0 0x00000001 // PWM Module 0 Sleep Mode Clock
1882  // Gating Control
1883 
1884 //*****************************************************************************
1885 //
1886 // The following are defines for the bit fields in the SYSCTL_SCGCQEI register.
1887 //
1888 //*****************************************************************************
1889 #define SYSCTL_SCGCQEI_S1 0x00000002 // QEI Module 1 Sleep Mode Clock
1890  // Gating Control
1891 #define SYSCTL_SCGCQEI_S0 0x00000001 // QEI Module 0 Sleep Mode Clock
1892  // Gating Control
1893 
1894 //*****************************************************************************
1895 //
1896 // The following are defines for the bit fields in the SYSCTL_SCGCEEPROM
1897 // register.
1898 //
1899 //*****************************************************************************
1900 #define SYSCTL_SCGCEEPROM_S0 0x00000001 // EEPROM Module Sleep Mode Clock
1901  // Gating Control
1902 
1903 //*****************************************************************************
1904 //
1905 // The following are defines for the bit fields in the SYSCTL_SCGCCCM register.
1906 //
1907 //*****************************************************************************
1908 #define SYSCTL_SCGCCCM_S0 0x00000001 // CRC and Cryptographic Modules
1909  // Sleep Mode Clock Gating Control
1910 
1911 //*****************************************************************************
1912 //
1913 // The following are defines for the bit fields in the SYSCTL_SCGCLCD register.
1914 //
1915 //*****************************************************************************
1916 #define SYSCTL_SCGCLCD_S0 0x00000001 // LCD Controller Module 0 Sleep
1917  // Mode Clock Gating Control
1918 
1919 //*****************************************************************************
1920 //
1921 // The following are defines for the bit fields in the SYSCTL_SCGCOWIRE
1922 // register.
1923 //
1924 //*****************************************************************************
1925 #define SYSCTL_SCGCOWIRE_S0 0x00000001 // 1-Wire Module 0 Sleep Mode Clock
1926  // Gating Control
1927 
1928 //*****************************************************************************
1929 //
1930 // The following are defines for the bit fields in the SYSCTL_SCGCEMAC
1931 // register.
1932 //
1933 //*****************************************************************************
1934 #define SYSCTL_SCGCEMAC_S0 0x00000001 // Ethernet MAC Module 0 Sleep Mode
1935  // Clock Gating Control
1936 
1937 //*****************************************************************************
1938 //
1939 // The following are defines for the bit fields in the SYSCTL_DCGCWD register.
1940 //
1941 //*****************************************************************************
1942 #define SYSCTL_DCGCWD_D1 0x00000002 // Watchdog Timer 1 Deep-Sleep Mode
1943  // Clock Gating Control
1944 #define SYSCTL_DCGCWD_D0 0x00000001 // Watchdog Timer 0 Deep-Sleep Mode
1945  // Clock Gating Control
1946 
1947 //*****************************************************************************
1948 //
1949 // The following are defines for the bit fields in the SYSCTL_DCGCTIMER
1950 // register.
1951 //
1952 //*****************************************************************************
1953 #define SYSCTL_DCGCTIMER_D7 0x00000080 // 16/32-Bit General-Purpose Timer
1954  // 7 Deep-Sleep Mode Clock Gating
1955  // Control
1956 #define SYSCTL_DCGCTIMER_D6 0x00000040 // 16/32-Bit General-Purpose Timer
1957  // 6 Deep-Sleep Mode Clock Gating
1958  // Control
1959 #define SYSCTL_DCGCTIMER_D5 0x00000020 // 16/32-Bit General-Purpose Timer
1960  // 5 Deep-Sleep Mode Clock Gating
1961  // Control
1962 #define SYSCTL_DCGCTIMER_D4 0x00000010 // 16/32-Bit General-Purpose Timer
1963  // 4 Deep-Sleep Mode Clock Gating
1964  // Control
1965 #define SYSCTL_DCGCTIMER_D3 0x00000008 // 16/32-Bit General-Purpose Timer
1966  // 3 Deep-Sleep Mode Clock Gating
1967  // Control
1968 #define SYSCTL_DCGCTIMER_D2 0x00000004 // 16/32-Bit General-Purpose Timer
1969  // 2 Deep-Sleep Mode Clock Gating
1970  // Control
1971 #define SYSCTL_DCGCTIMER_D1 0x00000002 // 16/32-Bit General-Purpose Timer
1972  // 1 Deep-Sleep Mode Clock Gating
1973  // Control
1974 #define SYSCTL_DCGCTIMER_D0 0x00000001 // 16/32-Bit General-Purpose Timer
1975  // 0 Deep-Sleep Mode Clock Gating
1976  // Control
1977 
1978 //*****************************************************************************
1979 //
1980 // The following are defines for the bit fields in the SYSCTL_DCGCGPIO
1981 // register.
1982 //
1983 //*****************************************************************************
1984 #define SYSCTL_DCGCGPIO_D17 0x00020000 // GPIO Port T Deep-Sleep Mode
1985  // Clock Gating Control
1986 #define SYSCTL_DCGCGPIO_D16 0x00010000 // GPIO Port S Deep-Sleep Mode
1987  // Clock Gating Control
1988 #define SYSCTL_DCGCGPIO_D15 0x00008000 // GPIO Port R Deep-Sleep Mode
1989  // Clock Gating Control
1990 #define SYSCTL_DCGCGPIO_D14 0x00004000 // GPIO Port Q Deep-Sleep Mode
1991  // Clock Gating Control
1992 #define SYSCTL_DCGCGPIO_D13 0x00002000 // GPIO Port P Deep-Sleep Mode
1993  // Clock Gating Control
1994 #define SYSCTL_DCGCGPIO_D12 0x00001000 // GPIO Port N Deep-Sleep Mode
1995  // Clock Gating Control
1996 #define SYSCTL_DCGCGPIO_D11 0x00000800 // GPIO Port M Deep-Sleep Mode
1997  // Clock Gating Control
1998 #define SYSCTL_DCGCGPIO_D10 0x00000400 // GPIO Port L Deep-Sleep Mode
1999  // Clock Gating Control
2000 #define SYSCTL_DCGCGPIO_D9 0x00000200 // GPIO Port K Deep-Sleep Mode
2001  // Clock Gating Control
2002 #define SYSCTL_DCGCGPIO_D8 0x00000100 // GPIO Port J Deep-Sleep Mode
2003  // Clock Gating Control
2004 #define SYSCTL_DCGCGPIO_D7 0x00000080 // GPIO Port H Deep-Sleep Mode
2005  // Clock Gating Control
2006 #define SYSCTL_DCGCGPIO_D6 0x00000040 // GPIO Port G Deep-Sleep Mode
2007  // Clock Gating Control
2008 #define SYSCTL_DCGCGPIO_D5 0x00000020 // GPIO Port F Deep-Sleep Mode
2009  // Clock Gating Control
2010 #define SYSCTL_DCGCGPIO_D4 0x00000010 // GPIO Port E Deep-Sleep Mode
2011  // Clock Gating Control
2012 #define SYSCTL_DCGCGPIO_D3 0x00000008 // GPIO Port D Deep-Sleep Mode
2013  // Clock Gating Control
2014 #define SYSCTL_DCGCGPIO_D2 0x00000004 // GPIO Port C Deep-Sleep Mode
2015  // Clock Gating Control
2016 #define SYSCTL_DCGCGPIO_D1 0x00000002 // GPIO Port B Deep-Sleep Mode
2017  // Clock Gating Control
2018 #define SYSCTL_DCGCGPIO_D0 0x00000001 // GPIO Port A Deep-Sleep Mode
2019  // Clock Gating Control
2020 
2021 //*****************************************************************************
2022 //
2023 // The following are defines for the bit fields in the SYSCTL_DCGCDMA register.
2024 //
2025 //*****************************************************************************
2026 #define SYSCTL_DCGCDMA_D0 0x00000001 // uDMA Module Deep-Sleep Mode
2027  // Clock Gating Control
2028 
2029 //*****************************************************************************
2030 //
2031 // The following are defines for the bit fields in the SYSCTL_DCGCEPI register.
2032 //
2033 //*****************************************************************************
2034 #define SYSCTL_DCGCEPI_D0 0x00000001 // EPI Module Deep-Sleep Mode Clock
2035  // Gating Control
2036 
2037 //*****************************************************************************
2038 //
2039 // The following are defines for the bit fields in the SYSCTL_DCGCHIB register.
2040 //
2041 //*****************************************************************************
2042 #define SYSCTL_DCGCHIB_D0 0x00000001 // Hibernation Module Deep-Sleep
2043  // Mode Clock Gating Control
2044 
2045 //*****************************************************************************
2046 //
2047 // The following are defines for the bit fields in the SYSCTL_DCGCUART
2048 // register.
2049 //
2050 //*****************************************************************************
2051 #define SYSCTL_DCGCUART_D7 0x00000080 // UART Module 7 Deep-Sleep Mode
2052  // Clock Gating Control
2053 #define SYSCTL_DCGCUART_D6 0x00000040 // UART Module 6 Deep-Sleep Mode
2054  // Clock Gating Control
2055 #define SYSCTL_DCGCUART_D5 0x00000020 // UART Module 5 Deep-Sleep Mode
2056  // Clock Gating Control
2057 #define SYSCTL_DCGCUART_D4 0x00000010 // UART Module 4 Deep-Sleep Mode
2058  // Clock Gating Control
2059 #define SYSCTL_DCGCUART_D3 0x00000008 // UART Module 3 Deep-Sleep Mode
2060  // Clock Gating Control
2061 #define SYSCTL_DCGCUART_D2 0x00000004 // UART Module 2 Deep-Sleep Mode
2062  // Clock Gating Control
2063 #define SYSCTL_DCGCUART_D1 0x00000002 // UART Module 1 Deep-Sleep Mode
2064  // Clock Gating Control
2065 #define SYSCTL_DCGCUART_D0 0x00000001 // UART Module 0 Deep-Sleep Mode
2066  // Clock Gating Control
2067 
2068 //*****************************************************************************
2069 //
2070 // The following are defines for the bit fields in the SYSCTL_DCGCSSI register.
2071 //
2072 //*****************************************************************************
2073 #define SYSCTL_DCGCSSI_D3 0x00000008 // SSI Module 3 Deep-Sleep Mode
2074  // Clock Gating Control
2075 #define SYSCTL_DCGCSSI_D2 0x00000004 // SSI Module 2 Deep-Sleep Mode
2076  // Clock Gating Control
2077 #define SYSCTL_DCGCSSI_D1 0x00000002 // SSI Module 1 Deep-Sleep Mode
2078  // Clock Gating Control
2079 #define SYSCTL_DCGCSSI_D0 0x00000001 // SSI Module 0 Deep-Sleep Mode
2080  // Clock Gating Control
2081 
2082 //*****************************************************************************
2083 //
2084 // The following are defines for the bit fields in the SYSCTL_DCGCI2C register.
2085 //
2086 //*****************************************************************************
2087 #define SYSCTL_DCGCI2C_D9 0x00000200 // I2C Module 9 Deep-Sleep Mode
2088  // Clock Gating Control
2089 #define SYSCTL_DCGCI2C_D8 0x00000100 // I2C Module 8 Deep-Sleep Mode
2090  // Clock Gating Control
2091 #define SYSCTL_DCGCI2C_D7 0x00000080 // I2C Module 7 Deep-Sleep Mode
2092  // Clock Gating Control
2093 #define SYSCTL_DCGCI2C_D6 0x00000040 // I2C Module 6 Deep-Sleep Mode
2094  // Clock Gating Control
2095 #define SYSCTL_DCGCI2C_D5 0x00000020 // I2C Module 5 Deep-Sleep Mode
2096  // Clock Gating Control
2097 #define SYSCTL_DCGCI2C_D4 0x00000010 // I2C Module 4 Deep-Sleep Mode
2098  // Clock Gating Control
2099 #define SYSCTL_DCGCI2C_D3 0x00000008 // I2C Module 3 Deep-Sleep Mode
2100  // Clock Gating Control
2101 #define SYSCTL_DCGCI2C_D2 0x00000004 // I2C Module 2 Deep-Sleep Mode
2102  // Clock Gating Control
2103 #define SYSCTL_DCGCI2C_D1 0x00000002 // I2C Module 1 Deep-Sleep Mode
2104  // Clock Gating Control
2105 #define SYSCTL_DCGCI2C_D0 0x00000001 // I2C Module 0 Deep-Sleep Mode
2106  // Clock Gating Control
2107 
2108 //*****************************************************************************
2109 //
2110 // The following are defines for the bit fields in the SYSCTL_DCGCUSB register.
2111 //
2112 //*****************************************************************************
2113 #define SYSCTL_DCGCUSB_D0 0x00000001 // USB Module Deep-Sleep Mode Clock
2114  // Gating Control
2115 
2116 //*****************************************************************************
2117 //
2118 // The following are defines for the bit fields in the SYSCTL_DCGCEPHY
2119 // register.
2120 //
2121 //*****************************************************************************
2122 #define SYSCTL_DCGCEPHY_D0 0x00000001 // PHY Module Deep-Sleep Mode Clock
2123  // Gating Control
2124 
2125 //*****************************************************************************
2126 //
2127 // The following are defines for the bit fields in the SYSCTL_DCGCCAN register.
2128 //
2129 //*****************************************************************************
2130 #define SYSCTL_DCGCCAN_D1 0x00000002 // CAN Module 1 Deep-Sleep Mode
2131  // Clock Gating Control
2132 #define SYSCTL_DCGCCAN_D0 0x00000001 // CAN Module 0 Deep-Sleep Mode
2133  // Clock Gating Control
2134 
2135 //*****************************************************************************
2136 //
2137 // The following are defines for the bit fields in the SYSCTL_DCGCADC register.
2138 //
2139 //*****************************************************************************
2140 #define SYSCTL_DCGCADC_D1 0x00000002 // ADC Module 1 Deep-Sleep Mode
2141  // Clock Gating Control
2142 #define SYSCTL_DCGCADC_D0 0x00000001 // ADC Module 0 Deep-Sleep Mode
2143  // Clock Gating Control
2144 
2145 //*****************************************************************************
2146 //
2147 // The following are defines for the bit fields in the SYSCTL_DCGCACMP
2148 // register.
2149 //
2150 //*****************************************************************************
2151 #define SYSCTL_DCGCACMP_D0 0x00000001 // Analog Comparator Module 0
2152  // Deep-Sleep Mode Clock Gating
2153  // Control
2154 
2155 //*****************************************************************************
2156 //
2157 // The following are defines for the bit fields in the SYSCTL_DCGCPWM register.
2158 //
2159 //*****************************************************************************
2160 #define SYSCTL_DCGCPWM_D1 0x00000002 // PWM Module 1 Deep-Sleep Mode
2161  // Clock Gating Control
2162 #define SYSCTL_DCGCPWM_D0 0x00000001 // PWM Module 0 Deep-Sleep Mode
2163  // Clock Gating Control
2164 
2165 //*****************************************************************************
2166 //
2167 // The following are defines for the bit fields in the SYSCTL_DCGCQEI register.
2168 //
2169 //*****************************************************************************
2170 #define SYSCTL_DCGCQEI_D1 0x00000002 // QEI Module 1 Deep-Sleep Mode
2171  // Clock Gating Control
2172 #define SYSCTL_DCGCQEI_D0 0x00000001 // QEI Module 0 Deep-Sleep Mode
2173  // Clock Gating Control
2174 
2175 //*****************************************************************************
2176 //
2177 // The following are defines for the bit fields in the SYSCTL_DCGCEEPROM
2178 // register.
2179 //
2180 //*****************************************************************************
2181 #define SYSCTL_DCGCEEPROM_D0 0x00000001 // EEPROM Module Deep-Sleep Mode
2182  // Clock Gating Control
2183 
2184 //*****************************************************************************
2185 //
2186 // The following are defines for the bit fields in the SYSCTL_DCGCCCM register.
2187 //
2188 //*****************************************************************************
2189 #define SYSCTL_DCGCCCM_D0 0x00000001 // CRC and Cryptographic Modules
2190  // Deep-Sleep Mode Clock Gating
2191  // Control
2192 
2193 //*****************************************************************************
2194 //
2195 // The following are defines for the bit fields in the SYSCTL_DCGCLCD register.
2196 //
2197 //*****************************************************************************
2198 #define SYSCTL_DCGCLCD_D0 0x00000001 // LCD Controller Module 0
2199  // Deep-Sleep Mode Clock Gating
2200  // Control
2201 
2202 //*****************************************************************************
2203 //
2204 // The following are defines for the bit fields in the SYSCTL_DCGCOWIRE
2205 // register.
2206 //
2207 //*****************************************************************************
2208 #define SYSCTL_DCGCOWIRE_D0 0x00000001 // 1-Wire Module 0 Deep-Sleep Mode
2209  // Clock Gating Control
2210 
2211 //*****************************************************************************
2212 //
2213 // The following are defines for the bit fields in the SYSCTL_DCGCEMAC
2214 // register.
2215 //
2216 //*****************************************************************************
2217 #define SYSCTL_DCGCEMAC_D0 0x00000001 // Ethernet MAC Module 0 Deep-Sleep
2218  // Mode Clock Gating Control
2219 
2220 //*****************************************************************************
2221 //
2222 // The following are defines for the bit fields in the SYSCTL_PCWD register.
2223 //
2224 //*****************************************************************************
2225 #define SYSCTL_PCWD_P1 0x00000002 // Watchdog Timer 1 Power Control
2226 #define SYSCTL_PCWD_P0 0x00000001 // Watchdog Timer 0 Power Control
2227 
2228 //*****************************************************************************
2229 //
2230 // The following are defines for the bit fields in the SYSCTL_PCTIMER register.
2231 //
2232 //*****************************************************************************
2233 #define SYSCTL_PCTIMER_P7 0x00000080 // General-Purpose Timer 7 Power
2234  // Control
2235 #define SYSCTL_PCTIMER_P6 0x00000040 // General-Purpose Timer 6 Power
2236  // Control
2237 #define SYSCTL_PCTIMER_P5 0x00000020 // General-Purpose Timer 5 Power
2238  // Control
2239 #define SYSCTL_PCTIMER_P4 0x00000010 // General-Purpose Timer 4 Power
2240  // Control
2241 #define SYSCTL_PCTIMER_P3 0x00000008 // General-Purpose Timer 3 Power
2242  // Control
2243 #define SYSCTL_PCTIMER_P2 0x00000004 // General-Purpose Timer 2 Power
2244  // Control
2245 #define SYSCTL_PCTIMER_P1 0x00000002 // General-Purpose Timer 1 Power
2246  // Control
2247 #define SYSCTL_PCTIMER_P0 0x00000001 // General-Purpose Timer 0 Power
2248  // Control
2249 
2250 //*****************************************************************************
2251 //
2252 // The following are defines for the bit fields in the SYSCTL_PCGPIO register.
2253 //
2254 //*****************************************************************************
2255 #define SYSCTL_PCGPIO_P17 0x00020000 // GPIO Port T Power Control
2256 #define SYSCTL_PCGPIO_P16 0x00010000 // GPIO Port S Power Control
2257 #define SYSCTL_PCGPIO_P15 0x00008000 // GPIO Port R Power Control
2258 #define SYSCTL_PCGPIO_P14 0x00004000 // GPIO Port Q Power Control
2259 #define SYSCTL_PCGPIO_P13 0x00002000 // GPIO Port P Power Control
2260 #define SYSCTL_PCGPIO_P12 0x00001000 // GPIO Port N Power Control
2261 #define SYSCTL_PCGPIO_P11 0x00000800 // GPIO Port M Power Control
2262 #define SYSCTL_PCGPIO_P10 0x00000400 // GPIO Port L Power Control
2263 #define SYSCTL_PCGPIO_P9 0x00000200 // GPIO Port K Power Control
2264 #define SYSCTL_PCGPIO_P8 0x00000100 // GPIO Port J Power Control
2265 #define SYSCTL_PCGPIO_P7 0x00000080 // GPIO Port H Power Control
2266 #define SYSCTL_PCGPIO_P6 0x00000040 // GPIO Port G Power Control
2267 #define SYSCTL_PCGPIO_P5 0x00000020 // GPIO Port F Power Control
2268 #define SYSCTL_PCGPIO_P4 0x00000010 // GPIO Port E Power Control
2269 #define SYSCTL_PCGPIO_P3 0x00000008 // GPIO Port D Power Control
2270 #define SYSCTL_PCGPIO_P2 0x00000004 // GPIO Port C Power Control
2271 #define SYSCTL_PCGPIO_P1 0x00000002 // GPIO Port B Power Control
2272 #define SYSCTL_PCGPIO_P0 0x00000001 // GPIO Port A Power Control
2273 
2274 //*****************************************************************************
2275 //
2276 // The following are defines for the bit fields in the SYSCTL_PCDMA register.
2277 //
2278 //*****************************************************************************
2279 #define SYSCTL_PCDMA_P0 0x00000001 // uDMA Module Power Control
2280 
2281 //*****************************************************************************
2282 //
2283 // The following are defines for the bit fields in the SYSCTL_PCEPI register.
2284 //
2285 //*****************************************************************************
2286 #define SYSCTL_PCEPI_P0 0x00000001 // EPI Module Power Control
2287 
2288 //*****************************************************************************
2289 //
2290 // The following are defines for the bit fields in the SYSCTL_PCHIB register.
2291 //
2292 //*****************************************************************************
2293 #define SYSCTL_PCHIB_P0 0x00000001 // Hibernation Module Power Control
2294 
2295 //*****************************************************************************
2296 //
2297 // The following are defines for the bit fields in the SYSCTL_PCUART register.
2298 //
2299 //*****************************************************************************
2300 #define SYSCTL_PCUART_P7 0x00000080 // UART Module 7 Power Control
2301 #define SYSCTL_PCUART_P6 0x00000040 // UART Module 6 Power Control
2302 #define SYSCTL_PCUART_P5 0x00000020 // UART Module 5 Power Control
2303 #define SYSCTL_PCUART_P4 0x00000010 // UART Module 4 Power Control
2304 #define SYSCTL_PCUART_P3 0x00000008 // UART Module 3 Power Control
2305 #define SYSCTL_PCUART_P2 0x00000004 // UART Module 2 Power Control
2306 #define SYSCTL_PCUART_P1 0x00000002 // UART Module 1 Power Control
2307 #define SYSCTL_PCUART_P0 0x00000001 // UART Module 0 Power Control
2308 
2309 //*****************************************************************************
2310 //
2311 // The following are defines for the bit fields in the SYSCTL_PCSSI register.
2312 //
2313 //*****************************************************************************
2314 #define SYSCTL_PCSSI_P3 0x00000008 // SSI Module 3 Power Control
2315 #define SYSCTL_PCSSI_P2 0x00000004 // SSI Module 2 Power Control
2316 #define SYSCTL_PCSSI_P1 0x00000002 // SSI Module 1 Power Control
2317 #define SYSCTL_PCSSI_P0 0x00000001 // SSI Module 0 Power Control
2318 
2319 //*****************************************************************************
2320 //
2321 // The following are defines for the bit fields in the SYSCTL_PCI2C register.
2322 //
2323 //*****************************************************************************
2324 #define SYSCTL_PCI2C_P9 0x00000200 // I2C Module 9 Power Control
2325 #define SYSCTL_PCI2C_P8 0x00000100 // I2C Module 8 Power Control
2326 #define SYSCTL_PCI2C_P7 0x00000080 // I2C Module 7 Power Control
2327 #define SYSCTL_PCI2C_P6 0x00000040 // I2C Module 6 Power Control
2328 #define SYSCTL_PCI2C_P5 0x00000020 // I2C Module 5 Power Control
2329 #define SYSCTL_PCI2C_P4 0x00000010 // I2C Module 4 Power Control
2330 #define SYSCTL_PCI2C_P3 0x00000008 // I2C Module 3 Power Control
2331 #define SYSCTL_PCI2C_P2 0x00000004 // I2C Module 2 Power Control
2332 #define SYSCTL_PCI2C_P1 0x00000002 // I2C Module 1 Power Control
2333 #define SYSCTL_PCI2C_P0 0x00000001 // I2C Module 0 Power Control
2334 
2335 //*****************************************************************************
2336 //
2337 // The following are defines for the bit fields in the SYSCTL_PCUSB register.
2338 //
2339 //*****************************************************************************
2340 #define SYSCTL_PCUSB_P0 0x00000001 // USB Module Power Control
2341 
2342 //*****************************************************************************
2343 //
2344 // The following are defines for the bit fields in the SYSCTL_PCEPHY register.
2345 //
2346 //*****************************************************************************
2347 #define SYSCTL_PCEPHY_P0 0x00000001 // Ethernet PHY Module Power
2348  // Control
2349 
2350 //*****************************************************************************
2351 //
2352 // The following are defines for the bit fields in the SYSCTL_PCCAN register.
2353 //
2354 //*****************************************************************************
2355 #define SYSCTL_PCCAN_P1 0x00000002 // CAN Module 1 Power Control
2356 #define SYSCTL_PCCAN_P0 0x00000001 // CAN Module 0 Power Control
2357 
2358 //*****************************************************************************
2359 //
2360 // The following are defines for the bit fields in the SYSCTL_PCADC register.
2361 //
2362 //*****************************************************************************
2363 #define SYSCTL_PCADC_P1 0x00000002 // ADC Module 1 Power Control
2364 #define SYSCTL_PCADC_P0 0x00000001 // ADC Module 0 Power Control
2365 
2366 //*****************************************************************************
2367 //
2368 // The following are defines for the bit fields in the SYSCTL_PCACMP register.
2369 //
2370 //*****************************************************************************
2371 #define SYSCTL_PCACMP_P0 0x00000001 // Analog Comparator Module 0 Power
2372  // Control
2373 
2374 //*****************************************************************************
2375 //
2376 // The following are defines for the bit fields in the SYSCTL_PCPWM register.
2377 //
2378 //*****************************************************************************
2379 #define SYSCTL_PCPWM_P0 0x00000001 // PWM Module 0 Power Control
2380 
2381 //*****************************************************************************
2382 //
2383 // The following are defines for the bit fields in the SYSCTL_PCQEI register.
2384 //
2385 //*****************************************************************************
2386 #define SYSCTL_PCQEI_P0 0x00000001 // QEI Module 0 Power Control
2387 
2388 //*****************************************************************************
2389 //
2390 // The following are defines for the bit fields in the SYSCTL_PCEEPROM
2391 // register.
2392 //
2393 //*****************************************************************************
2394 #define SYSCTL_PCEEPROM_P0 0x00000001 // EEPROM Module 0 Power Control
2395 
2396 //*****************************************************************************
2397 //
2398 // The following are defines for the bit fields in the SYSCTL_PCCCM register.
2399 //
2400 //*****************************************************************************
2401 #define SYSCTL_PCCCM_P0 0x00000001 // CRC and Cryptographic Modules
2402  // Power Control
2403 
2404 //*****************************************************************************
2405 //
2406 // The following are defines for the bit fields in the SYSCTL_PCLCD register.
2407 //
2408 //*****************************************************************************
2409 #define SYSCTL_PCLCD_P0 0x00000001 // LCD Controller Module 0 Power
2410  // Control
2411 
2412 //*****************************************************************************
2413 //
2414 // The following are defines for the bit fields in the SYSCTL_PCOWIRE register.
2415 //
2416 //*****************************************************************************
2417 #define SYSCTL_PCOWIRE_P0 0x00000001 // 1-Wire Module 0 Power Control
2418 
2419 //*****************************************************************************
2420 //
2421 // The following are defines for the bit fields in the SYSCTL_PCEMAC register.
2422 //
2423 //*****************************************************************************
2424 #define SYSCTL_PCEMAC_P0 0x00000001 // Ethernet MAC Module 0 Power
2425  // Control
2426 
2427 //*****************************************************************************
2428 //
2429 // The following are defines for the bit fields in the SYSCTL_PRWD register.
2430 //
2431 //*****************************************************************************
2432 #define SYSCTL_PRWD_R1 0x00000002 // Watchdog Timer 1 Peripheral
2433  // Ready
2434 #define SYSCTL_PRWD_R0 0x00000001 // Watchdog Timer 0 Peripheral
2435  // Ready
2436 
2437 //*****************************************************************************
2438 //
2439 // The following are defines for the bit fields in the SYSCTL_PRTIMER register.
2440 //
2441 //*****************************************************************************
2442 #define SYSCTL_PRTIMER_R7 0x00000080 // 16/32-Bit General-Purpose Timer
2443  // 7 Peripheral Ready
2444 #define SYSCTL_PRTIMER_R6 0x00000040 // 16/32-Bit General-Purpose Timer
2445  // 6 Peripheral Ready
2446 #define SYSCTL_PRTIMER_R5 0x00000020 // 16/32-Bit General-Purpose Timer
2447  // 5 Peripheral Ready
2448 #define SYSCTL_PRTIMER_R4 0x00000010 // 16/32-Bit General-Purpose Timer
2449  // 4 Peripheral Ready
2450 #define SYSCTL_PRTIMER_R3 0x00000008 // 16/32-Bit General-Purpose Timer
2451  // 3 Peripheral Ready
2452 #define SYSCTL_PRTIMER_R2 0x00000004 // 16/32-Bit General-Purpose Timer
2453  // 2 Peripheral Ready
2454 #define SYSCTL_PRTIMER_R1 0x00000002 // 16/32-Bit General-Purpose Timer
2455  // 1 Peripheral Ready
2456 #define SYSCTL_PRTIMER_R0 0x00000001 // 16/32-Bit General-Purpose Timer
2457  // 0 Peripheral Ready
2458 
2459 //*****************************************************************************
2460 //
2461 // The following are defines for the bit fields in the SYSCTL_PRGPIO register.
2462 //
2463 //*****************************************************************************
2464 #define SYSCTL_PRGPIO_R17 0x00020000 // GPIO Port T Peripheral Ready
2465 #define SYSCTL_PRGPIO_R16 0x00010000 // GPIO Port S Peripheral Ready
2466 #define SYSCTL_PRGPIO_R15 0x00008000 // GPIO Port R Peripheral Ready
2467 #define SYSCTL_PRGPIO_R14 0x00004000 // GPIO Port Q Peripheral Ready
2468 #define SYSCTL_PRGPIO_R13 0x00002000 // GPIO Port P Peripheral Ready
2469 #define SYSCTL_PRGPIO_R12 0x00001000 // GPIO Port N Peripheral Ready
2470 #define SYSCTL_PRGPIO_R11 0x00000800 // GPIO Port M Peripheral Ready
2471 #define SYSCTL_PRGPIO_R10 0x00000400 // GPIO Port L Peripheral Ready
2472 #define SYSCTL_PRGPIO_R9 0x00000200 // GPIO Port K Peripheral Ready
2473 #define SYSCTL_PRGPIO_R8 0x00000100 // GPIO Port J Peripheral Ready
2474 #define SYSCTL_PRGPIO_R7 0x00000080 // GPIO Port H Peripheral Ready
2475 #define SYSCTL_PRGPIO_R6 0x00000040 // GPIO Port G Peripheral Ready
2476 #define SYSCTL_PRGPIO_R5 0x00000020 // GPIO Port F Peripheral Ready
2477 #define SYSCTL_PRGPIO_R4 0x00000010 // GPIO Port E Peripheral Ready
2478 #define SYSCTL_PRGPIO_R3 0x00000008 // GPIO Port D Peripheral Ready
2479 #define SYSCTL_PRGPIO_R2 0x00000004 // GPIO Port C Peripheral Ready
2480 #define SYSCTL_PRGPIO_R1 0x00000002 // GPIO Port B Peripheral Ready
2481 #define SYSCTL_PRGPIO_R0 0x00000001 // GPIO Port A Peripheral Ready
2482 
2483 //*****************************************************************************
2484 //
2485 // The following are defines for the bit fields in the SYSCTL_PRDMA register.
2486 //
2487 //*****************************************************************************
2488 #define SYSCTL_PRDMA_R0 0x00000001 // uDMA Module Peripheral Ready
2489 
2490 //*****************************************************************************
2491 //
2492 // The following are defines for the bit fields in the SYSCTL_PREPI register.
2493 //
2494 //*****************************************************************************
2495 #define SYSCTL_PREPI_R0 0x00000001 // EPI Module Peripheral Ready
2496 
2497 //*****************************************************************************
2498 //
2499 // The following are defines for the bit fields in the SYSCTL_PRHIB register.
2500 //
2501 //*****************************************************************************
2502 #define SYSCTL_PRHIB_R0 0x00000001 // Hibernation Module Peripheral
2503  // Ready
2504 
2505 //*****************************************************************************
2506 //
2507 // The following are defines for the bit fields in the SYSCTL_PRUART register.
2508 //
2509 //*****************************************************************************
2510 #define SYSCTL_PRUART_R7 0x00000080 // UART Module 7 Peripheral Ready
2511 #define SYSCTL_PRUART_R6 0x00000040 // UART Module 6 Peripheral Ready
2512 #define SYSCTL_PRUART_R5 0x00000020 // UART Module 5 Peripheral Ready
2513 #define SYSCTL_PRUART_R4 0x00000010 // UART Module 4 Peripheral Ready
2514 #define SYSCTL_PRUART_R3 0x00000008 // UART Module 3 Peripheral Ready
2515 #define SYSCTL_PRUART_R2 0x00000004 // UART Module 2 Peripheral Ready
2516 #define SYSCTL_PRUART_R1 0x00000002 // UART Module 1 Peripheral Ready
2517 #define SYSCTL_PRUART_R0 0x00000001 // UART Module 0 Peripheral Ready
2518 
2519 //*****************************************************************************
2520 //
2521 // The following are defines for the bit fields in the SYSCTL_PRSSI register.
2522 //
2523 //*****************************************************************************
2524 #define SYSCTL_PRSSI_R3 0x00000008 // SSI Module 3 Peripheral Ready
2525 #define SYSCTL_PRSSI_R2 0x00000004 // SSI Module 2 Peripheral Ready
2526 #define SYSCTL_PRSSI_R1 0x00000002 // SSI Module 1 Peripheral Ready
2527 #define SYSCTL_PRSSI_R0 0x00000001 // SSI Module 0 Peripheral Ready
2528 
2529 //*****************************************************************************
2530 //
2531 // The following are defines for the bit fields in the SYSCTL_PRI2C register.
2532 //
2533 //*****************************************************************************
2534 #define SYSCTL_PRI2C_R9 0x00000200 // I2C Module 9 Peripheral Ready
2535 #define SYSCTL_PRI2C_R8 0x00000100 // I2C Module 8 Peripheral Ready
2536 #define SYSCTL_PRI2C_R7 0x00000080 // I2C Module 7 Peripheral Ready
2537 #define SYSCTL_PRI2C_R6 0x00000040 // I2C Module 6 Peripheral Ready
2538 #define SYSCTL_PRI2C_R5 0x00000020 // I2C Module 5 Peripheral Ready
2539 #define SYSCTL_PRI2C_R4 0x00000010 // I2C Module 4 Peripheral Ready
2540 #define SYSCTL_PRI2C_R3 0x00000008 // I2C Module 3 Peripheral Ready
2541 #define SYSCTL_PRI2C_R2 0x00000004 // I2C Module 2 Peripheral Ready
2542 #define SYSCTL_PRI2C_R1 0x00000002 // I2C Module 1 Peripheral Ready
2543 #define SYSCTL_PRI2C_R0 0x00000001 // I2C Module 0 Peripheral Ready
2544 
2545 //*****************************************************************************
2546 //
2547 // The following are defines for the bit fields in the SYSCTL_PRUSB register.
2548 //
2549 //*****************************************************************************
2550 #define SYSCTL_PRUSB_R0 0x00000001 // USB Module Peripheral Ready
2551 
2552 //*****************************************************************************
2553 //
2554 // The following are defines for the bit fields in the SYSCTL_PREPHY register.
2555 //
2556 //*****************************************************************************
2557 #define SYSCTL_PREPHY_R0 0x00000001 // Ethernet PHY Module Peripheral
2558  // Ready
2559 
2560 //*****************************************************************************
2561 //
2562 // The following are defines for the bit fields in the SYSCTL_PRCAN register.
2563 //
2564 //*****************************************************************************
2565 #define SYSCTL_PRCAN_R1 0x00000002 // CAN Module 1 Peripheral Ready
2566 #define SYSCTL_PRCAN_R0 0x00000001 // CAN Module 0 Peripheral Ready
2567 
2568 //*****************************************************************************
2569 //
2570 // The following are defines for the bit fields in the SYSCTL_PRADC register.
2571 //
2572 //*****************************************************************************
2573 #define SYSCTL_PRADC_R1 0x00000002 // ADC Module 1 Peripheral Ready
2574 #define SYSCTL_PRADC_R0 0x00000001 // ADC Module 0 Peripheral Ready
2575 
2576 //*****************************************************************************
2577 //
2578 // The following are defines for the bit fields in the SYSCTL_PRACMP register.
2579 //
2580 //*****************************************************************************
2581 #define SYSCTL_PRACMP_R0 0x00000001 // Analog Comparator Module 0
2582  // Peripheral Ready
2583 
2584 //*****************************************************************************
2585 //
2586 // The following are defines for the bit fields in the SYSCTL_PRPWM register.
2587 //
2588 //*****************************************************************************
2589 #define SYSCTL_PRPWM_R1 0x00000002 // PWM Module 1 Peripheral Ready
2590 #define SYSCTL_PRPWM_R0 0x00000001 // PWM Module 0 Peripheral Ready
2591 
2592 //*****************************************************************************
2593 //
2594 // The following are defines for the bit fields in the SYSCTL_PRQEI register.
2595 //
2596 //*****************************************************************************
2597 #define SYSCTL_PRQEI_R1 0x00000002 // QEI Module 1 Peripheral Ready
2598 #define SYSCTL_PRQEI_R0 0x00000001 // QEI Module 0 Peripheral Ready
2599 
2600 //*****************************************************************************
2601 //
2602 // The following are defines for the bit fields in the SYSCTL_PREEPROM
2603 // register.
2604 //
2605 //*****************************************************************************
2606 #define SYSCTL_PREEPROM_R0 0x00000001 // EEPROM Module Peripheral Ready
2607 
2608 //*****************************************************************************
2609 //
2610 // The following are defines for the bit fields in the SYSCTL_PRCCM register.
2611 //
2612 //*****************************************************************************
2613 #define SYSCTL_PRCCM_R0 0x00000001 // CRC and Cryptographic Modules
2614  // Peripheral Ready
2615 
2616 //*****************************************************************************
2617 //
2618 // The following are defines for the bit fields in the SYSCTL_PRLCD register.
2619 //
2620 //*****************************************************************************
2621 #define SYSCTL_PRLCD_R0 0x00000001 // LCD Controller Module 0
2622  // Peripheral Ready
2623 
2624 //*****************************************************************************
2625 //
2626 // The following are defines for the bit fields in the SYSCTL_PROWIRE register.
2627 //
2628 //*****************************************************************************
2629 #define SYSCTL_PROWIRE_R0 0x00000001 // 1-Wire Module 0 Peripheral Ready
2630 
2631 //*****************************************************************************
2632 //
2633 // The following are defines for the bit fields in the SYSCTL_PREMAC register.
2634 //
2635 //*****************************************************************************
2636 #define SYSCTL_PREMAC_R0 0x00000001 // Ethernet MAC Module 0 Peripheral
2637  // Ready
2638 
2639 //*****************************************************************************
2640 //
2641 // The following are defines for the bit fields in the SYSCTL_UNIQUEID0
2642 // register.
2643 //
2644 //*****************************************************************************
2645 #define SYSCTL_UNIQUEID0_ID_M 0xFFFFFFFF // Unique ID
2646 #define SYSCTL_UNIQUEID0_ID_S 0
2647 
2648 //*****************************************************************************
2649 //
2650 // The following are defines for the bit fields in the SYSCTL_UNIQUEID1
2651 // register.
2652 //
2653 //*****************************************************************************
2654 #define SYSCTL_UNIQUEID1_ID_M 0xFFFFFFFF // Unique ID
2655 #define SYSCTL_UNIQUEID1_ID_S 0
2656 
2657 //*****************************************************************************
2658 //
2659 // The following are defines for the bit fields in the SYSCTL_UNIQUEID2
2660 // register.
2661 //
2662 //*****************************************************************************
2663 #define SYSCTL_UNIQUEID2_ID_M 0xFFFFFFFF // Unique ID
2664 #define SYSCTL_UNIQUEID2_ID_S 0
2665 
2666 //*****************************************************************************
2667 //
2668 // The following are defines for the bit fields in the SYSCTL_UNIQUEID3
2669 // register.
2670 //
2671 //*****************************************************************************
2672 #define SYSCTL_UNIQUEID3_ID_M 0xFFFFFFFF // Unique ID
2673 #define SYSCTL_UNIQUEID3_ID_S 0
2674 
2675 // //*****************************************************************************
2676 // //
2677 // // The following are defines for the bit fields in the SYSCTL_CCMCGREQ
2678 // // register.
2679 // //
2680 // //*****************************************************************************
2681 // #define SYSCTL_CCMCGREQ_DESCFG 0x00000004 // DES Clock Gating Request
2682 // #define SYSCTL_CCMCGREQ_AESCFG 0x00000002 // AES Clock Gating Request
2683 // #define SYSCTL_CCMCGREQ_SHACFG 0x00000001 // SHA/MD5 Clock Gating Request
2684 
2685 #endif // __HW_SYSCTL_H__
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