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Go to the documentation of this file. 46 #define NVIC_ACTLR 0xE000E008 // Auxiliary Control 47 #define NVIC_ST_CTRL 0xE000E010 // SysTick Control and Status 49 #define NVIC_ST_RELOAD 0xE000E014 // SysTick Reload Value Register 50 #define NVIC_ST_CURRENT 0xE000E018 // SysTick Current Value Register 51 #define NVIC_EN0 0xE000E100 // Interrupt 0-31 Set Enable 52 #define NVIC_EN1 0xE000E104 // Interrupt 32-63 Set Enable 53 #define NVIC_EN2 0xE000E108 // Interrupt 64-95 Set Enable 54 #define NVIC_EN3 0xE000E10C // Interrupt 96-127 Set Enable 55 #define NVIC_EN4 0xE000E110 // Interrupt 128-159 Set Enable 56 #define NVIC_DIS0 0xE000E180 // Interrupt 0-31 Clear Enable 57 #define NVIC_DIS1 0xE000E184 // Interrupt 32-63 Clear Enable 58 #define NVIC_DIS2 0xE000E188 // Interrupt 64-95 Clear Enable 59 #define NVIC_DIS3 0xE000E18C // Interrupt 96-127 Clear Enable 60 #define NVIC_DIS4 0xE000E190 // Interrupt 128-159 Clear Enable 61 #define NVIC_PEND0 0xE000E200 // Interrupt 0-31 Set Pending 62 #define NVIC_PEND1 0xE000E204 // Interrupt 32-63 Set Pending 63 #define NVIC_PEND2 0xE000E208 // Interrupt 64-95 Set Pending 64 #define NVIC_PEND3 0xE000E20C // Interrupt 96-127 Set Pending 65 #define NVIC_PEND4 0xE000E210 // Interrupt 128-159 Set Pending 66 #define NVIC_UNPEND0 0xE000E280 // Interrupt 0-31 Clear Pending 67 #define NVIC_UNPEND1 0xE000E284 // Interrupt 32-63 Clear Pending 68 #define NVIC_UNPEND2 0xE000E288 // Interrupt 64-95 Clear Pending 69 #define NVIC_UNPEND3 0xE000E28C // Interrupt 96-127 Clear Pending 70 #define NVIC_UNPEND4 0xE000E290 // Interrupt 128-159 Clear Pending 71 #define NVIC_ACTIVE0 0xE000E300 // Interrupt 0-31 Active Bit 72 #define NVIC_ACTIVE1 0xE000E304 // Interrupt 32-63 Active Bit 73 #define NVIC_ACTIVE2 0xE000E308 // Interrupt 64-95 Active Bit 74 #define NVIC_ACTIVE3 0xE000E30C // Interrupt 96-127 Active Bit 75 #define NVIC_ACTIVE4 0xE000E310 // Interrupt 128-159 Active Bit 76 #define NVIC_PRI0 0xE000E400 // Interrupt 0-3 Priority 77 #define NVIC_PRI1 0xE000E404 // Interrupt 4-7 Priority 78 #define NVIC_PRI2 0xE000E408 // Interrupt 8-11 Priority 79 #define NVIC_PRI3 0xE000E40C // Interrupt 12-15 Priority 80 #define NVIC_PRI4 0xE000E410 // Interrupt 16-19 Priority 81 #define NVIC_PRI5 0xE000E414 // Interrupt 20-23 Priority 82 #define NVIC_PRI6 0xE000E418 // Interrupt 24-27 Priority 83 #define NVIC_PRI7 0xE000E41C // Interrupt 28-31 Priority 84 #define NVIC_PRI8 0xE000E420 // Interrupt 32-35 Priority 85 #define NVIC_PRI9 0xE000E424 // Interrupt 36-39 Priority 86 #define NVIC_PRI10 0xE000E428 // Interrupt 40-43 Priority 87 #define NVIC_PRI11 0xE000E42C // Interrupt 44-47 Priority 88 #define NVIC_PRI12 0xE000E430 // Interrupt 48-51 Priority 89 #define NVIC_PRI13 0xE000E434 // Interrupt 52-55 Priority 90 #define NVIC_PRI14 0xE000E438 // Interrupt 56-59 Priority 91 #define NVIC_PRI15 0xE000E43C // Interrupt 60-63 Priority 92 #define NVIC_PRI16 0xE000E440 // Interrupt 64-67 Priority 93 #define NVIC_PRI17 0xE000E444 // Interrupt 68-71 Priority 94 #define NVIC_PRI18 0xE000E448 // Interrupt 72-75 Priority 95 #define NVIC_PRI19 0xE000E44C // Interrupt 76-79 Priority 96 #define NVIC_PRI20 0xE000E450 // Interrupt 80-83 Priority 97 #define NVIC_PRI21 0xE000E454 // Interrupt 84-87 Priority 98 #define NVIC_PRI22 0xE000E458 // Interrupt 88-91 Priority 99 #define NVIC_PRI23 0xE000E45C // Interrupt 92-95 Priority 100 #define NVIC_PRI24 0xE000E460 // Interrupt 96-99 Priority 101 #define NVIC_PRI25 0xE000E464 // Interrupt 100-103 Priority 102 #define NVIC_PRI26 0xE000E468 // Interrupt 104-107 Priority 103 #define NVIC_PRI27 0xE000E46C // Interrupt 108-111 Priority 104 #define NVIC_PRI28 0xE000E470 // Interrupt 112-115 Priority 105 #define NVIC_PRI29 0xE000E474 // Interrupt 116-119 Priority 106 #define NVIC_PRI30 0xE000E478 // Interrupt 120-123 Priority 107 #define NVIC_PRI31 0xE000E47C // Interrupt 124-127 Priority 108 #define NVIC_PRI32 0xE000E480 // Interrupt 128-131 Priority 109 #define NVIC_PRI33 0xE000E484 // Interrupt 132-135 Priority 110 #define NVIC_PRI34 0xE000E488 // Interrupt 136-139 Priority 111 #define NVIC_CPUID 0xE000ED00 // CPU ID Base 112 #define NVIC_INT_CTRL 0xE000ED04 // Interrupt Control and State 113 #define NVIC_VTABLE 0xE000ED08 // Vector Table Offset 114 #define NVIC_APINT 0xE000ED0C // Application Interrupt and Reset 116 #define NVIC_SYS_CTRL 0xE000ED10 // System Control 117 #define NVIC_CFG_CTRL 0xE000ED14 // Configuration and Control 118 #define NVIC_SYS_PRI1 0xE000ED18 // System Handler Priority 1 119 #define NVIC_SYS_PRI2 0xE000ED1C // System Handler Priority 2 120 #define NVIC_SYS_PRI3 0xE000ED20 // System Handler Priority 3 121 #define NVIC_SYS_HND_CTRL 0xE000ED24 // System Handler Control and State 122 #define NVIC_FAULT_STAT 0xE000ED28 // Configurable Fault Status 123 #define NVIC_HFAULT_STAT 0xE000ED2C // Hard Fault Status 124 #define NVIC_DEBUG_STAT 0xE000ED30 // Debug Status Register 125 #define NVIC_MM_ADDR 0xE000ED34 // Memory Management Fault Address 126 #define NVIC_FAULT_ADDR 0xE000ED38 // Bus Fault Address 127 #define NVIC_CPAC 0xE000ED88 // Coprocessor Access Control 128 #define NVIC_MPU_TYPE 0xE000ED90 // MPU Type 129 #define NVIC_MPU_CTRL 0xE000ED94 // MPU Control 130 #define NVIC_MPU_NUMBER 0xE000ED98 // MPU Region Number 131 #define NVIC_MPU_BASE 0xE000ED9C // MPU Region Base Address 132 #define NVIC_MPU_ATTR 0xE000EDA0 // MPU Region Attribute and Size 133 #define NVIC_MPU_BASE1 0xE000EDA4 // MPU Region Base Address Alias 1 134 #define NVIC_MPU_ATTR1 0xE000EDA8 // MPU Region Attribute and Size 136 #define NVIC_MPU_BASE2 0xE000EDAC // MPU Region Base Address Alias 2 137 #define NVIC_MPU_ATTR2 0xE000EDB0 // MPU Region Attribute and Size 139 #define NVIC_MPU_BASE3 0xE000EDB4 // MPU Region Base Address Alias 3 140 #define NVIC_MPU_ATTR3 0xE000EDB8 // MPU Region Attribute and Size 142 #define NVIC_DBG_CTRL 0xE000EDF0 // Debug Control and Status Reg 143 #define NVIC_DBG_XFER 0xE000EDF4 // Debug Core Reg. Transfer Select 144 #define NVIC_DBG_DATA 0xE000EDF8 // Debug Core Register Data 145 #define NVIC_DBG_INT 0xE000EDFC // Debug Reset Interrupt Control 146 #define NVIC_SW_TRIG 0xE000EF00 // Software Trigger Interrupt 147 #define NVIC_FPCC 0xE000EF34 // Floating-Point Context Control 148 #define NVIC_FPCA 0xE000EF38 // Floating-Point Context Address 149 #define NVIC_FPDSC 0xE000EF3C // Floating-Point Default Status 157 #define NVIC_ACTLR_DISOOFP 0x00000200 // Disable Out-Of-Order Floating 159 #define NVIC_ACTLR_DISFPCA 0x00000100 // Disable CONTROL 160 #define NVIC_ACTLR_DISFOLD 0x00000004 // Disable IT Folding 161 #define NVIC_ACTLR_DISWBUF 0x00000002 // Disable Write Buffer 162 #define NVIC_ACTLR_DISMCYC 0x00000001 // Disable Interrupts of Multiple 170 #define NVIC_ST_CTRL_COUNT 0x00010000 // Count Flag 171 #define NVIC_ST_CTRL_CLK_SRC 0x00000004 // Clock Source 172 #define NVIC_ST_CTRL_INTEN 0x00000002 // Interrupt Enable 173 #define NVIC_ST_CTRL_ENABLE 0x00000001 // Enable 180 #define NVIC_ST_RELOAD_M 0x00FFFFFF // Reload Value 181 #define NVIC_ST_RELOAD_S 0 189 #define NVIC_ST_CURRENT_M 0x00FFFFFF // Current Value 190 #define NVIC_ST_CURRENT_S 0 197 #define NVIC_EN0_INT_M 0xFFFFFFFF // Interrupt Enable 204 #define NVIC_EN1_INT_M 0xFFFFFFFF // Interrupt Enable 211 #define NVIC_EN2_INT_M 0xFFFFFFFF // Interrupt Enable 218 #define NVIC_EN3_INT_M 0xFFFFFFFF // Interrupt Enable 225 #define NVIC_EN4_INT_M 0x000007FF // Interrupt Enable 232 #define NVIC_DIS0_INT_M 0xFFFFFFFF // Interrupt Disable 239 #define NVIC_DIS1_INT_M 0xFFFFFFFF // Interrupt Disable 246 #define NVIC_DIS2_INT_M 0xFFFFFFFF // Interrupt Disable 253 #define NVIC_DIS3_INT_M 0xFFFFFFFF // Interrupt Disable 260 #define NVIC_DIS4_INT_M 0x000007FF // Interrupt Disable 267 #define NVIC_PEND0_INT_M 0xFFFFFFFF // Interrupt Set Pending 274 #define NVIC_PEND1_INT_M 0xFFFFFFFF // Interrupt Set Pending 281 #define NVIC_PEND2_INT_M 0xFFFFFFFF // Interrupt Set Pending 288 #define NVIC_PEND3_INT_M 0xFFFFFFFF // Interrupt Set Pending 295 #define NVIC_PEND4_INT_M 0x000007FF // Interrupt Set Pending 302 #define NVIC_UNPEND0_INT_M 0xFFFFFFFF // Interrupt Clear Pending 309 #define NVIC_UNPEND1_INT_M 0xFFFFFFFF // Interrupt Clear Pending 316 #define NVIC_UNPEND2_INT_M 0xFFFFFFFF // Interrupt Clear Pending 323 #define NVIC_UNPEND3_INT_M 0xFFFFFFFF // Interrupt Clear Pending 330 #define NVIC_UNPEND4_INT_M 0x000007FF // Interrupt Clear Pending 337 #define NVIC_ACTIVE0_INT_M 0xFFFFFFFF // Interrupt Active 344 #define NVIC_ACTIVE1_INT_M 0xFFFFFFFF // Interrupt Active 351 #define NVIC_ACTIVE2_INT_M 0xFFFFFFFF // Interrupt Active 358 #define NVIC_ACTIVE3_INT_M 0xFFFFFFFF // Interrupt Active 365 #define NVIC_ACTIVE4_INT_M 0x000007FF // Interrupt Active 372 #define NVIC_PRI0_INT3_M 0xE0000000 // Interrupt 3 Priority Mask 373 #define NVIC_PRI0_INT2_M 0x00E00000 // Interrupt 2 Priority Mask 374 #define NVIC_PRI0_INT1_M 0x0000E000 // Interrupt 1 Priority Mask 375 #define NVIC_PRI0_INT0_M 0x000000E0 // Interrupt 0 Priority Mask 376 #define NVIC_PRI0_INT3_S 29 377 #define NVIC_PRI0_INT2_S 21 378 #define NVIC_PRI0_INT1_S 13 379 #define NVIC_PRI0_INT0_S 5 386 #define NVIC_PRI1_INT7_M 0xE0000000 // Interrupt 7 Priority Mask 387 #define NVIC_PRI1_INT6_M 0x00E00000 // Interrupt 6 Priority Mask 388 #define NVIC_PRI1_INT5_M 0x0000E000 // Interrupt 5 Priority Mask 389 #define NVIC_PRI1_INT4_M 0x000000E0 // Interrupt 4 Priority Mask 390 #define NVIC_PRI1_INT7_S 29 391 #define NVIC_PRI1_INT6_S 21 392 #define NVIC_PRI1_INT5_S 13 393 #define NVIC_PRI1_INT4_S 5 400 #define NVIC_PRI2_INT11_M 0xE0000000 // Interrupt 11 Priority Mask 401 #define NVIC_PRI2_INT10_M 0x00E00000 // Interrupt 10 Priority Mask 402 #define NVIC_PRI2_INT9_M 0x0000E000 // Interrupt 9 Priority Mask 403 #define NVIC_PRI2_INT8_M 0x000000E0 // Interrupt 8 Priority Mask 404 #define NVIC_PRI2_INT11_S 29 405 #define NVIC_PRI2_INT10_S 21 406 #define NVIC_PRI2_INT9_S 13 407 #define NVIC_PRI2_INT8_S 5 414 #define NVIC_PRI3_INT15_M 0xE0000000 // Interrupt 15 Priority Mask 415 #define NVIC_PRI3_INT14_M 0x00E00000 // Interrupt 14 Priority Mask 416 #define NVIC_PRI3_INT13_M 0x0000E000 // Interrupt 13 Priority Mask 417 #define NVIC_PRI3_INT12_M 0x000000E0 // Interrupt 12 Priority Mask 418 #define NVIC_PRI3_INT15_S 29 419 #define NVIC_PRI3_INT14_S 21 420 #define NVIC_PRI3_INT13_S 13 421 #define NVIC_PRI3_INT12_S 5 428 #define NVIC_PRI4_INT19_M 0xE0000000 // Interrupt 19 Priority Mask 429 #define NVIC_PRI4_INT18_M 0x00E00000 // Interrupt 18 Priority Mask 430 #define NVIC_PRI4_INT17_M 0x0000E000 // Interrupt 17 Priority Mask 431 #define NVIC_PRI4_INT16_M 0x000000E0 // Interrupt 16 Priority Mask 432 #define NVIC_PRI4_INT19_S 29 433 #define NVIC_PRI4_INT18_S 21 434 #define NVIC_PRI4_INT17_S 13 435 #define NVIC_PRI4_INT16_S 5 442 #define NVIC_PRI5_INT23_M 0xE0000000 // Interrupt 23 Priority Mask 443 #define NVIC_PRI5_INT22_M 0x00E00000 // Interrupt 22 Priority Mask 444 #define NVIC_PRI5_INT21_M 0x0000E000 // Interrupt 21 Priority Mask 445 #define NVIC_PRI5_INT20_M 0x000000E0 // Interrupt 20 Priority Mask 446 #define NVIC_PRI5_INT23_S 29 447 #define NVIC_PRI5_INT22_S 21 448 #define NVIC_PRI5_INT21_S 13 449 #define NVIC_PRI5_INT20_S 5 456 #define NVIC_PRI6_INT27_M 0xE0000000 // Interrupt 27 Priority Mask 457 #define NVIC_PRI6_INT26_M 0x00E00000 // Interrupt 26 Priority Mask 458 #define NVIC_PRI6_INT25_M 0x0000E000 // Interrupt 25 Priority Mask 459 #define NVIC_PRI6_INT24_M 0x000000E0 // Interrupt 24 Priority Mask 460 #define NVIC_PRI6_INT27_S 29 461 #define NVIC_PRI6_INT26_S 21 462 #define NVIC_PRI6_INT25_S 13 463 #define NVIC_PRI6_INT24_S 5 470 #define NVIC_PRI7_INT31_M 0xE0000000 // Interrupt 31 Priority Mask 471 #define NVIC_PRI7_INT30_M 0x00E00000 // Interrupt 30 Priority Mask 472 #define NVIC_PRI7_INT29_M 0x0000E000 // Interrupt 29 Priority Mask 473 #define NVIC_PRI7_INT28_M 0x000000E0 // Interrupt 28 Priority Mask 474 #define NVIC_PRI7_INT31_S 29 475 #define NVIC_PRI7_INT30_S 21 476 #define NVIC_PRI7_INT29_S 13 477 #define NVIC_PRI7_INT28_S 5 484 #define NVIC_PRI8_INT35_M 0xE0000000 // Interrupt 35 Priority Mask 485 #define NVIC_PRI8_INT34_M 0x00E00000 // Interrupt 34 Priority Mask 486 #define NVIC_PRI8_INT33_M 0x0000E000 // Interrupt 33 Priority Mask 487 #define NVIC_PRI8_INT32_M 0x000000E0 // Interrupt 32 Priority Mask 488 #define NVIC_PRI8_INT35_S 29 489 #define NVIC_PRI8_INT34_S 21 490 #define NVIC_PRI8_INT33_S 13 491 #define NVIC_PRI8_INT32_S 5 498 #define NVIC_PRI9_INT39_M 0xE0000000 // Interrupt 39 Priority Mask 499 #define NVIC_PRI9_INT38_M 0x00E00000 // Interrupt 38 Priority Mask 500 #define NVIC_PRI9_INT37_M 0x0000E000 // Interrupt 37 Priority Mask 501 #define NVIC_PRI9_INT36_M 0x000000E0 // Interrupt 36 Priority Mask 502 #define NVIC_PRI9_INT39_S 29 503 #define NVIC_PRI9_INT38_S 21 504 #define NVIC_PRI9_INT37_S 13 505 #define NVIC_PRI9_INT36_S 5 512 #define NVIC_PRI10_INT43_M 0xE0000000 // Interrupt 43 Priority Mask 513 #define NVIC_PRI10_INT42_M 0x00E00000 // Interrupt 42 Priority Mask 514 #define NVIC_PRI10_INT41_M 0x0000E000 // Interrupt 41 Priority Mask 515 #define NVIC_PRI10_INT40_M 0x000000E0 // Interrupt 40 Priority Mask 516 #define NVIC_PRI10_INT43_S 29 517 #define NVIC_PRI10_INT42_S 21 518 #define NVIC_PRI10_INT41_S 13 519 #define NVIC_PRI10_INT40_S 5 526 #define NVIC_PRI11_INT47_M 0xE0000000 // Interrupt 47 Priority Mask 527 #define NVIC_PRI11_INT46_M 0x00E00000 // Interrupt 46 Priority Mask 528 #define NVIC_PRI11_INT45_M 0x0000E000 // Interrupt 45 Priority Mask 529 #define NVIC_PRI11_INT44_M 0x000000E0 // Interrupt 44 Priority Mask 530 #define NVIC_PRI11_INT47_S 29 531 #define NVIC_PRI11_INT46_S 21 532 #define NVIC_PRI11_INT45_S 13 533 #define NVIC_PRI11_INT44_S 5 540 #define NVIC_PRI12_INT51_M 0xE0000000 // Interrupt 51 Priority Mask 541 #define NVIC_PRI12_INT50_M 0x00E00000 // Interrupt 50 Priority Mask 542 #define NVIC_PRI12_INT49_M 0x0000E000 // Interrupt 49 Priority Mask 543 #define NVIC_PRI12_INT48_M 0x000000E0 // Interrupt 48 Priority Mask 544 #define NVIC_PRI12_INT51_S 29 545 #define NVIC_PRI12_INT50_S 21 546 #define NVIC_PRI12_INT49_S 13 547 #define NVIC_PRI12_INT48_S 5 554 #define NVIC_PRI13_INT55_M 0xE0000000 // Interrupt 55 Priority Mask 555 #define NVIC_PRI13_INT54_M 0x00E00000 // Interrupt 54 Priority Mask 556 #define NVIC_PRI13_INT53_M 0x0000E000 // Interrupt 53 Priority Mask 557 #define NVIC_PRI13_INT52_M 0x000000E0 // Interrupt 52 Priority Mask 558 #define NVIC_PRI13_INT55_S 29 559 #define NVIC_PRI13_INT54_S 21 560 #define NVIC_PRI13_INT53_S 13 561 #define NVIC_PRI13_INT52_S 5 568 #define NVIC_PRI14_INTD_M 0xE0000000 // Interrupt 59 Priority Mask 569 #define NVIC_PRI14_INTC_M 0x00E00000 // Interrupt 58 Priority Mask 570 #define NVIC_PRI14_INTB_M 0x0000E000 // Interrupt 57 Priority Mask 571 #define NVIC_PRI14_INTA_M 0x000000E0 // Interrupt 56 Priority Mask 572 #define NVIC_PRI14_INTD_S 29 573 #define NVIC_PRI14_INTC_S 21 574 #define NVIC_PRI14_INTB_S 13 575 #define NVIC_PRI14_INTA_S 5 582 #define NVIC_PRI15_INTD_M 0xE0000000 // Interrupt 63 Priority Mask 583 #define NVIC_PRI15_INTC_M 0x00E00000 // Interrupt 62 Priority Mask 584 #define NVIC_PRI15_INTB_M 0x0000E000 // Interrupt 61 Priority Mask 585 #define NVIC_PRI15_INTA_M 0x000000E0 // Interrupt 60 Priority Mask 586 #define NVIC_PRI15_INTD_S 29 587 #define NVIC_PRI15_INTC_S 21 588 #define NVIC_PRI15_INTB_S 13 589 #define NVIC_PRI15_INTA_S 5 596 #define NVIC_PRI16_INTD_M 0xE0000000 // Interrupt 67 Priority Mask 597 #define NVIC_PRI16_INTC_M 0x00E00000 // Interrupt 66 Priority Mask 598 #define NVIC_PRI16_INTB_M 0x0000E000 // Interrupt 65 Priority Mask 599 #define NVIC_PRI16_INTA_M 0x000000E0 // Interrupt 64 Priority Mask 600 #define NVIC_PRI16_INTD_S 29 601 #define NVIC_PRI16_INTC_S 21 602 #define NVIC_PRI16_INTB_S 13 603 #define NVIC_PRI16_INTA_S 5 610 #define NVIC_PRI17_INTD_M 0xE0000000 // Interrupt 71 Priority Mask 611 #define NVIC_PRI17_INTC_M 0x00E00000 // Interrupt 70 Priority Mask 612 #define NVIC_PRI17_INTB_M 0x0000E000 // Interrupt 69 Priority Mask 613 #define NVIC_PRI17_INTA_M 0x000000E0 // Interrupt 68 Priority Mask 614 #define NVIC_PRI17_INTD_S 29 615 #define NVIC_PRI17_INTC_S 21 616 #define NVIC_PRI17_INTB_S 13 617 #define NVIC_PRI17_INTA_S 5 624 #define NVIC_PRI18_INTD_M 0xE0000000 // Interrupt 75 Priority Mask 625 #define NVIC_PRI18_INTC_M 0x00E00000 // Interrupt 74 Priority Mask 626 #define NVIC_PRI18_INTB_M 0x0000E000 // Interrupt 73 Priority Mask 627 #define NVIC_PRI18_INTA_M 0x000000E0 // Interrupt 72 Priority Mask 628 #define NVIC_PRI18_INTD_S 29 629 #define NVIC_PRI18_INTC_S 21 630 #define NVIC_PRI18_INTB_S 13 631 #define NVIC_PRI18_INTA_S 5 638 #define NVIC_PRI19_INTD_M 0xE0000000 // Interrupt 79 Priority Mask 639 #define NVIC_PRI19_INTC_M 0x00E00000 // Interrupt 78 Priority Mask 640 #define NVIC_PRI19_INTB_M 0x0000E000 // Interrupt 77 Priority Mask 641 #define NVIC_PRI19_INTA_M 0x000000E0 // Interrupt 76 Priority Mask 642 #define NVIC_PRI19_INTD_S 29 643 #define NVIC_PRI19_INTC_S 21 644 #define NVIC_PRI19_INTB_S 13 645 #define NVIC_PRI19_INTA_S 5 652 #define NVIC_PRI20_INTD_M 0xE0000000 // Interrupt 83 Priority Mask 653 #define NVIC_PRI20_INTC_M 0x00E00000 // Interrupt 82 Priority Mask 654 #define NVIC_PRI20_INTB_M 0x0000E000 // Interrupt 81 Priority Mask 655 #define NVIC_PRI20_INTA_M 0x000000E0 // Interrupt 80 Priority Mask 656 #define NVIC_PRI20_INTD_S 29 657 #define NVIC_PRI20_INTC_S 21 658 #define NVIC_PRI20_INTB_S 13 659 #define NVIC_PRI20_INTA_S 5 666 #define NVIC_PRI21_INTD_M 0xE0000000 // Interrupt 87 Priority Mask 667 #define NVIC_PRI21_INTC_M 0x00E00000 // Interrupt 86 Priority Mask 668 #define NVIC_PRI21_INTB_M 0x0000E000 // Interrupt 85 Priority Mask 669 #define NVIC_PRI21_INTA_M 0x000000E0 // Interrupt 84 Priority Mask 670 #define NVIC_PRI21_INTD_S 29 671 #define NVIC_PRI21_INTC_S 21 672 #define NVIC_PRI21_INTB_S 13 673 #define NVIC_PRI21_INTA_S 5 680 #define NVIC_PRI22_INTD_M 0xE0000000 // Interrupt 91 Priority Mask 681 #define NVIC_PRI22_INTC_M 0x00E00000 // Interrupt 90 Priority Mask 682 #define NVIC_PRI22_INTB_M 0x0000E000 // Interrupt 89 Priority Mask 683 #define NVIC_PRI22_INTA_M 0x000000E0 // Interrupt 88 Priority Mask 684 #define NVIC_PRI22_INTD_S 29 685 #define NVIC_PRI22_INTC_S 21 686 #define NVIC_PRI22_INTB_S 13 687 #define NVIC_PRI22_INTA_S 5 694 #define NVIC_PRI23_INTD_M 0xE0000000 // Interrupt 95 Priority Mask 695 #define NVIC_PRI23_INTC_M 0x00E00000 // Interrupt 94 Priority Mask 696 #define NVIC_PRI23_INTB_M 0x0000E000 // Interrupt 93 Priority Mask 697 #define NVIC_PRI23_INTA_M 0x000000E0 // Interrupt 92 Priority Mask 698 #define NVIC_PRI23_INTD_S 29 699 #define NVIC_PRI23_INTC_S 21 700 #define NVIC_PRI23_INTB_S 13 701 #define NVIC_PRI23_INTA_S 5 708 #define NVIC_PRI24_INTD_M 0xE0000000 // Interrupt 99 Priority Mask 709 #define NVIC_PRI24_INTC_M 0x00E00000 // Interrupt 98 Priority Mask 710 #define NVIC_PRI24_INTB_M 0x0000E000 // Interrupt 97 Priority Mask 711 #define NVIC_PRI24_INTA_M 0x000000E0 // Interrupt 96 Priority Mask 712 #define NVIC_PRI24_INTD_S 29 713 #define NVIC_PRI24_INTC_S 21 714 #define NVIC_PRI24_INTB_S 13 715 #define NVIC_PRI24_INTA_S 5 722 #define NVIC_PRI25_INTD_M 0xE0000000 // Interrupt 103 Priority Mask 723 #define NVIC_PRI25_INTC_M 0x00E00000 // Interrupt 102 Priority Mask 724 #define NVIC_PRI25_INTB_M 0x0000E000 // Interrupt 101 Priority Mask 725 #define NVIC_PRI25_INTA_M 0x000000E0 // Interrupt 100 Priority Mask 726 #define NVIC_PRI25_INTD_S 29 727 #define NVIC_PRI25_INTC_S 21 728 #define NVIC_PRI25_INTB_S 13 729 #define NVIC_PRI25_INTA_S 5 736 #define NVIC_PRI26_INTD_M 0xE0000000 // Interrupt 107 Priority Mask 737 #define NVIC_PRI26_INTC_M 0x00E00000 // Interrupt 106 Priority Mask 738 #define NVIC_PRI26_INTB_M 0x0000E000 // Interrupt 105 Priority Mask 739 #define NVIC_PRI26_INTA_M 0x000000E0 // Interrupt 104 Priority Mask 740 #define NVIC_PRI26_INTD_S 29 741 #define NVIC_PRI26_INTC_S 21 742 #define NVIC_PRI26_INTB_S 13 743 #define NVIC_PRI26_INTA_S 5 750 #define NVIC_PRI27_INTD_M 0xE0000000 // Interrupt 111 Priority Mask 751 #define NVIC_PRI27_INTC_M 0x00E00000 // Interrupt 110 Priority Mask 752 #define NVIC_PRI27_INTB_M 0x0000E000 // Interrupt 109 Priority Mask 753 #define NVIC_PRI27_INTA_M 0x000000E0 // Interrupt 108 Priority Mask 754 #define NVIC_PRI27_INTD_S 29 755 #define NVIC_PRI27_INTC_S 21 756 #define NVIC_PRI27_INTB_S 13 757 #define NVIC_PRI27_INTA_S 5 764 #define NVIC_PRI28_INTD_M 0xE0000000 // Interrupt 115 Priority Mask 765 #define NVIC_PRI28_INTC_M 0x00E00000 // Interrupt 114 Priority Mask 766 #define NVIC_PRI28_INTB_M 0x0000E000 // Interrupt 113 Priority Mask 767 #define NVIC_PRI28_INTA_M 0x000000E0 // Interrupt 112 Priority Mask 768 #define NVIC_PRI28_INTD_S 29 769 #define NVIC_PRI28_INTC_S 21 770 #define NVIC_PRI28_INTB_S 13 771 #define NVIC_PRI28_INTA_S 5 778 #define NVIC_PRI29_INTD_M 0xE0000000 // Interrupt 119 Priority Mask 779 #define NVIC_PRI29_INTC_M 0x00E00000 // Interrupt 118 Priority Mask 780 #define NVIC_PRI29_INTB_M 0x0000E000 // Interrupt 117 Priority Mask 781 #define NVIC_PRI29_INTA_M 0x000000E0 // Interrupt 116 Priority Mask 782 #define NVIC_PRI29_INTD_S 29 783 #define NVIC_PRI29_INTC_S 21 784 #define NVIC_PRI29_INTB_S 13 785 #define NVIC_PRI29_INTA_S 5 792 #define NVIC_PRI30_INTD_M 0xE0000000 // Interrupt 123 Priority Mask 793 #define NVIC_PRI30_INTC_M 0x00E00000 // Interrupt 122 Priority Mask 794 #define NVIC_PRI30_INTB_M 0x0000E000 // Interrupt 121 Priority Mask 795 #define NVIC_PRI30_INTA_M 0x000000E0 // Interrupt 120 Priority Mask 796 #define NVIC_PRI30_INTD_S 29 797 #define NVIC_PRI30_INTC_S 21 798 #define NVIC_PRI30_INTB_S 13 799 #define NVIC_PRI30_INTA_S 5 806 #define NVIC_PRI31_INTD_M 0xE0000000 // Interrupt 127 Priority Mask 807 #define NVIC_PRI31_INTC_M 0x00E00000 // Interrupt 126 Priority Mask 808 #define NVIC_PRI31_INTB_M 0x0000E000 // Interrupt 125 Priority Mask 809 #define NVIC_PRI31_INTA_M 0x000000E0 // Interrupt 124 Priority Mask 810 #define NVIC_PRI31_INTD_S 29 811 #define NVIC_PRI31_INTC_S 21 812 #define NVIC_PRI31_INTB_S 13 813 #define NVIC_PRI31_INTA_S 5 820 #define NVIC_PRI32_INTD_M 0xE0000000 // Interrupt 131 Priority Mask 821 #define NVIC_PRI32_INTC_M 0x00E00000 // Interrupt 130 Priority Mask 822 #define NVIC_PRI32_INTB_M 0x0000E000 // Interrupt 129 Priority Mask 823 #define NVIC_PRI32_INTA_M 0x000000E0 // Interrupt 128 Priority Mask 824 #define NVIC_PRI32_INTD_S 29 825 #define NVIC_PRI32_INTC_S 21 826 #define NVIC_PRI32_INTB_S 13 827 #define NVIC_PRI32_INTA_S 5 834 #define NVIC_PRI33_INTD_M 0xE0000000 // Interrupt Priority for Interrupt 836 #define NVIC_PRI33_INTC_M 0x00E00000 // Interrupt Priority for Interrupt 838 #define NVIC_PRI33_INTB_M 0x0000E000 // Interrupt Priority for Interrupt 840 #define NVIC_PRI33_INTA_M 0x000000E0 // Interrupt Priority for Interrupt 842 #define NVIC_PRI33_INTD_S 29 843 #define NVIC_PRI33_INTC_S 21 844 #define NVIC_PRI33_INTB_S 13 845 #define NVIC_PRI33_INTA_S 5 852 #define NVIC_PRI34_INTD_M 0xE0000000 // Interrupt Priority for Interrupt 854 #define NVIC_PRI34_INTC_M 0x00E00000 // Interrupt Priority for Interrupt 856 #define NVIC_PRI34_INTB_M 0x0000E000 // Interrupt Priority for Interrupt 858 #define NVIC_PRI34_INTA_M 0x000000E0 // Interrupt Priority for Interrupt 860 #define NVIC_PRI34_INTD_S 29 861 #define NVIC_PRI34_INTC_S 21 862 #define NVIC_PRI34_INTB_S 13 863 #define NVIC_PRI34_INTA_S 5 870 #define NVIC_CPUID_IMP_M 0xFF000000 // Implementer Code 871 #define NVIC_CPUID_IMP_ARM 0x41000000 // ARM 872 #define NVIC_CPUID_VAR_M 0x00F00000 // Variant Number 873 #define NVIC_CPUID_CON_M 0x000F0000 // Constant 874 #define NVIC_CPUID_PARTNO_M 0x0000FFF0 // Part Number 875 #define NVIC_CPUID_PARTNO_CM4 0x0000C240 // Cortex-M4 processor 876 #define NVIC_CPUID_REV_M 0x0000000F // Revision Number 883 #define NVIC_INT_CTRL_NMI_SET 0x80000000 // NMI Set Pending 884 #define NVIC_INT_CTRL_PEND_SV 0x10000000 // PendSV Set Pending 885 #define NVIC_INT_CTRL_UNPEND_SV 0x08000000 // PendSV Clear Pending 886 #define NVIC_INT_CTRL_PENDSTSET 0x04000000 // SysTick Set Pending 887 #define NVIC_INT_CTRL_PENDSTCLR 0x02000000 // SysTick Clear Pending 888 #define NVIC_INT_CTRL_ISR_PRE 0x00800000 // Debug Interrupt Handling 889 #define NVIC_INT_CTRL_ISR_PEND 0x00400000 // Interrupt Pending 890 #define NVIC_INT_CTRL_VEC_PEN_M 0x000FF000 // Interrupt Pending Vector Number 891 #define NVIC_INT_CTRL_VEC_PEN_NMI \ 893 #define NVIC_INT_CTRL_VEC_PEN_HARD \ 894 0x00003000 // Hard fault 895 #define NVIC_INT_CTRL_VEC_PEN_MEM \ 896 0x00004000 // Memory management fault 897 #define NVIC_INT_CTRL_VEC_PEN_BUS \ 898 0x00005000 // Bus fault 899 #define NVIC_INT_CTRL_VEC_PEN_USG \ 900 0x00006000 // Usage fault 901 #define NVIC_INT_CTRL_VEC_PEN_SVC \ 903 #define NVIC_INT_CTRL_VEC_PEN_PNDSV \ 905 #define NVIC_INT_CTRL_VEC_PEN_TICK \ 906 0x0000F000 // SysTick 907 #define NVIC_INT_CTRL_RET_BASE 0x00000800 // Return to Base 908 #define NVIC_INT_CTRL_VEC_ACT_M 0x000000FF // Interrupt Pending Vector Number 909 #define NVIC_INT_CTRL_VEC_ACT_S 0 916 #define NVIC_VTABLE_OFFSET_M 0xFFFFFC00 // Vector Table Offset 917 #define NVIC_VTABLE_OFFSET_S 10 924 #define NVIC_APINT_VECTKEY_M 0xFFFF0000 // Register Key 925 #define NVIC_APINT_VECTKEY 0x05FA0000 // Vector key 926 #define NVIC_APINT_ENDIANESS 0x00008000 // Data Endianess 927 #define NVIC_APINT_PRIGROUP_M 0x00000700 // Interrupt Priority Grouping 928 #define NVIC_APINT_PRIGROUP_7_1 0x00000000 // Priority group 7.1 split 929 #define NVIC_APINT_PRIGROUP_6_2 0x00000100 // Priority group 6.2 split 930 #define NVIC_APINT_PRIGROUP_5_3 0x00000200 // Priority group 5.3 split 931 #define NVIC_APINT_PRIGROUP_4_4 0x00000300 // Priority group 4.4 split 932 #define NVIC_APINT_PRIGROUP_3_5 0x00000400 // Priority group 3.5 split 933 #define NVIC_APINT_PRIGROUP_2_6 0x00000500 // Priority group 2.6 split 934 #define NVIC_APINT_PRIGROUP_1_7 0x00000600 // Priority group 1.7 split 935 #define NVIC_APINT_PRIGROUP_0_8 0x00000700 // Priority group 0.8 split 936 #define NVIC_APINT_SYSRESETREQ 0x00000004 // System Reset Request 937 #define NVIC_APINT_VECT_CLR_ACT 0x00000002 // Clear Active NMI / Fault 938 #define NVIC_APINT_VECT_RESET 0x00000001 // System Reset 945 #define NVIC_SYS_CTRL_SEVONPEND 0x00000010 // Wake Up on Pending 946 #define NVIC_SYS_CTRL_SLEEPDEEP 0x00000004 // Deep Sleep Enable 947 #define NVIC_SYS_CTRL_SLEEPEXIT 0x00000002 // Sleep on ISR Exit 954 #define NVIC_CFG_CTRL_STKALIGN 0x00000200 // Stack Alignment on Exception 956 #define NVIC_CFG_CTRL_BFHFNMIGN 0x00000100 // Ignore Bus Fault in NMI and 958 #define NVIC_CFG_CTRL_DIV0 0x00000010 // Trap on Divide by 0 959 #define NVIC_CFG_CTRL_UNALIGNED 0x00000008 // Trap on Unaligned Access 960 #define NVIC_CFG_CTRL_MAIN_PEND 0x00000002 // Allow Main Interrupt Trigger 961 #define NVIC_CFG_CTRL_BASE_THR 0x00000001 // Thread State Control 968 #define NVIC_SYS_PRI1_USAGE_M 0x00E00000 // Usage Fault Priority 969 #define NVIC_SYS_PRI1_BUS_M 0x0000E000 // Bus Fault Priority 970 #define NVIC_SYS_PRI1_MEM_M 0x000000E0 // Memory Management Fault Priority 971 #define NVIC_SYS_PRI1_USAGE_S 21 972 #define NVIC_SYS_PRI1_BUS_S 13 973 #define NVIC_SYS_PRI1_MEM_S 5 980 #define NVIC_SYS_PRI2_SVC_M 0xE0000000 // SVCall Priority 981 #define NVIC_SYS_PRI2_SVC_S 29 988 #define NVIC_SYS_PRI3_TICK_M 0xE0000000 // SysTick Exception Priority 989 #define NVIC_SYS_PRI3_PENDSV_M 0x00E00000 // PendSV Priority 990 #define NVIC_SYS_PRI3_DEBUG_M 0x000000E0 // Debug Priority 991 #define NVIC_SYS_PRI3_TICK_S 29 992 #define NVIC_SYS_PRI3_PENDSV_S 21 993 #define NVIC_SYS_PRI3_DEBUG_S 5 1001 #define NVIC_SYS_HND_CTRL_USAGE 0x00040000 // Usage Fault Enable 1002 #define NVIC_SYS_HND_CTRL_BUS 0x00020000 // Bus Fault Enable 1003 #define NVIC_SYS_HND_CTRL_MEM 0x00010000 // Memory Management Fault Enable 1004 #define NVIC_SYS_HND_CTRL_SVC 0x00008000 // SVC Call Pending 1005 #define NVIC_SYS_HND_CTRL_BUSP 0x00004000 // Bus Fault Pending 1006 #define NVIC_SYS_HND_CTRL_MEMP 0x00002000 // Memory Management Fault Pending 1007 #define NVIC_SYS_HND_CTRL_USAGEP \ 1008 0x00001000 // Usage Fault Pending 1009 #define NVIC_SYS_HND_CTRL_TICK 0x00000800 // SysTick Exception Active 1010 #define NVIC_SYS_HND_CTRL_PNDSV 0x00000400 // PendSV Exception Active 1011 #define NVIC_SYS_HND_CTRL_MON 0x00000100 // Debug Monitor Active 1012 #define NVIC_SYS_HND_CTRL_SVCA 0x00000080 // SVC Call Active 1013 #define NVIC_SYS_HND_CTRL_USGA 0x00000008 // Usage Fault Active 1014 #define NVIC_SYS_HND_CTRL_BUSA 0x00000002 // Bus Fault Active 1015 #define NVIC_SYS_HND_CTRL_MEMA 0x00000001 // Memory Management Fault Active 1023 #define NVIC_FAULT_STAT_DIV0 0x02000000 // Divide-by-Zero Usage Fault 1024 #define NVIC_FAULT_STAT_UNALIGN 0x01000000 // Unaligned Access Usage Fault 1025 #define NVIC_FAULT_STAT_NOCP 0x00080000 // No Coprocessor Usage Fault 1026 #define NVIC_FAULT_STAT_INVPC 0x00040000 // Invalid PC Load Usage Fault 1027 #define NVIC_FAULT_STAT_INVSTAT 0x00020000 // Invalid State Usage Fault 1028 #define NVIC_FAULT_STAT_UNDEF 0x00010000 // Undefined Instruction Usage 1030 #define NVIC_FAULT_STAT_BFARV 0x00008000 // Bus Fault Address Register Valid 1031 #define NVIC_FAULT_STAT_BLSPERR 0x00002000 // Bus Fault on Floating-Point Lazy 1033 #define NVIC_FAULT_STAT_BSTKE 0x00001000 // Stack Bus Fault 1034 #define NVIC_FAULT_STAT_BUSTKE 0x00000800 // Unstack Bus Fault 1035 #define NVIC_FAULT_STAT_IMPRE 0x00000400 // Imprecise Data Bus Error 1036 #define NVIC_FAULT_STAT_PRECISE 0x00000200 // Precise Data Bus Error 1037 #define NVIC_FAULT_STAT_IBUS 0x00000100 // Instruction Bus Error 1038 #define NVIC_FAULT_STAT_MMARV 0x00000080 // Memory Management Fault Address 1040 #define NVIC_FAULT_STAT_MLSPERR 0x00000020 // Memory Management Fault on 1043 #define NVIC_FAULT_STAT_MSTKE 0x00000010 // Stack Access Violation 1044 #define NVIC_FAULT_STAT_MUSTKE 0x00000008 // Unstack Access Violation 1045 #define NVIC_FAULT_STAT_DERR 0x00000002 // Data Access Violation 1046 #define NVIC_FAULT_STAT_IERR 0x00000001 // Instruction Access Violation 1054 #define NVIC_HFAULT_STAT_DBG 0x80000000 // Debug Event 1055 #define NVIC_HFAULT_STAT_FORCED 0x40000000 // Forced Hard Fault 1056 #define NVIC_HFAULT_STAT_VECT 0x00000002 // Vector Table Read Fault 1064 #define NVIC_DEBUG_STAT_EXTRNL 0x00000010 // EDBGRQ asserted 1065 #define NVIC_DEBUG_STAT_VCATCH 0x00000008 // Vector catch 1066 #define NVIC_DEBUG_STAT_DWTTRAP 0x00000004 // DWT match 1067 #define NVIC_DEBUG_STAT_BKPT 0x00000002 // Breakpoint instruction 1068 #define NVIC_DEBUG_STAT_HALTED 0x00000001 // Halt request 1075 #define NVIC_MM_ADDR_M 0xFFFFFFFF // Fault Address 1076 #define NVIC_MM_ADDR_S 0 1084 #define NVIC_FAULT_ADDR_M 0xFFFFFFFF // Fault Address 1085 #define NVIC_FAULT_ADDR_S 0 1092 #define NVIC_CPAC_CP11_M 0x00C00000 // CP11 Coprocessor Access 1094 #define NVIC_CPAC_CP11_DIS 0x00000000 // Access Denied 1095 #define NVIC_CPAC_CP11_PRIV 0x00400000 // Privileged Access Only 1096 #define NVIC_CPAC_CP11_FULL 0x00C00000 // Full Access 1097 #define NVIC_CPAC_CP10_M 0x00300000 // CP10 Coprocessor Access 1099 #define NVIC_CPAC_CP10_DIS 0x00000000 // Access Denied 1100 #define NVIC_CPAC_CP10_PRIV 0x00100000 // Privileged Access Only 1101 #define NVIC_CPAC_CP10_FULL 0x00300000 // Full Access 1108 #define NVIC_MPU_TYPE_IREGION_M 0x00FF0000 // Number of I Regions 1109 #define NVIC_MPU_TYPE_DREGION_M 0x0000FF00 // Number of D Regions 1110 #define NVIC_MPU_TYPE_SEPARATE 0x00000001 // Separate or Unified MPU 1111 #define NVIC_MPU_TYPE_IREGION_S 16 1112 #define NVIC_MPU_TYPE_DREGION_S 8 1119 #define NVIC_MPU_CTRL_PRIVDEFEN 0x00000004 // MPU Default Region 1120 #define NVIC_MPU_CTRL_HFNMIENA 0x00000002 // MPU Enabled During Faults 1121 #define NVIC_MPU_CTRL_ENABLE 0x00000001 // MPU Enable 1129 #define NVIC_MPU_NUMBER_M 0x00000007 // MPU Region to Access 1130 #define NVIC_MPU_NUMBER_S 0 1137 #define NVIC_MPU_BASE_ADDR_M 0xFFFFFFE0 // Base Address Mask 1138 #define NVIC_MPU_BASE_VALID 0x00000010 // Region Number Valid 1139 #define NVIC_MPU_BASE_REGION_M 0x00000007 // Region Number 1140 #define NVIC_MPU_BASE_ADDR_S 5 1141 #define NVIC_MPU_BASE_REGION_S 0 1148 #define NVIC_MPU_ATTR_XN 0x10000000 // Instruction Access Disable 1149 #define NVIC_MPU_ATTR_AP_M 0x07000000 // Access Privilege 1150 #define NVIC_MPU_ATTR_AP_NO_NO 0x00000000 // prv: no access, usr: no access 1151 #define NVIC_MPU_ATTR_AP_RW_NO 0x01000000 // prv: rw, usr: none 1152 #define NVIC_MPU_ATTR_AP_RW_RO 0x02000000 // prv: rw, usr: read-only 1153 #define NVIC_MPU_ATTR_AP_RW_RW 0x03000000 // prv: rw, usr: rw 1154 #define NVIC_MPU_ATTR_AP_RO_NO 0x05000000 // prv: ro, usr: none 1155 #define NVIC_MPU_ATTR_AP_RO_RO 0x06000000 // prv: ro, usr: ro 1156 #define NVIC_MPU_ATTR_TEX_M 0x00380000 // Type Extension Mask 1157 #define NVIC_MPU_ATTR_SHAREABLE 0x00040000 // Shareable 1158 #define NVIC_MPU_ATTR_CACHEABLE 0x00020000 // Cacheable 1159 #define NVIC_MPU_ATTR_BUFFRABLE 0x00010000 // Bufferable 1160 #define NVIC_MPU_ATTR_SRD_M 0x0000FF00 // Subregion Disable Bits 1161 #define NVIC_MPU_ATTR_SRD_0 0x00000100 // Sub-region 0 disable 1162 #define NVIC_MPU_ATTR_SRD_1 0x00000200 // Sub-region 1 disable 1163 #define NVIC_MPU_ATTR_SRD_2 0x00000400 // Sub-region 2 disable 1164 #define NVIC_MPU_ATTR_SRD_3 0x00000800 // Sub-region 3 disable 1165 #define NVIC_MPU_ATTR_SRD_4 0x00001000 // Sub-region 4 disable 1166 #define NVIC_MPU_ATTR_SRD_5 0x00002000 // Sub-region 5 disable 1167 #define NVIC_MPU_ATTR_SRD_6 0x00004000 // Sub-region 6 disable 1168 #define NVIC_MPU_ATTR_SRD_7 0x00008000 // Sub-region 7 disable 1169 #define NVIC_MPU_ATTR_SIZE_M 0x0000003E // Region Size Mask 1170 #define NVIC_MPU_ATTR_SIZE_32B 0x00000008 // Region size 32 bytes 1171 #define NVIC_MPU_ATTR_SIZE_64B 0x0000000A // Region size 64 bytes 1172 #define NVIC_MPU_ATTR_SIZE_128B 0x0000000C // Region size 128 bytes 1173 #define NVIC_MPU_ATTR_SIZE_256B 0x0000000E // Region size 256 bytes 1174 #define NVIC_MPU_ATTR_SIZE_512B 0x00000010 // Region size 512 bytes 1175 #define NVIC_MPU_ATTR_SIZE_1K 0x00000012 // Region size 1 Kbytes 1176 #define NVIC_MPU_ATTR_SIZE_2K 0x00000014 // Region size 2 Kbytes 1177 #define NVIC_MPU_ATTR_SIZE_4K 0x00000016 // Region size 4 Kbytes 1178 #define NVIC_MPU_ATTR_SIZE_8K 0x00000018 // Region size 8 Kbytes 1179 #define NVIC_MPU_ATTR_SIZE_16K 0x0000001A // Region size 16 Kbytes 1180 #define NVIC_MPU_ATTR_SIZE_32K 0x0000001C // Region size 32 Kbytes 1181 #define NVIC_MPU_ATTR_SIZE_64K 0x0000001E // Region size 64 Kbytes 1182 #define NVIC_MPU_ATTR_SIZE_128K 0x00000020 // Region size 128 Kbytes 1183 #define NVIC_MPU_ATTR_SIZE_256K 0x00000022 // Region size 256 Kbytes 1184 #define NVIC_MPU_ATTR_SIZE_512K 0x00000024 // Region size 512 Kbytes 1185 #define NVIC_MPU_ATTR_SIZE_1M 0x00000026 // Region size 1 Mbytes 1186 #define NVIC_MPU_ATTR_SIZE_2M 0x00000028 // Region size 2 Mbytes 1187 #define NVIC_MPU_ATTR_SIZE_4M 0x0000002A // Region size 4 Mbytes 1188 #define NVIC_MPU_ATTR_SIZE_8M 0x0000002C // Region size 8 Mbytes 1189 #define NVIC_MPU_ATTR_SIZE_16M 0x0000002E // Region size 16 Mbytes 1190 #define NVIC_MPU_ATTR_SIZE_32M 0x00000030 // Region size 32 Mbytes 1191 #define NVIC_MPU_ATTR_SIZE_64M 0x00000032 // Region size 64 Mbytes 1192 #define NVIC_MPU_ATTR_SIZE_128M 0x00000034 // Region size 128 Mbytes 1193 #define NVIC_MPU_ATTR_SIZE_256M 0x00000036 // Region size 256 Mbytes 1194 #define NVIC_MPU_ATTR_SIZE_512M 0x00000038 // Region size 512 Mbytes 1195 #define NVIC_MPU_ATTR_SIZE_1G 0x0000003A // Region size 1 Gbytes 1196 #define NVIC_MPU_ATTR_SIZE_2G 0x0000003C // Region size 2 Gbytes 1197 #define NVIC_MPU_ATTR_SIZE_4G 0x0000003E // Region size 4 Gbytes 1198 #define NVIC_MPU_ATTR_ENABLE 0x00000001 // Region Enable 1205 #define NVIC_MPU_BASE1_ADDR_M 0xFFFFFFE0 // Base Address Mask 1206 #define NVIC_MPU_BASE1_VALID 0x00000010 // Region Number Valid 1207 #define NVIC_MPU_BASE1_REGION_M 0x00000007 // Region Number 1208 #define NVIC_MPU_BASE1_ADDR_S 5 1209 #define NVIC_MPU_BASE1_REGION_S 0 1216 #define NVIC_MPU_ATTR1_XN 0x10000000 // Instruction Access Disable 1217 #define NVIC_MPU_ATTR1_AP_M 0x07000000 // Access Privilege 1218 #define NVIC_MPU_ATTR1_TEX_M 0x00380000 // Type Extension Mask 1219 #define NVIC_MPU_ATTR1_SHAREABLE \ 1220 0x00040000 // Shareable 1221 #define NVIC_MPU_ATTR1_CACHEABLE \ 1222 0x00020000 // Cacheable 1223 #define NVIC_MPU_ATTR1_BUFFRABLE \ 1224 0x00010000 // Bufferable 1225 #define NVIC_MPU_ATTR1_SRD_M 0x0000FF00 // Subregion Disable Bits 1226 #define NVIC_MPU_ATTR1_SIZE_M 0x0000003E // Region Size Mask 1227 #define NVIC_MPU_ATTR1_ENABLE 0x00000001 // Region Enable 1234 #define NVIC_MPU_BASE2_ADDR_M 0xFFFFFFE0 // Base Address Mask 1235 #define NVIC_MPU_BASE2_VALID 0x00000010 // Region Number Valid 1236 #define NVIC_MPU_BASE2_REGION_M 0x00000007 // Region Number 1237 #define NVIC_MPU_BASE2_ADDR_S 5 1238 #define NVIC_MPU_BASE2_REGION_S 0 1245 #define NVIC_MPU_ATTR2_XN 0x10000000 // Instruction Access Disable 1246 #define NVIC_MPU_ATTR2_AP_M 0x07000000 // Access Privilege 1247 #define NVIC_MPU_ATTR2_TEX_M 0x00380000 // Type Extension Mask 1248 #define NVIC_MPU_ATTR2_SHAREABLE \ 1249 0x00040000 // Shareable 1250 #define NVIC_MPU_ATTR2_CACHEABLE \ 1251 0x00020000 // Cacheable 1252 #define NVIC_MPU_ATTR2_BUFFRABLE \ 1253 0x00010000 // Bufferable 1254 #define NVIC_MPU_ATTR2_SRD_M 0x0000FF00 // Subregion Disable Bits 1255 #define NVIC_MPU_ATTR2_SIZE_M 0x0000003E // Region Size Mask 1256 #define NVIC_MPU_ATTR2_ENABLE 0x00000001 // Region Enable 1263 #define NVIC_MPU_BASE3_ADDR_M 0xFFFFFFE0 // Base Address Mask 1264 #define NVIC_MPU_BASE3_VALID 0x00000010 // Region Number Valid 1265 #define NVIC_MPU_BASE3_REGION_M 0x00000007 // Region Number 1266 #define NVIC_MPU_BASE3_ADDR_S 5 1267 #define NVIC_MPU_BASE3_REGION_S 0 1274 #define NVIC_MPU_ATTR3_XN 0x10000000 // Instruction Access Disable 1275 #define NVIC_MPU_ATTR3_AP_M 0x07000000 // Access Privilege 1276 #define NVIC_MPU_ATTR3_TEX_M 0x00380000 // Type Extension Mask 1277 #define NVIC_MPU_ATTR3_SHAREABLE \ 1278 0x00040000 // Shareable 1279 #define NVIC_MPU_ATTR3_CACHEABLE \ 1280 0x00020000 // Cacheable 1281 #define NVIC_MPU_ATTR3_BUFFRABLE \ 1282 0x00010000 // Bufferable 1283 #define NVIC_MPU_ATTR3_SRD_M 0x0000FF00 // Subregion Disable Bits 1284 #define NVIC_MPU_ATTR3_SIZE_M 0x0000003E // Region Size Mask 1285 #define NVIC_MPU_ATTR3_ENABLE 0x00000001 // Region Enable 1292 #define NVIC_DBG_CTRL_DBGKEY_M 0xFFFF0000 // Debug key mask 1293 #define NVIC_DBG_CTRL_DBGKEY 0xA05F0000 // Debug key 1294 #define NVIC_DBG_CTRL_S_RESET_ST \ 1295 0x02000000 // Core has reset since last read 1296 #define NVIC_DBG_CTRL_S_RETIRE_ST \ 1297 0x01000000 // Core has executed insruction 1299 #define NVIC_DBG_CTRL_S_LOCKUP 0x00080000 // Core is locked up 1300 #define NVIC_DBG_CTRL_S_SLEEP 0x00040000 // Core is sleeping 1301 #define NVIC_DBG_CTRL_S_HALT 0x00020000 // Core status on halt 1302 #define NVIC_DBG_CTRL_S_REGRDY 0x00010000 // Register read/write available 1303 #define NVIC_DBG_CTRL_C_SNAPSTALL \ 1304 0x00000020 // Breaks a stalled load/store 1305 #define NVIC_DBG_CTRL_C_MASKINT 0x00000008 // Mask interrupts when stepping 1306 #define NVIC_DBG_CTRL_C_STEP 0x00000004 // Step the core 1307 #define NVIC_DBG_CTRL_C_HALT 0x00000002 // Halt the core 1308 #define NVIC_DBG_CTRL_C_DEBUGEN 0x00000001 // Enable debug 1315 #define NVIC_DBG_XFER_REG_WNR 0x00010000 // Write or not read 1316 #define NVIC_DBG_XFER_REG_SEL_M 0x0000001F // Register 1317 #define NVIC_DBG_XFER_REG_R0 0x00000000 // Register R0 1318 #define NVIC_DBG_XFER_REG_R1 0x00000001 // Register R1 1319 #define NVIC_DBG_XFER_REG_R2 0x00000002 // Register R2 1320 #define NVIC_DBG_XFER_REG_R3 0x00000003 // Register R3 1321 #define NVIC_DBG_XFER_REG_R4 0x00000004 // Register R4 1322 #define NVIC_DBG_XFER_REG_R5 0x00000005 // Register R5 1323 #define NVIC_DBG_XFER_REG_R6 0x00000006 // Register R6 1324 #define NVIC_DBG_XFER_REG_R7 0x00000007 // Register R7 1325 #define NVIC_DBG_XFER_REG_R8 0x00000008 // Register R8 1326 #define NVIC_DBG_XFER_REG_R9 0x00000009 // Register R9 1327 #define NVIC_DBG_XFER_REG_R10 0x0000000A // Register R10 1328 #define NVIC_DBG_XFER_REG_R11 0x0000000B // Register R11 1329 #define NVIC_DBG_XFER_REG_R12 0x0000000C // Register R12 1330 #define NVIC_DBG_XFER_REG_R13 0x0000000D // Register R13 1331 #define NVIC_DBG_XFER_REG_R14 0x0000000E // Register R14 1332 #define NVIC_DBG_XFER_REG_R15 0x0000000F // Register R15 1333 #define NVIC_DBG_XFER_REG_FLAGS 0x00000010 // xPSR/Flags register 1334 #define NVIC_DBG_XFER_REG_MSP 0x00000011 // Main SP 1335 #define NVIC_DBG_XFER_REG_PSP 0x00000012 // Process SP 1336 #define NVIC_DBG_XFER_REG_DSP 0x00000013 // Deep SP 1337 #define NVIC_DBG_XFER_REG_CFBP 0x00000014 // Control/Fault/BasePri/PriMask 1344 #define NVIC_DBG_DATA_M 0xFFFFFFFF // Data temporary cache 1345 #define NVIC_DBG_DATA_S 0 1352 #define NVIC_DBG_INT_HARDERR 0x00000400 // Debug trap on hard fault 1353 #define NVIC_DBG_INT_INTERR 0x00000200 // Debug trap on interrupt errors 1354 #define NVIC_DBG_INT_BUSERR 0x00000100 // Debug trap on bus error 1355 #define NVIC_DBG_INT_STATERR 0x00000080 // Debug trap on usage fault state 1356 #define NVIC_DBG_INT_CHKERR 0x00000040 // Debug trap on usage fault check 1357 #define NVIC_DBG_INT_NOCPERR 0x00000020 // Debug trap on coprocessor error 1358 #define NVIC_DBG_INT_MMERR 0x00000010 // Debug trap on mem manage fault 1359 #define NVIC_DBG_INT_RESET 0x00000008 // Core reset status 1360 #define NVIC_DBG_INT_RSTPENDCLR 0x00000004 // Clear pending core reset 1361 #define NVIC_DBG_INT_RSTPENDING 0x00000002 // Core reset is pending 1362 #define NVIC_DBG_INT_RSTVCATCH 0x00000001 // Reset vector catch 1369 #define NVIC_SW_TRIG_INTID_M 0x000000FF // Interrupt ID 1370 #define NVIC_SW_TRIG_INTID_S 0 1377 #define NVIC_FPCC_ASPEN 0x80000000 // Automatic State Preservation 1379 #define NVIC_FPCC_LSPEN 0x40000000 // Lazy State Preservation Enable 1380 #define NVIC_FPCC_MONRDY 0x00000100 // Monitor Ready 1381 #define NVIC_FPCC_BFRDY 0x00000040 // Bus Fault Ready 1382 #define NVIC_FPCC_MMRDY 0x00000020 // Memory Management Fault Ready 1383 #define NVIC_FPCC_HFRDY 0x00000010 // Hard Fault Ready 1384 #define NVIC_FPCC_THREAD 0x00000008 // Thread Mode 1385 #define NVIC_FPCC_USER 0x00000002 // User Privilege Level 1386 #define NVIC_FPCC_LSPACT 0x00000001 // Lazy State Preservation Active 1393 #define NVIC_FPCA_ADDRESS_M 0xFFFFFFF8 // Address 1394 #define NVIC_FPCA_ADDRESS_S 3 1401 #define NVIC_FPDSC_AHP 0x04000000 // AHP Bit Default 1402 #define NVIC_FPDSC_DN 0x02000000 // DN Bit Default 1403 #define NVIC_FPDSC_FZ 0x01000000 // FZ Bit Default 1404 #define NVIC_FPDSC_RMODE_M 0x00C00000 // RMODE Bit Default 1405 #define NVIC_FPDSC_RMODE_RN 0x00000000 // Round to Nearest (RN) mode 1406 #define NVIC_FPDSC_RMODE_RP 0x00400000 // Round towards Plus Infinity (RP) 1408 #define NVIC_FPDSC_RMODE_RM 0x00800000 // Round towards Minus Infinity 1410 #define NVIC_FPDSC_RMODE_RZ 0x00C00000 // Round towards Zero (RZ) mode 1412 #endif // __HW_NVIC_H__
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