hw_hibernate.h
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1 //*****************************************************************************
2 //
3 // hw_hibernate.h - Defines and Macros for the Hibernation module.
4 //
5 // Copyright (c) 2007-2017 Texas Instruments Incorporated. All rights reserved.
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36 //*****************************************************************************
37 
38 #ifndef __HW_HIBERNATE_H__
39 #define __HW_HIBERNATE_H__
40 
41 //*****************************************************************************
42 //
43 // The following are defines for the Hibernation module register addresses.
44 //
45 //*****************************************************************************
46 #define HIB_RTCC 0x400FC000 // Hibernation RTC Counter
47 #define HIB_RTCM0 0x400FC004 // Hibernation RTC Match 0
48 #define HIB_RTCLD 0x400FC00C // Hibernation RTC Load
49 #define HIB_CTL 0x400FC010 // Hibernation Control
50 #define HIB_IM 0x400FC014 // Hibernation Interrupt Mask
51 #define HIB_RIS 0x400FC018 // Hibernation Raw Interrupt Status
52 #define HIB_MIS 0x400FC01C // Hibernation Masked Interrupt
53  // Status
54 #define HIB_IC 0x400FC020 // Hibernation Interrupt Clear
55 #define HIB_RTCT 0x400FC024 // Hibernation RTC Trim
56 #define HIB_RTCSS 0x400FC028 // Hibernation RTC Sub Seconds
57 #define HIB_IO 0x400FC02C // Hibernation IO Configuration
58 #define HIB_DATA 0x400FC030 // Hibernation Data
59 #define HIB_CALCTL 0x400FC300 // Hibernation Calendar Control
60 #define HIB_CAL0 0x400FC310 // Hibernation Calendar 0
61 #define HIB_CAL1 0x400FC314 // Hibernation Calendar 1
62 #define HIB_CALLD0 0x400FC320 // Hibernation Calendar Load 0
63 #define HIB_CALLD1 0x400FC324 // Hibernation Calendar Load
64 #define HIB_CALM0 0x400FC330 // Hibernation Calendar Match 0
65 #define HIB_CALM1 0x400FC334 // Hibernation Calendar Match 1
66 #define HIB_LOCK 0x400FC360 // Hibernation Lock
67 #define HIB_TPCTL 0x400FC400 // HIB Tamper Control
68 #define HIB_TPSTAT 0x400FC404 // HIB Tamper Status
69 #define HIB_TPIO 0x400FC410 // HIB Tamper I/O Control
70 #define HIB_TPLOG0 0x400FC4E0 // HIB Tamper Log 0
71 #define HIB_TPLOG1 0x400FC4E4 // HIB Tamper Log 1
72 #define HIB_TPLOG2 0x400FC4E8 // HIB Tamper Log 2
73 #define HIB_TPLOG3 0x400FC4EC // HIB Tamper Log 3
74 #define HIB_TPLOG4 0x400FC4F0 // HIB Tamper Log 4
75 #define HIB_TPLOG5 0x400FC4F4 // HIB Tamper Log 5
76 #define HIB_TPLOG6 0x400FC4F8 // HIB Tamper Log 6
77 #define HIB_TPLOG7 0x400FC4FC // HIB Tamper Log 7
78 #define HIB_PP 0x400FCFC0 // Hibernation Peripheral
79  // Properties
80 #define HIB_CC 0x400FCFC8 // Hibernation Clock Control
81 
82 //*****************************************************************************
83 //
84 // The following are defines for the bit fields in the HIB_RTCC register.
85 //
86 //*****************************************************************************
87 #define HIB_RTCC_M 0xFFFFFFFF // RTC Counter
88 #define HIB_RTCC_S 0
89 
90 //*****************************************************************************
91 //
92 // The following are defines for the bit fields in the HIB_RTCM0 register.
93 //
94 //*****************************************************************************
95 #define HIB_RTCM0_M 0xFFFFFFFF // RTC Match 0
96 #define HIB_RTCM0_S 0
97 
98 //*****************************************************************************
99 //
100 // The following are defines for the bit fields in the HIB_RTCLD register.
101 //
102 //*****************************************************************************
103 #define HIB_RTCLD_M 0xFFFFFFFF // RTC Load
104 #define HIB_RTCLD_S 0
105 
106 //*****************************************************************************
107 //
108 // The following are defines for the bit fields in the HIB_CTL register.
109 //
110 //*****************************************************************************
111 #define HIB_CTL_WRC 0x80000000 // Write Complete/Capable
112 #define HIB_CTL_RETCLR 0x40000000 // GPIO Retention/Clear
113 #define HIB_CTL_OSCSEL 0x00080000 // Oscillator Select
114 #define HIB_CTL_OSCDRV 0x00020000 // Oscillator Drive Capability
115 #define HIB_CTL_OSCBYP 0x00010000 // Oscillator Bypass
116 #define HIB_CTL_VBATSEL_M 0x00006000 // Select for Low-Battery
117  // Comparator
118 #define HIB_CTL_VBATSEL_1_9V 0x00000000 // 1.9 Volts
119 #define HIB_CTL_VBATSEL_2_1V 0x00002000 // 2.1 Volts (default)
120 #define HIB_CTL_VBATSEL_2_3V 0x00004000 // 2.3 Volts
121 #define HIB_CTL_VBATSEL_2_5V 0x00006000 // 2.5 Volts
122 #define HIB_CTL_BATCHK 0x00000400 // Check Battery Status
123 #define HIB_CTL_BATWKEN 0x00000200 // Wake on Low Battery
124 #define HIB_CTL_VDD3ON 0x00000100 // VDD Powered
125 #define HIB_CTL_VABORT 0x00000080 // Power Cut Abort Enable
126 #define HIB_CTL_CLK32EN 0x00000040 // Clocking Enable
127 #define HIB_CTL_PINWEN 0x00000010 // External Wake Pin Enable
128 #define HIB_CTL_RTCWEN 0x00000008 // RTC Wake-up Enable
129 #define HIB_CTL_HIBREQ 0x00000002 // Hibernation Request
130 #define HIB_CTL_RTCEN 0x00000001 // RTC Timer Enable
131 
132 //*****************************************************************************
133 //
134 // The following are defines for the bit fields in the HIB_IM register.
135 //
136 //*****************************************************************************
137 #define HIB_IM_VDDFAIL 0x00000080 // VDD Fail Interrupt Mask
138 #define HIB_IM_RSTWK 0x00000040 // Reset Pad I/O Wake-Up Interrupt
139  // Mask
140 #define HIB_IM_PADIOWK 0x00000020 // Pad I/O Wake-Up Interrupt Mask
141 #define HIB_IM_WC 0x00000010 // External Write Complete/Capable
142  // Interrupt Mask
143 #define HIB_IM_EXTW 0x00000008 // External Wake-Up Interrupt Mask
144 #define HIB_IM_LOWBAT 0x00000004 // Low Battery Voltage Interrupt
145  // Mask
146 #define HIB_IM_RTCALT0 0x00000001 // RTC Alert 0 Interrupt Mask
147 
148 //*****************************************************************************
149 //
150 // The following are defines for the bit fields in the HIB_RIS register.
151 //
152 //*****************************************************************************
153 #define HIB_RIS_VDDFAIL 0x00000080 // VDD Fail Raw Interrupt Status
154 #define HIB_RIS_RSTWK 0x00000040 // Reset Pad I/O Wake-Up Raw
155  // Interrupt Status
156 #define HIB_RIS_PADIOWK 0x00000020 // Pad I/O Wake-Up Raw Interrupt
157  // Status
158 #define HIB_RIS_WC 0x00000010 // Write Complete/Capable Raw
159  // Interrupt Status
160 #define HIB_RIS_EXTW 0x00000008 // External Wake-Up Raw Interrupt
161  // Status
162 #define HIB_RIS_LOWBAT 0x00000004 // Low Battery Voltage Raw
163  // Interrupt Status
164 #define HIB_RIS_RTCALT0 0x00000001 // RTC Alert 0 Raw Interrupt Status
165 
166 //*****************************************************************************
167 //
168 // The following are defines for the bit fields in the HIB_MIS register.
169 //
170 //*****************************************************************************
171 #define HIB_MIS_VDDFAIL 0x00000080 // VDD Fail Interrupt Mask
172 #define HIB_MIS_RSTWK 0x00000040 // Reset Pad I/O Wake-Up Interrupt
173  // Mask
174 #define HIB_MIS_PADIOWK 0x00000020 // Pad I/O Wake-Up Interrupt Mask
175 #define HIB_MIS_WC 0x00000010 // Write Complete/Capable Masked
176  // Interrupt Status
177 #define HIB_MIS_EXTW 0x00000008 // External Wake-Up Masked
178  // Interrupt Status
179 #define HIB_MIS_LOWBAT 0x00000004 // Low Battery Voltage Masked
180  // Interrupt Status
181 #define HIB_MIS_RTCALT0 0x00000001 // RTC Alert 0 Masked Interrupt
182  // Status
183 
184 //*****************************************************************************
185 //
186 // The following are defines for the bit fields in the HIB_IC register.
187 //
188 //*****************************************************************************
189 #define HIB_IC_VDDFAIL 0x00000080 // VDD Fail Interrupt Clear
190 #define HIB_IC_RSTWK 0x00000040 // Reset Pad I/O Wake-Up Interrupt
191  // Clear
192 #define HIB_IC_PADIOWK 0x00000020 // Pad I/O Wake-Up Interrupt Clear
193 #define HIB_IC_WC 0x00000010 // Write Complete/Capable Interrupt
194  // Clear
195 #define HIB_IC_EXTW 0x00000008 // External Wake-Up Interrupt Clear
196 #define HIB_IC_LOWBAT 0x00000004 // Low Battery Voltage Interrupt
197  // Clear
198 #define HIB_IC_RTCALT0 0x00000001 // RTC Alert0 Masked Interrupt
199  // Clear
200 
201 //*****************************************************************************
202 //
203 // The following are defines for the bit fields in the HIB_RTCT register.
204 //
205 //*****************************************************************************
206 #define HIB_RTCT_TRIM_M 0x0000FFFF // RTC Trim Value
207 #define HIB_RTCT_TRIM_S 0
208 
209 //*****************************************************************************
210 //
211 // The following are defines for the bit fields in the HIB_RTCSS register.
212 //
213 //*****************************************************************************
214 #define HIB_RTCSS_RTCSSM_M 0x7FFF0000 // RTC Sub Seconds Match
215 #define HIB_RTCSS_RTCSSC_M 0x00007FFF // RTC Sub Seconds Count
216 #define HIB_RTCSS_RTCSSM_S 16
217 #define HIB_RTCSS_RTCSSC_S 0
218 
219 //*****************************************************************************
220 //
221 // The following are defines for the bit fields in the HIB_IO register.
222 //
223 //*****************************************************************************
224 #define HIB_IO_IOWRC 0x80000000 // I/O Write Complete
225 #define HIB_IO_WURSTEN 0x00000010 // Reset Wake Source Enable
226 #define HIB_IO_WUUNLK 0x00000001 // I/O Wake Pad Configuration
227  // Enable
228 
229 //*****************************************************************************
230 //
231 // The following are defines for the bit fields in the HIB_DATA register.
232 //
233 //*****************************************************************************
234 #define HIB_DATA_RTD_M 0xFFFFFFFF // Hibernation Module NV Data
235 #define HIB_DATA_RTD_S 0
236 
237 //*****************************************************************************
238 //
239 // The following are defines for the bit fields in the HIB_CALCTL register.
240 //
241 //*****************************************************************************
242 #define HIB_CALCTL_CAL24 0x00000004 // Calendar Mode
243 #define HIB_CALCTL_CALEN 0x00000001 // RTC Calendar/Counter Mode Select
244 
245 //*****************************************************************************
246 //
247 // The following are defines for the bit fields in the HIB_CAL0 register.
248 //
249 //*****************************************************************************
250 #define HIB_CAL0_VALID 0x80000000 // Valid Calendar Load
251 #define HIB_CAL0_AMPM 0x00400000 // AM/PM Designation
252 #define HIB_CAL0_HR_M 0x001F0000 // Hours
253 #define HIB_CAL0_MIN_M 0x00003F00 // Minutes
254 #define HIB_CAL0_SEC_M 0x0000003F // Seconds
255 #define HIB_CAL0_HR_S 16
256 #define HIB_CAL0_MIN_S 8
257 #define HIB_CAL0_SEC_S 0
258 
259 //*****************************************************************************
260 //
261 // The following are defines for the bit fields in the HIB_CAL1 register.
262 //
263 //*****************************************************************************
264 #define HIB_CAL1_VALID 0x80000000 // Valid Calendar Load
265 #define HIB_CAL1_DOW_M 0x07000000 // Day of Week
266 #define HIB_CAL1_YEAR_M 0x007F0000 // Year Value
267 #define HIB_CAL1_MON_M 0x00000F00 // Month
268 #define HIB_CAL1_DOM_M 0x0000001F // Day of Month
269 #define HIB_CAL1_DOW_S 24
270 #define HIB_CAL1_YEAR_S 16
271 #define HIB_CAL1_MON_S 8
272 #define HIB_CAL1_DOM_S 0
273 
274 //*****************************************************************************
275 //
276 // The following are defines for the bit fields in the HIB_CALLD0 register.
277 //
278 //*****************************************************************************
279 #define HIB_CALLD0_AMPM 0x00400000 // AM/PM Designation
280 #define HIB_CALLD0_HR_M 0x001F0000 // Hours
281 #define HIB_CALLD0_MIN_M 0x00003F00 // Minutes
282 #define HIB_CALLD0_SEC_M 0x0000003F // Seconds
283 #define HIB_CALLD0_HR_S 16
284 #define HIB_CALLD0_MIN_S 8
285 #define HIB_CALLD0_SEC_S 0
286 
287 //*****************************************************************************
288 //
289 // The following are defines for the bit fields in the HIB_CALLD1 register.
290 //
291 //*****************************************************************************
292 #define HIB_CALLD1_DOW_M 0x07000000 // Day of Week
293 #define HIB_CALLD1_YEAR_M 0x007F0000 // Year Value
294 #define HIB_CALLD1_MON_M 0x00000F00 // Month
295 #define HIB_CALLD1_DOM_M 0x0000001F // Day of Month
296 #define HIB_CALLD1_DOW_S 24
297 #define HIB_CALLD1_YEAR_S 16
298 #define HIB_CALLD1_MON_S 8
299 #define HIB_CALLD1_DOM_S 0
300 
301 //*****************************************************************************
302 //
303 // The following are defines for the bit fields in the HIB_CALM0 register.
304 //
305 //*****************************************************************************
306 #define HIB_CALM0_AMPM 0x00400000 // AM/PM Designation
307 #define HIB_CALM0_HR_M 0x001F0000 // Hours
308 #define HIB_CALM0_MIN_M 0x00003F00 // Minutes
309 #define HIB_CALM0_SEC_M 0x0000003F // Seconds
310 #define HIB_CALM0_HR_S 16
311 #define HIB_CALM0_MIN_S 8
312 #define HIB_CALM0_SEC_S 0
313 
314 //*****************************************************************************
315 //
316 // The following are defines for the bit fields in the HIB_CALM1 register.
317 //
318 //*****************************************************************************
319 #define HIB_CALM1_DOM_M 0x0000001F // Day of Month
320 #define HIB_CALM1_DOM_S 0
321 
322 //*****************************************************************************
323 //
324 // The following are defines for the bit fields in the HIB_LOCK register.
325 //
326 //*****************************************************************************
327 #define HIB_LOCK_HIBLOCK_M 0xFFFFFFFF // HIbernate Lock
328 #define HIB_LOCK_HIBLOCK_KEY 0xA3359554 // Hibernate Lock Key
329 #define HIB_LOCK_HIBLOCK_S 0
330 
331 //*****************************************************************************
332 //
333 // The following are defines for the bit fields in the HIB_TPCTL register.
334 //
335 //*****************************************************************************
336 #define HIB_TPCTL_WAKE 0x00000800 // Wake from Hibernate on a Tamper
337  // Event
338 #define HIB_TPCTL_MEMCLR_M 0x00000300 // HIB Memory Clear on Tamper Event
339 #define HIB_TPCTL_MEMCLR_NONE 0x00000000 // Do not Clear HIB memory on
340  // tamper event
341 #define HIB_TPCTL_MEMCLR_LOW32 0x00000100 // Clear Lower 32 Bytes of HIB
342  // memory on tamper event
343 #define HIB_TPCTL_MEMCLR_HIGH32 0x00000200 // Clear upper 32 Bytes of HIB
344  // memory on tamper event
345 #define HIB_TPCTL_MEMCLR_ALL 0x00000300 // Clear all HIB memory on tamper
346  // event
347 #define HIB_TPCTL_TPCLR 0x00000010 // Tamper Event Clear
348 #define HIB_TPCTL_TPEN 0x00000001 // Tamper Module Enable
349 
350 //*****************************************************************************
351 //
352 // The following are defines for the bit fields in the HIB_TPSTAT register.
353 //
354 //*****************************************************************************
355 #define HIB_TPSTAT_STATE_M 0x0000000C // Tamper Module Status
356 #define HIB_TPSTAT_STATE_DISABLED \
357  0x00000000 // Tamper disabled
358 #define HIB_TPSTAT_STATE_CONFIGED \
359  0x00000004 // Tamper configured
360 #define HIB_TPSTAT_STATE_ERROR 0x00000008 // Tamper pin event occurred
361 #define HIB_TPSTAT_XOSCST 0x00000002 // External Oscillator Status
362 #define HIB_TPSTAT_XOSCFAIL 0x00000001 // External Oscillator Failure
363 
364 //*****************************************************************************
365 //
366 // The following are defines for the bit fields in the HIB_TPIO register.
367 //
368 //*****************************************************************************
369 #define HIB_TPIO_GFLTR3 0x08000000 // TMPR3 Glitch Filtering
370 #define HIB_TPIO_PUEN3 0x04000000 // TMPR3 Internal Weak Pull-up
371  // Enable
372 #define HIB_TPIO_LEV3 0x02000000 // TMPR3 Trigger Level
373 #define HIB_TPIO_EN3 0x01000000 // TMPR3 Enable
374 #define HIB_TPIO_GFLTR2 0x00080000 // TMPR2 Glitch Filtering
375 #define HIB_TPIO_PUEN2 0x00040000 // TMPR2 Internal Weak Pull-up
376  // Enable
377 #define HIB_TPIO_LEV2 0x00020000 // TMPR2 Trigger Level
378 #define HIB_TPIO_EN2 0x00010000 // TMPR2 Enable
379 #define HIB_TPIO_GFLTR1 0x00000800 // TMPR1 Glitch Filtering
380 #define HIB_TPIO_PUEN1 0x00000400 // TMPR1 Internal Weak Pull-up
381  // Enable
382 #define HIB_TPIO_LEV1 0x00000200 // TMPR1 Trigger Level
383 #define HIB_TPIO_EN1 0x00000100 // TMPR1Enable
384 #define HIB_TPIO_GFLTR0 0x00000008 // TMPR0 Glitch Filtering
385 #define HIB_TPIO_PUEN0 0x00000004 // TMPR0 Internal Weak Pull-up
386  // Enable
387 #define HIB_TPIO_LEV0 0x00000002 // TMPR0 Trigger Level
388 #define HIB_TPIO_EN0 0x00000001 // TMPR0 Enable
389 
390 //*****************************************************************************
391 //
392 // The following are defines for the bit fields in the HIB_TPLOG0 register.
393 //
394 //*****************************************************************************
395 #define HIB_TPLOG0_TIME_M 0xFFFFFFFF // Tamper Log Calendar Information
396 #define HIB_TPLOG0_TIME_S 0
397 
398 //*****************************************************************************
399 //
400 // The following are defines for the bit fields in the HIB_TPLOG1 register.
401 //
402 //*****************************************************************************
403 #define HIB_TPLOG1_XOSC 0x00010000 // Status of external 32
404 #define HIB_TPLOG1_TRIG3 0x00000008 // Status of TMPR[3] Trigger
405 #define HIB_TPLOG1_TRIG2 0x00000004 // Status of TMPR[2] Trigger
406 #define HIB_TPLOG1_TRIG1 0x00000002 // Status of TMPR[1] Trigger
407 #define HIB_TPLOG1_TRIG0 0x00000001 // Status of TMPR[0] Trigger
408 
409 //*****************************************************************************
410 //
411 // The following are defines for the bit fields in the HIB_TPLOG2 register.
412 //
413 //*****************************************************************************
414 #define HIB_TPLOG2_TIME_M 0xFFFFFFFF // Tamper Log Calendar Information
415 #define HIB_TPLOG2_TIME_S 0
416 
417 //*****************************************************************************
418 //
419 // The following are defines for the bit fields in the HIB_TPLOG3 register.
420 //
421 //*****************************************************************************
422 #define HIB_TPLOG3_XOSC 0x00010000 // Status of external 32
423 #define HIB_TPLOG3_TRIG3 0x00000008 // Status of TMPR[3] Trigger
424 #define HIB_TPLOG3_TRIG2 0x00000004 // Status of TMPR[2] Trigger
425 #define HIB_TPLOG3_TRIG1 0x00000002 // Status of TMPR[1] Trigger
426 #define HIB_TPLOG3_TRIG0 0x00000001 // Status of TMPR[0] Trigger
427 
428 //*****************************************************************************
429 //
430 // The following are defines for the bit fields in the HIB_TPLOG4 register.
431 //
432 //*****************************************************************************
433 #define HIB_TPLOG4_TIME_M 0xFFFFFFFF // Tamper Log Calendar Information
434 #define HIB_TPLOG4_TIME_S 0
435 
436 //*****************************************************************************
437 //
438 // The following are defines for the bit fields in the HIB_TPLOG5 register.
439 //
440 //*****************************************************************************
441 #define HIB_TPLOG5_XOSC 0x00010000 // Status of external 32
442 #define HIB_TPLOG5_TRIG3 0x00000008 // Status of TMPR[3] Trigger
443 #define HIB_TPLOG5_TRIG2 0x00000004 // Status of TMPR[2] Trigger
444 #define HIB_TPLOG5_TRIG1 0x00000002 // Status of TMPR[1] Trigger
445 #define HIB_TPLOG5_TRIG0 0x00000001 // Status of TMPR[0] Trigger
446 
447 //*****************************************************************************
448 //
449 // The following are defines for the bit fields in the HIB_TPLOG6 register.
450 //
451 //*****************************************************************************
452 #define HIB_TPLOG6_TIME_M 0xFFFFFFFF // Tamper Log Calendar Information
453 #define HIB_TPLOG6_TIME_S 0
454 
455 //*****************************************************************************
456 //
457 // The following are defines for the bit fields in the HIB_TPLOG7 register.
458 //
459 //*****************************************************************************
460 #define HIB_TPLOG7_XOSC 0x00010000 // Status of external 32
461 #define HIB_TPLOG7_TRIG3 0x00000008 // Status of TMPR[3] Trigger
462 #define HIB_TPLOG7_TRIG2 0x00000004 // Status of TMPR[2] Trigger
463 #define HIB_TPLOG7_TRIG1 0x00000002 // Status of TMPR[1] Trigger
464 #define HIB_TPLOG7_TRIG0 0x00000001 // Status of TMPR[0] Trigger
465 
466 //*****************************************************************************
467 //
468 // The following are defines for the bit fields in the HIB_PP register.
469 //
470 //*****************************************************************************
471 #define HIB_PP_TAMPER 0x00000002 // Tamper Pin Presence
472 #define HIB_PP_WAKENC 0x00000001 // Wake Pin Presence
473 
474 //*****************************************************************************
475 //
476 // The following are defines for the bit fields in the HIB_CC register.
477 //
478 //*****************************************************************************
479 #define HIB_CC_SYSCLKEN 0x00000001 // RTCOSC to System Clock Enable
480 
481 #endif // __HW_HIBERNATE_H__
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