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Go to the documentation of this file. 47 #define EPI_O_CFG 0x00000000 // EPI Configuration 48 #define EPI_O_BAUD 0x00000004 // EPI Main Baud Rate 49 #define EPI_O_BAUD2 0x00000008 // EPI Main Baud Rate 50 #define EPI_O_HB16CFG 0x00000010 // EPI Host-Bus 16 Configuration 51 #define EPI_O_GPCFG 0x00000010 // EPI General-Purpose 53 #define EPI_O_SDRAMCFG 0x00000010 // EPI SDRAM Configuration 54 #define EPI_O_HB8CFG 0x00000010 // EPI Host-Bus 8 Configuration 55 #define EPI_O_HB8CFG2 0x00000014 // EPI Host-Bus 8 Configuration 2 56 #define EPI_O_HB16CFG2 0x00000014 // EPI Host-Bus 16 Configuration 2 57 #define EPI_O_ADDRMAP 0x0000001C // EPI Address Map 58 #define EPI_O_RSIZE0 0x00000020 // EPI Read Size 0 59 #define EPI_O_RADDR0 0x00000024 // EPI Read Address 0 60 #define EPI_O_RPSTD0 0x00000028 // EPI Non-Blocking Read Data 0 61 #define EPI_O_RSIZE1 0x00000030 // EPI Read Size 1 62 #define EPI_O_RADDR1 0x00000034 // EPI Read Address 1 63 #define EPI_O_RPSTD1 0x00000038 // EPI Non-Blocking Read Data 1 64 #define EPI_O_STAT 0x00000060 // EPI Status 65 #define EPI_O_RFIFOCNT 0x0000006C // EPI Read FIFO Count 66 #define EPI_O_READFIFO0 0x00000070 // EPI Read FIFO 67 #define EPI_O_READFIFO1 0x00000074 // EPI Read FIFO Alias 1 68 #define EPI_O_READFIFO2 0x00000078 // EPI Read FIFO Alias 2 69 #define EPI_O_READFIFO3 0x0000007C // EPI Read FIFO Alias 3 70 #define EPI_O_READFIFO4 0x00000080 // EPI Read FIFO Alias 4 71 #define EPI_O_READFIFO5 0x00000084 // EPI Read FIFO Alias 5 72 #define EPI_O_READFIFO6 0x00000088 // EPI Read FIFO Alias 6 73 #define EPI_O_READFIFO7 0x0000008C // EPI Read FIFO Alias 7 74 #define EPI_O_FIFOLVL 0x00000200 // EPI FIFO Level Selects 75 #define EPI_O_WFIFOCNT 0x00000204 // EPI Write FIFO Count 76 #define EPI_O_DMATXCNT 0x00000208 // EPI DMA Transmit Count 77 #define EPI_O_IM 0x00000210 // EPI Interrupt Mask 78 #define EPI_O_RIS 0x00000214 // EPI Raw Interrupt Status 79 #define EPI_O_MIS 0x00000218 // EPI Masked Interrupt Status 80 #define EPI_O_EISC 0x0000021C // EPI Error and Interrupt Status 82 #define EPI_O_HB8CFG3 0x00000308 // EPI Host-Bus 8 Configuration 3 83 #define EPI_O_HB16CFG3 0x00000308 // EPI Host-Bus 16 Configuration 3 84 #define EPI_O_HB16CFG4 0x0000030C // EPI Host-Bus 16 Configuration 4 85 #define EPI_O_HB8CFG4 0x0000030C // EPI Host-Bus 8 Configuration 4 86 #define EPI_O_HB8TIME 0x00000310 // EPI Host-Bus 8 Timing Extension 87 #define EPI_O_HB16TIME 0x00000310 // EPI Host-Bus 16 Timing Extension 88 #define EPI_O_HB8TIME2 0x00000314 // EPI Host-Bus 8 Timing Extension 89 #define EPI_O_HB16TIME2 0x00000314 // EPI Host-Bus 16 Timing Extension 90 #define EPI_O_HB16TIME3 0x00000318 // EPI Host-Bus 16 Timing Extension 91 #define EPI_O_HB8TIME3 0x00000318 // EPI Host-Bus 8 Timing Extension 92 #define EPI_O_HB8TIME4 0x0000031C // EPI Host-Bus 8 Timing Extension 93 #define EPI_O_HB16TIME4 0x0000031C // EPI Host-Bus 16 Timing Extension 94 #define EPI_O_HBPSRAM 0x00000360 // EPI Host-Bus PSRAM 101 #define EPI_CFG_INTDIV 0x00000100 // Integer Clock Divider Enable 102 #define EPI_CFG_BLKEN 0x00000010 // Block Enable 103 #define EPI_CFG_MODE_M 0x0000000F // Mode Select 104 #define EPI_CFG_MODE_NONE 0x00000000 // General Purpose 105 #define EPI_CFG_MODE_SDRAM 0x00000001 // SDRAM 106 #define EPI_CFG_MODE_HB8 0x00000002 // 8-Bit Host-Bus (HB8) 107 #define EPI_CFG_MODE_HB16 0x00000003 // 16-Bit Host-Bus (HB16) 114 #define EPI_BAUD_COUNT1_M 0xFFFF0000 // Baud Rate Counter 1 115 #define EPI_BAUD_COUNT0_M 0x0000FFFF // Baud Rate Counter 0 116 #define EPI_BAUD_COUNT1_S 16 117 #define EPI_BAUD_COUNT0_S 0 124 #define EPI_BAUD2_COUNT1_M 0xFFFF0000 // CS3n Baud Rate Counter 1 125 #define EPI_BAUD2_COUNT0_M 0x0000FFFF // CS2n Baud Rate Counter 0 126 #define EPI_BAUD2_COUNT1_S 16 127 #define EPI_BAUD2_COUNT0_S 0 134 #define EPI_HB16CFG_CLKGATE 0x80000000 // Clock Gated 135 #define EPI_HB16CFG_CLKGATEI 0x40000000 // Clock Gated Idle 136 #define EPI_HB16CFG_CLKINV 0x20000000 // Invert Output Clock Enable 137 #define EPI_HB16CFG_RDYEN 0x10000000 // Input Ready Enable 138 #define EPI_HB16CFG_IRDYINV 0x08000000 // Input Ready Invert 139 #define EPI_HB16CFG_XFFEN 0x00800000 // External FIFO FULL Enable 140 #define EPI_HB16CFG_XFEEN 0x00400000 // External FIFO EMPTY Enable 141 #define EPI_HB16CFG_WRHIGH 0x00200000 // WRITE Strobe Polarity 142 #define EPI_HB16CFG_RDHIGH 0x00100000 // READ Strobe Polarity 143 #define EPI_HB16CFG_ALEHIGH 0x00080000 // ALE Strobe Polarity 144 #define EPI_HB16CFG_WRCRE 0x00040000 // PSRAM Configuration Register 146 #define EPI_HB16CFG_RDCRE 0x00020000 // PSRAM Configuration Register 148 #define EPI_HB16CFG_BURST 0x00010000 // Burst Mode 149 #define EPI_HB16CFG_MAXWAIT_M 0x0000FF00 // Maximum Wait 150 #define EPI_HB16CFG_WRWS_M 0x000000C0 // Write Wait States 151 #define EPI_HB16CFG_WRWS_2 0x00000000 // Active WRn is 2 EPI clocks 152 #define EPI_HB16CFG_WRWS_4 0x00000040 // Active WRn is 4 EPI clocks 153 #define EPI_HB16CFG_WRWS_6 0x00000080 // Active WRn is 6 EPI clocks 154 #define EPI_HB16CFG_WRWS_8 0x000000C0 // Active WRn is 8 EPI clocks 155 #define EPI_HB16CFG_RDWS_M 0x00000030 // Read Wait States 156 #define EPI_HB16CFG_RDWS_2 0x00000000 // Active RDn is 2 EPI clocks 157 #define EPI_HB16CFG_RDWS_4 0x00000010 // Active RDn is 4 EPI clocks 158 #define EPI_HB16CFG_RDWS_6 0x00000020 // Active RDn is 6 EPI clocks 159 #define EPI_HB16CFG_RDWS_8 0x00000030 // Active RDn is 8 EPI clocks 160 #define EPI_HB16CFG_BSEL 0x00000004 // Byte Select Configuration 161 #define EPI_HB16CFG_MODE_M 0x00000003 // Host Bus Sub-Mode 162 #define EPI_HB16CFG_MODE_ADMUX 0x00000000 // ADMUX - AD[15:0] 163 #define EPI_HB16CFG_MODE_ADNMUX 0x00000001 // ADNONMUX - D[15:0] 164 #define EPI_HB16CFG_MODE_SRAM 0x00000002 // Continuous Read - D[15:0] 165 #define EPI_HB16CFG_MODE_XFIFO 0x00000003 // XFIFO - D[15:0] 166 #define EPI_HB16CFG_MAXWAIT_S 8 173 #define EPI_GPCFG_CLKPIN 0x80000000 // Clock Pin 174 #define EPI_GPCFG_CLKGATE 0x40000000 // Clock Gated 175 #define EPI_GPCFG_FRM50 0x04000000 // 50/50 Frame 176 #define EPI_GPCFG_FRMCNT_M 0x03C00000 // Frame Count 177 #define EPI_GPCFG_WR2CYC 0x00080000 // 2-Cycle Writes 178 #define EPI_GPCFG_ASIZE_M 0x00000030 // Address Bus Size 179 #define EPI_GPCFG_ASIZE_NONE 0x00000000 // No address 180 #define EPI_GPCFG_ASIZE_4BIT 0x00000010 // Up to 4 bits wide 181 #define EPI_GPCFG_ASIZE_12BIT 0x00000020 // Up to 12 bits wide. This size 183 #define EPI_GPCFG_ASIZE_20BIT 0x00000030 // Up to 20 bits wide. This size 186 #define EPI_GPCFG_DSIZE_M 0x00000003 // Size of Data Bus 187 #define EPI_GPCFG_DSIZE_4BIT 0x00000000 // 8 Bits Wide (EPI0S0 to EPI0S7) 188 #define EPI_GPCFG_DSIZE_16BIT 0x00000001 // 16 Bits Wide (EPI0S0 to EPI0S15) 189 #define EPI_GPCFG_DSIZE_24BIT 0x00000002 // 24 Bits Wide (EPI0S0 to EPI0S23) 190 #define EPI_GPCFG_DSIZE_32BIT 0x00000003 // 32 Bits Wide (EPI0S0 to EPI0S31) 191 #define EPI_GPCFG_FRMCNT_S 22 198 #define EPI_SDRAMCFG_FREQ_M 0xC0000000 // EPI Frequency Range 199 #define EPI_SDRAMCFG_FREQ_NONE 0x00000000 // 0 - 15 MHz 200 #define EPI_SDRAMCFG_FREQ_15MHZ 0x40000000 // 15 - 30 MHz 201 #define EPI_SDRAMCFG_FREQ_30MHZ 0x80000000 // 30 - 50 MHz 202 #define EPI_SDRAMCFG_RFSH_M 0x07FF0000 // Refresh Counter 203 #define EPI_SDRAMCFG_SLEEP 0x00000200 // Sleep Mode 204 #define EPI_SDRAMCFG_SIZE_M 0x00000003 // Size of SDRAM 205 #define EPI_SDRAMCFG_SIZE_8MB 0x00000000 // 64 megabits (8MB) 206 #define EPI_SDRAMCFG_SIZE_16MB 0x00000001 // 128 megabits (16MB) 207 #define EPI_SDRAMCFG_SIZE_32MB 0x00000002 // 256 megabits (32MB) 208 #define EPI_SDRAMCFG_SIZE_64MB 0x00000003 // 512 megabits (64MB) 209 #define EPI_SDRAMCFG_RFSH_S 16 216 #define EPI_HB8CFG_CLKGATE 0x80000000 // Clock Gated 217 #define EPI_HB8CFG_CLKGATEI 0x40000000 // Clock Gated when Idle 218 #define EPI_HB8CFG_CLKINV 0x20000000 // Invert Output Clock Enable 219 #define EPI_HB8CFG_RDYEN 0x10000000 // Input Ready Enable 220 #define EPI_HB8CFG_IRDYINV 0x08000000 // Input Ready Invert 221 #define EPI_HB8CFG_XFFEN 0x00800000 // External FIFO FULL Enable 222 #define EPI_HB8CFG_XFEEN 0x00400000 // External FIFO EMPTY Enable 223 #define EPI_HB8CFG_WRHIGH 0x00200000 // WRITE Strobe Polarity 224 #define EPI_HB8CFG_RDHIGH 0x00100000 // READ Strobe Polarity 225 #define EPI_HB8CFG_ALEHIGH 0x00080000 // ALE Strobe Polarity 226 #define EPI_HB8CFG_MAXWAIT_M 0x0000FF00 // Maximum Wait 227 #define EPI_HB8CFG_WRWS_M 0x000000C0 // Write Wait States 228 #define EPI_HB8CFG_WRWS_2 0x00000000 // Active WRn is 2 EPI clocks 229 #define EPI_HB8CFG_WRWS_4 0x00000040 // Active WRn is 4 EPI clocks 230 #define EPI_HB8CFG_WRWS_6 0x00000080 // Active WRn is 6 EPI clocks 231 #define EPI_HB8CFG_WRWS_8 0x000000C0 // Active WRn is 8 EPI clocks 232 #define EPI_HB8CFG_RDWS_M 0x00000030 // Read Wait States 233 #define EPI_HB8CFG_RDWS_2 0x00000000 // Active RDn is 2 EPI clocks 234 #define EPI_HB8CFG_RDWS_4 0x00000010 // Active RDn is 4 EPI clocks 235 #define EPI_HB8CFG_RDWS_6 0x00000020 // Active RDn is 6 EPI clocks 236 #define EPI_HB8CFG_RDWS_8 0x00000030 // Active RDn is 8 EPI clocks 237 #define EPI_HB8CFG_MODE_M 0x00000003 // Host Bus Sub-Mode 238 #define EPI_HB8CFG_MODE_MUX 0x00000000 // ADMUX - AD[7:0] 239 #define EPI_HB8CFG_MODE_NMUX 0x00000001 // ADNONMUX - D[7:0] 240 #define EPI_HB8CFG_MODE_SRAM 0x00000002 // Continuous Read - D[7:0] 241 #define EPI_HB8CFG_MODE_FIFO 0x00000003 // XFIFO - D[7:0] 242 #define EPI_HB8CFG_MAXWAIT_S 8 249 #define EPI_HB8CFG2_CSCFGEXT 0x08000000 // Chip Select Extended 251 #define EPI_HB8CFG2_CSBAUD 0x04000000 // Chip Select Baud Rate and 254 #define EPI_HB8CFG2_CSCFG_M 0x03000000 // Chip Select Configuration 255 #define EPI_HB8CFG2_CSCFG_ALE 0x00000000 // ALE Configuration 256 #define EPI_HB8CFG2_CSCFG_CS 0x01000000 // CSn Configuration 257 #define EPI_HB8CFG2_CSCFG_DCS 0x02000000 // Dual CSn Configuration 258 #define EPI_HB8CFG2_CSCFG_ADCS 0x03000000 // ALE with Dual CSn Configuration 259 #define EPI_HB8CFG2_WRHIGH 0x00200000 // CS1n WRITE Strobe Polarity 260 #define EPI_HB8CFG2_RDHIGH 0x00100000 // CS1n READ Strobe Polarity 261 #define EPI_HB8CFG2_ALEHIGH 0x00080000 // CS1n ALE Strobe Polarity 262 #define EPI_HB8CFG2_WRWS_M 0x000000C0 // CS1n Write Wait States 263 #define EPI_HB8CFG2_WRWS_2 0x00000000 // Active WRn is 2 EPI clocks 264 #define EPI_HB8CFG2_WRWS_4 0x00000040 // Active WRn is 4 EPI clocks 265 #define EPI_HB8CFG2_WRWS_6 0x00000080 // Active WRn is 6 EPI clocks 266 #define EPI_HB8CFG2_WRWS_8 0x000000C0 // Active WRn is 8 EPI clocks 267 #define EPI_HB8CFG2_RDWS_M 0x00000030 // CS1n Read Wait States 268 #define EPI_HB8CFG2_RDWS_2 0x00000000 // Active RDn is 2 EPI clocks 269 #define EPI_HB8CFG2_RDWS_4 0x00000010 // Active RDn is 4 EPI clocks 270 #define EPI_HB8CFG2_RDWS_6 0x00000020 // Active RDn is 6 EPI clocks 271 #define EPI_HB8CFG2_RDWS_8 0x00000030 // Active RDn is 8 EPI clocks 272 #define EPI_HB8CFG2_MODE_M 0x00000003 // CS1n Host Bus Sub-Mode 273 #define EPI_HB8CFG2_MODE_ADMUX 0x00000000 // ADMUX - AD[7:0] 274 #define EPI_HB8CFG2_MODE_AD 0x00000001 // ADNONMUX - D[7:0] 281 #define EPI_HB16CFG2_CSCFGEXT 0x08000000 // Chip Select Extended 283 #define EPI_HB16CFG2_CSBAUD 0x04000000 // Chip Select Baud Rate and 286 #define EPI_HB16CFG2_CSCFG_M 0x03000000 // Chip Select Configuration 287 #define EPI_HB16CFG2_CSCFG_ALE 0x00000000 // ALE Configuration 288 #define EPI_HB16CFG2_CSCFG_CS 0x01000000 // CSn Configuration 289 #define EPI_HB16CFG2_CSCFG_DCS 0x02000000 // Dual CSn Configuration 290 #define EPI_HB16CFG2_CSCFG_ADCS 0x03000000 // ALE with Dual CSn Configuration 291 #define EPI_HB16CFG2_WRHIGH 0x00200000 // CS1n WRITE Strobe Polarity 292 #define EPI_HB16CFG2_RDHIGH 0x00100000 // CS1n READ Strobe Polarity 293 #define EPI_HB16CFG2_ALEHIGH 0x00080000 // CS1n ALE Strobe Polarity 294 #define EPI_HB16CFG2_WRCRE 0x00040000 // CS1n PSRAM Configuration 296 #define EPI_HB16CFG2_RDCRE 0x00020000 // CS1n PSRAM Configuration 298 #define EPI_HB16CFG2_BURST 0x00010000 // CS1n Burst Mode 299 #define EPI_HB16CFG2_WRWS_M 0x000000C0 // CS1n Write Wait States 300 #define EPI_HB16CFG2_WRWS_2 0x00000000 // Active WRn is 2 EPI clocks 301 #define EPI_HB16CFG2_WRWS_4 0x00000040 // Active WRn is 4 EPI clocks 302 #define EPI_HB16CFG2_WRWS_6 0x00000080 // Active WRn is 6 EPI clocks 303 #define EPI_HB16CFG2_WRWS_8 0x000000C0 // Active WRn is 8 EPI clocks 304 #define EPI_HB16CFG2_RDWS_M 0x00000030 // CS1n Read Wait States 305 #define EPI_HB16CFG2_RDWS_2 0x00000000 // Active RDn is 2 EPI clocks 306 #define EPI_HB16CFG2_RDWS_4 0x00000010 // Active RDn is 4 EPI clocks 307 #define EPI_HB16CFG2_RDWS_6 0x00000020 // Active RDn is 6 EPI clocks 308 #define EPI_HB16CFG2_RDWS_8 0x00000030 // Active RDn is 8 EPI clocks 309 #define EPI_HB16CFG2_MODE_M 0x00000003 // CS1n Host Bus Sub-Mode 310 #define EPI_HB16CFG2_MODE_ADMUX 0x00000000 // ADMUX - AD[15:0] 311 #define EPI_HB16CFG2_MODE_AD 0x00000001 // ADNONMUX - D[15:0] 318 #define EPI_ADDRMAP_ECSZ_M 0x00000C00 // External Code Size 319 #define EPI_ADDRMAP_ECSZ_256B 0x00000000 // 256 bytes; lower address range: 321 #define EPI_ADDRMAP_ECSZ_64KB 0x00000400 // 64 KB; lower address range: 323 #define EPI_ADDRMAP_ECSZ_16MB 0x00000800 // 16 MB; lower address range: 325 #define EPI_ADDRMAP_ECSZ_256MB 0x00000C00 // 256MB; lower address range: 327 #define EPI_ADDRMAP_ECADR_M 0x00000300 // External Code Address 328 #define EPI_ADDRMAP_ECADR_NONE 0x00000000 // Not mapped 329 #define EPI_ADDRMAP_ECADR_1000 0x00000100 // At 0x1000.0000 330 #define EPI_ADDRMAP_EPSZ_M 0x000000C0 // External Peripheral Size 331 #define EPI_ADDRMAP_EPSZ_256B 0x00000000 // 256 bytes; lower address range: 333 #define EPI_ADDRMAP_EPSZ_64KB 0x00000040 // 64 KB; lower address range: 335 #define EPI_ADDRMAP_EPSZ_16MB 0x00000080 // 16 MB; lower address range: 337 #define EPI_ADDRMAP_EPSZ_256MB 0x000000C0 // 256 MB; lower address range: 339 #define EPI_ADDRMAP_EPADR_M 0x00000030 // External Peripheral Address 340 #define EPI_ADDRMAP_EPADR_NONE 0x00000000 // Not mapped 341 #define EPI_ADDRMAP_EPADR_A000 0x00000010 // At 0xA000.0000 342 #define EPI_ADDRMAP_EPADR_C000 0x00000020 // At 0xC000.0000 343 #define EPI_ADDRMAP_EPADR_HBQS 0x00000030 // Only to be used with Host Bus 348 #define EPI_ADDRMAP_ERSZ_M 0x0000000C // External RAM Size 349 #define EPI_ADDRMAP_ERSZ_256B 0x00000000 // 256 bytes; lower address range: 351 #define EPI_ADDRMAP_ERSZ_64KB 0x00000004 // 64 KB; lower address range: 353 #define EPI_ADDRMAP_ERSZ_16MB 0x00000008 // 16 MB; lower address range: 355 #define EPI_ADDRMAP_ERSZ_256MB 0x0000000C // 256 MB; lower address range: 357 #define EPI_ADDRMAP_ERADR_M 0x00000003 // External RAM Address 358 #define EPI_ADDRMAP_ERADR_NONE 0x00000000 // Not mapped 359 #define EPI_ADDRMAP_ERADR_6000 0x00000001 // At 0x6000.0000 360 #define EPI_ADDRMAP_ERADR_8000 0x00000002 // At 0x8000.0000 361 #define EPI_ADDRMAP_ERADR_HBQS 0x00000003 // Only to be used with Host Bus 372 #define EPI_RSIZE0_SIZE_M 0x00000003 // Current Size 373 #define EPI_RSIZE0_SIZE_8BIT 0x00000001 // Byte (8 bits) 374 #define EPI_RSIZE0_SIZE_16BIT 0x00000002 // Half-word (16 bits) 375 #define EPI_RSIZE0_SIZE_32BIT 0x00000003 // Word (32 bits) 382 #define EPI_RADDR0_ADDR_M 0xFFFFFFFF // Current Address 383 #define EPI_RADDR0_ADDR_S 0 390 #define EPI_RPSTD0_POSTCNT_M 0x00001FFF // Post Count 391 #define EPI_RPSTD0_POSTCNT_S 0 398 #define EPI_RSIZE1_SIZE_M 0x00000003 // Current Size 399 #define EPI_RSIZE1_SIZE_8BIT 0x00000001 // Byte (8 bits) 400 #define EPI_RSIZE1_SIZE_16BIT 0x00000002 // Half-word (16 bits) 401 #define EPI_RSIZE1_SIZE_32BIT 0x00000003 // Word (32 bits) 408 #define EPI_RADDR1_ADDR_M 0xFFFFFFFF // Current Address 409 #define EPI_RADDR1_ADDR_S 0 416 #define EPI_RPSTD1_POSTCNT_M 0x00001FFF // Post Count 417 #define EPI_RPSTD1_POSTCNT_S 0 424 #define EPI_STAT_XFFULL 0x00000100 // External FIFO Full 425 #define EPI_STAT_XFEMPTY 0x00000080 // External FIFO Empty 426 #define EPI_STAT_INITSEQ 0x00000040 // Initialization Sequence 427 #define EPI_STAT_WBUSY 0x00000020 // Write Busy 428 #define EPI_STAT_NBRBUSY 0x00000010 // Non-Blocking Read Busy 429 #define EPI_STAT_ACTIVE 0x00000001 // Register Active 436 #define EPI_RFIFOCNT_COUNT_M 0x0000000F // FIFO Count 437 #define EPI_RFIFOCNT_COUNT_S 0 445 #define EPI_READFIFO0_DATA_M 0xFFFFFFFF // Reads Data 446 #define EPI_READFIFO0_DATA_S 0 454 #define EPI_READFIFO1_DATA_M 0xFFFFFFFF // Reads Data 455 #define EPI_READFIFO1_DATA_S 0 463 #define EPI_READFIFO2_DATA_M 0xFFFFFFFF // Reads Data 464 #define EPI_READFIFO2_DATA_S 0 472 #define EPI_READFIFO3_DATA_M 0xFFFFFFFF // Reads Data 473 #define EPI_READFIFO3_DATA_S 0 481 #define EPI_READFIFO4_DATA_M 0xFFFFFFFF // Reads Data 482 #define EPI_READFIFO4_DATA_S 0 490 #define EPI_READFIFO5_DATA_M 0xFFFFFFFF // Reads Data 491 #define EPI_READFIFO5_DATA_S 0 499 #define EPI_READFIFO6_DATA_M 0xFFFFFFFF // Reads Data 500 #define EPI_READFIFO6_DATA_S 0 508 #define EPI_READFIFO7_DATA_M 0xFFFFFFFF // Reads Data 509 #define EPI_READFIFO7_DATA_S 0 516 #define EPI_FIFOLVL_WFERR 0x00020000 // Write Full Error 517 #define EPI_FIFOLVL_RSERR 0x00010000 // Read Stall Error 518 #define EPI_FIFOLVL_WRFIFO_M 0x00000070 // Write FIFO 519 #define EPI_FIFOLVL_WRFIFO_EMPT 0x00000000 // Interrupt is triggered while 521 #define EPI_FIFOLVL_WRFIFO_2 0x00000020 // Interrupt is triggered until 528 #define EPI_FIFOLVL_WRFIFO_1 0x00000030 // Interrupt is triggered until 532 #define EPI_FIFOLVL_WRFIFO_NFULL \ 533 0x00000040 // Trigger interrupt when WRFIFO is 537 #define EPI_FIFOLVL_RDFIFO_M 0x00000007 // Read FIFO 538 #define EPI_FIFOLVL_RDFIFO_EMPT 0x00000000 // Empty 539 #define EPI_FIFOLVL_RDFIFO_1 0x00000001 // Trigger when there are 1 or more 541 #define EPI_FIFOLVL_RDFIFO_2 0x00000002 // Trigger when there are 2 or more 543 #define EPI_FIFOLVL_RDFIFO_4 0x00000003 // Trigger when there are 4 or more 545 #define EPI_FIFOLVL_RDFIFO_6 0x00000004 // Trigger when there are 6 or more 547 #define EPI_FIFOLVL_RDFIFO_7 0x00000005 // Trigger when there are 7 or more 549 #define EPI_FIFOLVL_RDFIFO_8 0x00000006 // Trigger when there are 8 entries 557 #define EPI_WFIFOCNT_WTAV_M 0x00000007 // Available Write Transactions 558 #define EPI_WFIFOCNT_WTAV_S 0 565 #define EPI_DMATXCNT_TXCNT_M 0x0000FFFF // DMA Count 566 #define EPI_DMATXCNT_TXCNT_S 0 573 #define EPI_IM_DMAWRIM 0x00000010 // Write uDMA Interrupt Mask 574 #define EPI_IM_DMARDIM 0x00000008 // Read uDMA Interrupt Mask 575 #define EPI_IM_WRIM 0x00000004 // Write FIFO Empty Interrupt Mask 576 #define EPI_IM_RDIM 0x00000002 // Read FIFO Full Interrupt Mask 577 #define EPI_IM_ERRIM 0x00000001 // Error Interrupt Mask 584 #define EPI_RIS_DMAWRRIS 0x00000010 // Write uDMA Raw Interrupt Status 585 #define EPI_RIS_DMARDRIS 0x00000008 // Read uDMA Raw Interrupt Status 586 #define EPI_RIS_WRRIS 0x00000004 // Write Raw Interrupt Status 587 #define EPI_RIS_RDRIS 0x00000002 // Read Raw Interrupt Status 588 #define EPI_RIS_ERRRIS 0x00000001 // Error Raw Interrupt Status 595 #define EPI_MIS_DMAWRMIS 0x00000010 // Write uDMA Masked Interrupt 597 #define EPI_MIS_DMARDMIS 0x00000008 // Read uDMA Masked Interrupt 599 #define EPI_MIS_WRMIS 0x00000004 // Write Masked Interrupt Status 600 #define EPI_MIS_RDMIS 0x00000002 // Read Masked Interrupt Status 601 #define EPI_MIS_ERRMIS 0x00000001 // Error Masked Interrupt Status 608 #define EPI_EISC_DMAWRIC 0x00000010 // Write uDMA Interrupt Clear 609 #define EPI_EISC_DMARDIC 0x00000008 // Read uDMA Interrupt Clear 610 #define EPI_EISC_WTFULL 0x00000004 // Write FIFO Full Error 611 #define EPI_EISC_RSTALL 0x00000002 // Read Stalled Error 612 #define EPI_EISC_TOUT 0x00000001 // Timeout Error 619 #define EPI_HB8CFG3_WRHIGH 0x00200000 // CS2n WRITE Strobe Polarity 620 #define EPI_HB8CFG3_RDHIGH 0x00100000 // CS2n READ Strobe Polarity 621 #define EPI_HB8CFG3_ALEHIGH 0x00080000 // CS2n ALE Strobe Polarity 622 #define EPI_HB8CFG3_WRWS_M 0x000000C0 // CS2n Write Wait States 623 #define EPI_HB8CFG3_WRWS_2 0x00000000 // Active WRn is 2 EPI clocks 624 #define EPI_HB8CFG3_WRWS_4 0x00000040 // Active WRn is 4 EPI clocks 625 #define EPI_HB8CFG3_WRWS_6 0x00000080 // Active WRn is 6 EPI clocks 626 #define EPI_HB8CFG3_WRWS_8 0x000000C0 // Active WRn is 8 EPI clocks 627 #define EPI_HB8CFG3_RDWS_M 0x00000030 // CS2n Read Wait States 628 #define EPI_HB8CFG3_RDWS_2 0x00000000 // Active RDn is 2 EPI clocks 629 #define EPI_HB8CFG3_RDWS_4 0x00000010 // Active RDn is 4 EPI clocks 630 #define EPI_HB8CFG3_RDWS_6 0x00000020 // Active RDn is 6 EPI clocks 631 #define EPI_HB8CFG3_RDWS_8 0x00000030 // Active RDn is 8 EPI clocks 632 #define EPI_HB8CFG3_MODE_M 0x00000003 // CS2n Host Bus Sub-Mode 633 #define EPI_HB8CFG3_MODE_ADMUX 0x00000000 // ADMUX - AD[7:0] 634 #define EPI_HB8CFG3_MODE_AD 0x00000001 // ADNONMUX - D[7:0] 641 #define EPI_HB16CFG3_WRHIGH 0x00200000 // CS2n WRITE Strobe Polarity 642 #define EPI_HB16CFG3_RDHIGH 0x00100000 // CS2n READ Strobe Polarity 643 #define EPI_HB16CFG3_ALEHIGH 0x00080000 // CS2n ALE Strobe Polarity 644 #define EPI_HB16CFG3_WRCRE 0x00040000 // CS2n PSRAM Configuration 646 #define EPI_HB16CFG3_RDCRE 0x00020000 // CS2n PSRAM Configuration 648 #define EPI_HB16CFG3_BURST 0x00010000 // CS2n Burst Mode 649 #define EPI_HB16CFG3_WRWS_M 0x000000C0 // CS2n Write Wait States 650 #define EPI_HB16CFG3_WRWS_2 0x00000000 // Active WRn is 2 EPI clocks 651 #define EPI_HB16CFG3_WRWS_4 0x00000040 // Active WRn is 4 EPI clocks 652 #define EPI_HB16CFG3_WRWS_6 0x00000080 // Active WRn is 6 EPI clocks 653 #define EPI_HB16CFG3_WRWS_8 0x000000C0 // Active WRn is 8 EPI clocks 654 #define EPI_HB16CFG3_RDWS_M 0x00000030 // CS2n Read Wait States 655 #define EPI_HB16CFG3_RDWS_2 0x00000000 // Active RDn is 2 EPI clocks 656 #define EPI_HB16CFG3_RDWS_4 0x00000010 // Active RDn is 4 EPI clocks 657 #define EPI_HB16CFG3_RDWS_6 0x00000020 // Active RDn is 6 EPI clocks 658 #define EPI_HB16CFG3_RDWS_8 0x00000030 // Active RDn is 8 EPI clocks 659 #define EPI_HB16CFG3_MODE_M 0x00000003 // CS2n Host Bus Sub-Mode 660 #define EPI_HB16CFG3_MODE_ADMUX 0x00000000 // ADMUX - AD[15:0] 661 #define EPI_HB16CFG3_MODE_AD 0x00000001 // ADNONMUX - D[15:0] 668 #define EPI_HB16CFG4_WRHIGH 0x00200000 // CS3n WRITE Strobe Polarity 669 #define EPI_HB16CFG4_RDHIGH 0x00100000 // CS3n READ Strobe Polarity 670 #define EPI_HB16CFG4_ALEHIGH 0x00080000 // CS3n ALE Strobe Polarity 671 #define EPI_HB16CFG4_WRCRE 0x00040000 // CS3n PSRAM Configuration 673 #define EPI_HB16CFG4_RDCRE 0x00020000 // CS3n PSRAM Configuration 675 #define EPI_HB16CFG4_BURST 0x00010000 // CS3n Burst Mode 676 #define EPI_HB16CFG4_WRWS_M 0x000000C0 // CS3n Write Wait States 677 #define EPI_HB16CFG4_WRWS_2 0x00000000 // Active WRn is 2 EPI clocks 678 #define EPI_HB16CFG4_WRWS_4 0x00000040 // Active WRn is 4 EPI clocks 679 #define EPI_HB16CFG4_WRWS_6 0x00000080 // Active WRn is 6 EPI clocks 680 #define EPI_HB16CFG4_WRWS_8 0x000000C0 // Active WRn is 8 EPI clocks 681 #define EPI_HB16CFG4_RDWS_M 0x00000030 // CS3n Read Wait States 682 #define EPI_HB16CFG4_RDWS_2 0x00000000 // Active RDn is 2 EPI clocks 683 #define EPI_HB16CFG4_RDWS_4 0x00000010 // Active RDn is 4 EPI clocks 684 #define EPI_HB16CFG4_RDWS_6 0x00000020 // Active RDn is 6 EPI clocks 685 #define EPI_HB16CFG4_RDWS_8 0x00000030 // Active RDn is 8 EPI clocks 686 #define EPI_HB16CFG4_MODE_M 0x00000003 // CS3n Host Bus Sub-Mode 687 #define EPI_HB16CFG4_MODE_ADMUX 0x00000000 // ADMUX - AD[15:0] 688 #define EPI_HB16CFG4_MODE_AD 0x00000001 // ADNONMUX - D[15:0] 695 #define EPI_HB8CFG4_WRHIGH 0x00200000 // CS3n WRITE Strobe Polarity 696 #define EPI_HB8CFG4_RDHIGH 0x00100000 // CS2n READ Strobe Polarity 697 #define EPI_HB8CFG4_ALEHIGH 0x00080000 // CS3n ALE Strobe Polarity 698 #define EPI_HB8CFG4_WRWS_M 0x000000C0 // CS3n Write Wait States 699 #define EPI_HB8CFG4_WRWS_2 0x00000000 // Active WRn is 2 EPI clocks 700 #define EPI_HB8CFG4_WRWS_4 0x00000040 // Active WRn is 4 EPI clocks 701 #define EPI_HB8CFG4_WRWS_6 0x00000080 // Active WRn is 6 EPI clocks 702 #define EPI_HB8CFG4_WRWS_8 0x000000C0 // Active WRn is 8 EPI clocks 703 #define EPI_HB8CFG4_RDWS_M 0x00000030 // CS3n Read Wait States 704 #define EPI_HB8CFG4_RDWS_2 0x00000000 // Active RDn is 2 EPI clocks 705 #define EPI_HB8CFG4_RDWS_4 0x00000010 // Active RDn is 4 EPI clocks 706 #define EPI_HB8CFG4_RDWS_6 0x00000020 // Active RDn is 6 EPI clocks 707 #define EPI_HB8CFG4_RDWS_8 0x00000030 // Active RDn is 8 EPI clocks 708 #define EPI_HB8CFG4_MODE_M 0x00000003 // CS3n Host Bus Sub-Mode 709 #define EPI_HB8CFG4_MODE_ADMUX 0x00000000 // ADMUX - AD[7:0] 710 #define EPI_HB8CFG4_MODE_AD 0x00000001 // ADNONMUX - D[7:0] 717 #define EPI_HB8TIME_IRDYDLY_M 0x03000000 // CS0n Input Ready Delay 718 #define EPI_HB8TIME_CAPWIDTH_M 0x00003000 // CS0n Inter-transfer Capture 720 #define EPI_HB8TIME_WRWSM 0x00000010 // Write Wait State Minus One 721 #define EPI_HB8TIME_RDWSM 0x00000001 // Read Wait State Minus One 722 #define EPI_HB8TIME_IRDYDLY_S 24 723 #define EPI_HB8TIME_CAPWIDTH_S 12 730 #define EPI_HB16TIME_IRDYDLY_M 0x03000000 // CS0n Input Ready Delay 731 #define EPI_HB16TIME_PSRAMSZ_M 0x00070000 // PSRAM Row Size 732 #define EPI_HB16TIME_PSRAMSZ_0 0x00000000 // No row size limitation 733 #define EPI_HB16TIME_PSRAMSZ_128B \ 735 #define EPI_HB16TIME_PSRAMSZ_256B \ 737 #define EPI_HB16TIME_PSRAMSZ_512B \ 739 #define EPI_HB16TIME_PSRAMSZ_1KB \ 741 #define EPI_HB16TIME_PSRAMSZ_2KB \ 743 #define EPI_HB16TIME_PSRAMSZ_4KB \ 745 #define EPI_HB16TIME_PSRAMSZ_8KB \ 747 #define EPI_HB16TIME_CAPWIDTH_M 0x00003000 // CS0n Inter-transfer Capture 749 #define EPI_HB16TIME_WRWSM 0x00000010 // Write Wait State Minus One 750 #define EPI_HB16TIME_RDWSM 0x00000001 // Read Wait State Minus One 751 #define EPI_HB16TIME_IRDYDLY_S 24 752 #define EPI_HB16TIME_CAPWIDTH_S 12 759 #define EPI_HB8TIME2_IRDYDLY_M 0x03000000 // CS1n Input Ready Delay 760 #define EPI_HB8TIME2_CAPWIDTH_M 0x00003000 // CS1n Inter-transfer Capture 762 #define EPI_HB8TIME2_WRWSM 0x00000010 // CS1n Write Wait State Minus One 763 #define EPI_HB8TIME2_RDWSM 0x00000001 // CS1n Read Wait State Minus One 764 #define EPI_HB8TIME2_IRDYDLY_S 24 765 #define EPI_HB8TIME2_CAPWIDTH_S 12 773 #define EPI_HB16TIME2_IRDYDLY_M 0x03000000 // CS1n Input Ready Delay 774 #define EPI_HB16TIME2_PSRAMSZ_M 0x00070000 // PSRAM Row Size 775 #define EPI_HB16TIME2_PSRAMSZ_0 0x00000000 // No row size limitation 776 #define EPI_HB16TIME2_PSRAMSZ_128B \ 778 #define EPI_HB16TIME2_PSRAMSZ_256B \ 780 #define EPI_HB16TIME2_PSRAMSZ_512B \ 782 #define EPI_HB16TIME2_PSRAMSZ_1KB \ 784 #define EPI_HB16TIME2_PSRAMSZ_2KB \ 786 #define EPI_HB16TIME2_PSRAMSZ_4KB \ 788 #define EPI_HB16TIME2_PSRAMSZ_8KB \ 790 #define EPI_HB16TIME2_CAPWIDTH_M \ 791 0x00003000 // CS1n Inter-transfer Capture 793 #define EPI_HB16TIME2_WRWSM 0x00000010 // CS1n Write Wait State Minus One 794 #define EPI_HB16TIME2_RDWSM 0x00000001 // CS1n Read Wait State Minus One 795 #define EPI_HB16TIME2_IRDYDLY_S 24 796 #define EPI_HB16TIME2_CAPWIDTH_S \ 805 #define EPI_HB16TIME3_IRDYDLY_M 0x03000000 // CS2n Input Ready Delay 806 #define EPI_HB16TIME3_PSRAMSZ_M 0x00070000 // PSRAM Row Size 807 #define EPI_HB16TIME3_PSRAMSZ_0 0x00000000 // No row size limitation 808 #define EPI_HB16TIME3_PSRAMSZ_128B \ 810 #define EPI_HB16TIME3_PSRAMSZ_256B \ 812 #define EPI_HB16TIME3_PSRAMSZ_512B \ 814 #define EPI_HB16TIME3_PSRAMSZ_1KB \ 816 #define EPI_HB16TIME3_PSRAMSZ_2KB \ 818 #define EPI_HB16TIME3_PSRAMSZ_4KB \ 820 #define EPI_HB16TIME3_PSRAMSZ_8KB \ 822 #define EPI_HB16TIME3_CAPWIDTH_M \ 823 0x00003000 // CS2n Inter-transfer Capture 825 #define EPI_HB16TIME3_WRWSM 0x00000010 // CS2n Write Wait State Minus One 826 #define EPI_HB16TIME3_RDWSM 0x00000001 // CS2n Read Wait State Minus One 827 #define EPI_HB16TIME3_IRDYDLY_S 24 828 #define EPI_HB16TIME3_CAPWIDTH_S \ 836 #define EPI_HB8TIME3_IRDYDLY_M 0x03000000 // CS2n Input Ready Delay 837 #define EPI_HB8TIME3_CAPWIDTH_M 0x00003000 // CS2n Inter-transfer Capture 839 #define EPI_HB8TIME3_WRWSM 0x00000010 // CS2n Write Wait State Minus One 840 #define EPI_HB8TIME3_RDWSM 0x00000001 // CS2n Read Wait State Minus One 841 #define EPI_HB8TIME3_IRDYDLY_S 24 842 #define EPI_HB8TIME3_CAPWIDTH_S 12 849 #define EPI_HB8TIME4_IRDYDLY_M 0x03000000 // CS3n Input Ready Delay 850 #define EPI_HB8TIME4_CAPWIDTH_M 0x00003000 // CS3n Inter-transfer Capture 852 #define EPI_HB8TIME4_WRWSM 0x00000010 // CS3n Write Wait State Minus One 853 #define EPI_HB8TIME4_RDWSM 0x00000001 // CS3n Read Wait State Minus One 854 #define EPI_HB8TIME4_IRDYDLY_S 24 855 #define EPI_HB8TIME4_CAPWIDTH_S 12 863 #define EPI_HB16TIME4_IRDYDLY_M 0x03000000 // CS3n Input Ready Delay 864 #define EPI_HB16TIME4_PSRAMSZ_M 0x00070000 // PSRAM Row Size 865 #define EPI_HB16TIME4_PSRAMSZ_0 0x00000000 // No row size limitation 866 #define EPI_HB16TIME4_PSRAMSZ_128B \ 868 #define EPI_HB16TIME4_PSRAMSZ_256B \ 870 #define EPI_HB16TIME4_PSRAMSZ_512B \ 872 #define EPI_HB16TIME4_PSRAMSZ_1KB \ 874 #define EPI_HB16TIME4_PSRAMSZ_2KB \ 876 #define EPI_HB16TIME4_PSRAMSZ_4KB \ 878 #define EPI_HB16TIME4_PSRAMSZ_8KB \ 880 #define EPI_HB16TIME4_CAPWIDTH_M \ 881 0x00003000 // CS3n Inter-transfer Capture 883 #define EPI_HB16TIME4_WRWSM 0x00000010 // CS3n Write Wait State Minus One 884 #define EPI_HB16TIME4_RDWSM 0x00000001 // CS3n Read Wait State Minus One 885 #define EPI_HB16TIME4_IRDYDLY_S 24 886 #define EPI_HB16TIME4_CAPWIDTH_S \ 894 #define EPI_HBPSRAM_CR_M 0x001FFFFF // PSRAM Config Register 895 #define EPI_HBPSRAM_CR_S 0 910 #define EPI_FIFOLVL_WRFIFO_1_4 0x00000020 // Trigger when there are up to 3 912 #define EPI_FIFOLVL_WRFIFO_1_2 0x00000030 // Trigger when there are up to 2 914 #define EPI_FIFOLVL_WRFIFO_3_4 0x00000040 // Trigger when there is 1 space 916 #define EPI_FIFOLVL_RDFIFO_1_8 0x00000001 // Trigger when there are 1 or more 918 #define EPI_FIFOLVL_RDFIFO_1_4 0x00000002 // Trigger when there are 2 or more 920 #define EPI_FIFOLVL_RDFIFO_1_2 0x00000003 // Trigger when there are 4 or more 922 #define EPI_FIFOLVL_RDFIFO_3_4 0x00000004 // Trigger when there are 6 or more 924 #define EPI_FIFOLVL_RDFIFO_7_8 0x00000005 // Trigger when there are 7 or more 926 #define EPI_FIFOLVL_RDFIFO_FULL 0x00000006 // Trigger when there are 8 entries 931 #endif // __HW_EPI_H__
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