hw_des.h
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1 //*****************************************************************************
2 //
3 // hw_des.h - Macros used when accessing the DES hardware.
4 //
5 // Copyright (c) 2012-2017 Texas Instruments Incorporated. All rights reserved.
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36 //*****************************************************************************
37 
38 #ifndef __HW_DES_H__
39 #define __HW_DES_H__
40 
41 //*****************************************************************************
42 //
43 // The following are defines for the DES register offsets.
44 //
45 //*****************************************************************************
46 #define DES_O_KEY3_L 0x00000000 // DES Key 3 LSW for 192-Bit Key
47 #define DES_O_KEY3_H 0x00000004 // DES Key 3 MSW for 192-Bit Key
48 #define DES_O_KEY2_L 0x00000008 // DES Key 2 LSW for 128-Bit Key
49 #define DES_O_KEY2_H 0x0000000C // DES Key 2 MSW for 128-Bit Key
50 #define DES_O_KEY1_L 0x00000010 // DES Key 1 LSW for 64-Bit Key
51 #define DES_O_KEY1_H 0x00000014 // DES Key 1 MSW for 64-Bit Key
52 #define DES_O_IV_L 0x00000018 // DES Initialization Vector
53 #define DES_O_IV_H 0x0000001C // DES Initialization Vector
54 #define DES_O_CTRL 0x00000020 // DES Control
55 #define DES_O_LENGTH 0x00000024 // DES Cryptographic Data Length
56 #define DES_O_DATA_L 0x00000028 // DES LSW Data RW
57 #define DES_O_DATA_H 0x0000002C // DES MSW Data RW
58 #define DES_O_REVISION 0x00000030 // DES Revision Number
59 #define DES_O_SYSCONFIG 0x00000034 // DES System Configuration
60 #define DES_O_SYSSTATUS 0x00000038 // DES System Status
61 #define DES_O_IRQSTATUS 0x0000003C // DES Interrupt Status
62 #define DES_O_IRQENABLE 0x00000040 // DES Interrupt Enable
63 #define DES_O_DIRTYBITS 0x00000044 // DES Dirty Bits
64 #define DES_O_DMAIM 0xFFFF8030 // DES DMA Interrupt Mask
65 #define DES_O_DMARIS 0xFFFF8034 // DES DMA Raw Interrupt Status
66 #define DES_O_DMAMIS 0xFFFF8038 // DES DMA Masked Interrupt Status
67 #define DES_O_DMAIC 0xFFFF803C // DES DMA Interrupt Clear
68 
69 //*****************************************************************************
70 //
71 // The following are defines for the bit fields in the DES_O_KEY3_L register.
72 //
73 //*****************************************************************************
74 #define DES_KEY3_L_KEY_M 0xFFFFFFFF // Key Data
75 #define DES_KEY3_L_KEY_S 0
76 
77 //*****************************************************************************
78 //
79 // The following are defines for the bit fields in the DES_O_KEY3_H register.
80 //
81 //*****************************************************************************
82 #define DES_KEY3_H_KEY_M 0xFFFFFFFF // Key Data
83 #define DES_KEY3_H_KEY_S 0
84 
85 //*****************************************************************************
86 //
87 // The following are defines for the bit fields in the DES_O_KEY2_L register.
88 //
89 //*****************************************************************************
90 #define DES_KEY2_L_KEY_M 0xFFFFFFFF // Key Data
91 #define DES_KEY2_L_KEY_S 0
92 
93 //*****************************************************************************
94 //
95 // The following are defines for the bit fields in the DES_O_KEY2_H register.
96 //
97 //*****************************************************************************
98 #define DES_KEY2_H_KEY_M 0xFFFFFFFF // Key Data
99 #define DES_KEY2_H_KEY_S 0
100 
101 //*****************************************************************************
102 //
103 // The following are defines for the bit fields in the DES_O_KEY1_L register.
104 //
105 //*****************************************************************************
106 #define DES_KEY1_L_KEY_M 0xFFFFFFFF // Key Data
107 #define DES_KEY1_L_KEY_S 0
108 
109 //*****************************************************************************
110 //
111 // The following are defines for the bit fields in the DES_O_KEY1_H register.
112 //
113 //*****************************************************************************
114 #define DES_KEY1_H_KEY_M 0xFFFFFFFF // Key Data
115 #define DES_KEY1_H_KEY_S 0
116 
117 //*****************************************************************************
118 //
119 // The following are defines for the bit fields in the DES_O_IV_L register.
120 //
121 //*****************************************************************************
122 #define DES_IV_L_M 0xFFFFFFFF // Initialization vector for CBC,
123  // CFB modes (LSW)
124 #define DES_IV_L_S 0
125 
126 //*****************************************************************************
127 //
128 // The following are defines for the bit fields in the DES_O_IV_H register.
129 //
130 //*****************************************************************************
131 #define DES_IV_H_M 0xFFFFFFFF // Initialization vector for CBC,
132  // CFB modes (MSW)
133 #define DES_IV_H_S 0
134 
135 //*****************************************************************************
136 //
137 // The following are defines for the bit fields in the DES_O_CTRL register.
138 //
139 //*****************************************************************************
140 #define DES_CTRL_CONTEXT 0x80000000 // If 1, this read-only status bit
141  // indicates that the context data
142  // registers can be overwritten and
143  // the host is permitted to write
144  // the next context
145 #define DES_CTRL_MODE_M 0x00000030 // Select CBC, ECB or CFB mode0x0:
146  // ECB mode0x1: CBC mode0x2: CFB
147  // mode0x3: reserved
148 #define DES_CTRL_TDES 0x00000008 // Select DES or triple DES
149  // encryption/decryption
150 #define DES_CTRL_DIRECTION 0x00000004 // Select encryption/decryption
151  // 0x0: decryption is selected0x1:
152  // Encryption is selected
153 #define DES_CTRL_INPUT_READY 0x00000002 // When 1, ready to encrypt/decrypt
154  // data
155 #define DES_CTRL_OUTPUT_READY 0x00000001 // When 1, Data decrypted/encrypted
156  // ready
157 #define DES_CTRL_MODE_S 4
158 
159 //*****************************************************************************
160 //
161 // The following are defines for the bit fields in the DES_O_LENGTH register.
162 //
163 //*****************************************************************************
164 #define DES_LENGTH_M 0xFFFFFFFF // Cryptographic data length in
165  // bytes for all modes
166 #define DES_LENGTH_S 0
167 
168 //*****************************************************************************
169 //
170 // The following are defines for the bit fields in the DES_O_DATA_L register.
171 //
172 //*****************************************************************************
173 #define DES_DATA_L_M 0xFFFFFFFF // Data for encryption/decryption,
174  // LSW
175 #define DES_DATA_L_S 0
176 
177 //*****************************************************************************
178 //
179 // The following are defines for the bit fields in the DES_O_DATA_H register.
180 //
181 //*****************************************************************************
182 #define DES_DATA_H_M 0xFFFFFFFF // Data for encryption/decryption,
183  // MSW
184 #define DES_DATA_H_S 0
185 
186 //*****************************************************************************
187 //
188 // The following are defines for the bit fields in the DES_O_REVISION register.
189 //
190 //*****************************************************************************
191 #define DES_REVISION_M 0xFFFFFFFF // Revision number
192 #define DES_REVISION_S 0
193 
194 //*****************************************************************************
195 //
196 // The following are defines for the bit fields in the DES_O_SYSCONFIG
197 // register.
198 //
199 //*****************************************************************************
200 #define DES_SYSCONFIG_DMA_REQ_CONTEXT_IN_EN \
201  0x00000080 // DMA Request Context In Enable
202 #define DES_SYSCONFIG_DMA_REQ_DATA_OUT_EN \
203  0x00000040 // DMA Request Data Out Enable
204 #define DES_SYSCONFIG_DMA_REQ_DATA_IN_EN \
205  0x00000020 // DMA Request Data In Enable
206 #define DES_SYSCONFIG_SIDLE_M 0x0000000C // Sidle mode
207 #define DES_SYSCONFIG_SIDLE_FORCE \
208  0x00000000 // Force-idle mode
209 #define DES_SYSCONFIG_SOFTRESET 0x00000002 // Soft reset
210 
211 //*****************************************************************************
212 //
213 // The following are defines for the bit fields in the DES_O_SYSSTATUS
214 // register.
215 //
216 //*****************************************************************************
217 #define DES_SYSSTATUS_RESETDONE 0x00000001 // Reset Done
218 
219 //*****************************************************************************
220 //
221 // The following are defines for the bit fields in the DES_O_IRQSTATUS
222 // register.
223 //
224 //*****************************************************************************
225 #define DES_IRQSTATUS_DATA_OUT 0x00000004 // This bit indicates data output
226  // interrupt is active and triggers
227  // the interrupt output
228 #define DES_IRQSTATUS_DATA_IN 0x00000002 // This bit indicates data input
229  // interrupt is active and triggers
230  // the interrupt output
231 #define DES_IRQSTATUS_CONTEX_IN 0x00000001 // This bit indicates context
232  // interrupt is active and triggers
233  // the interrupt output
234 
235 //*****************************************************************************
236 //
237 // The following are defines for the bit fields in the DES_O_IRQENABLE
238 // register.
239 //
240 //*****************************************************************************
241 #define DES_IRQENABLE_M_DATA_OUT \
242  0x00000004 // If this bit is set to 1 the data
243  // output interrupt is enabled
244 #define DES_IRQENABLE_M_DATA_IN 0x00000002 // If this bit is set to 1 the data
245  // input interrupt is enabled
246 #define DES_IRQENABLE_M_CONTEX_IN \
247  0x00000001 // If this bit is set to 1 the
248  // context interrupt is enabled
249 
250 //*****************************************************************************
251 //
252 // The following are defines for the bit fields in the DES_O_DIRTYBITS
253 // register.
254 //
255 //*****************************************************************************
256 #define DES_DIRTYBITS_S_DIRTY 0x00000002 // This bit is set to 1 by the
257  // module if any of the DES_*
258  // registers is written
259 #define DES_DIRTYBITS_S_ACCESS 0x00000001 // This bit is set to 1 by the
260  // module if any of the DES_*
261  // registers is read
262 
263 //*****************************************************************************
264 //
265 // The following are defines for the bit fields in the DES_O_DMAIM register.
266 //
267 //*****************************************************************************
268 #define DES_DMAIM_DOUT 0x00000004 // Data Out DMA Done Interrupt Mask
269 #define DES_DMAIM_DIN 0x00000002 // Data In DMA Done Interrupt Mask
270 #define DES_DMAIM_CIN 0x00000001 // Context In DMA Done Interrupt
271  // Mask
272 
273 //*****************************************************************************
274 //
275 // The following are defines for the bit fields in the DES_O_DMARIS register.
276 //
277 //*****************************************************************************
278 #define DES_DMARIS_DOUT 0x00000004 // Data Out DMA Done Raw Interrupt
279  // Status
280 #define DES_DMARIS_DIN 0x00000002 // Data In DMA Done Raw Interrupt
281  // Status
282 #define DES_DMARIS_CIN 0x00000001 // Context In DMA Done Raw
283  // Interrupt Status
284 
285 //*****************************************************************************
286 //
287 // The following are defines for the bit fields in the DES_O_DMAMIS register.
288 //
289 //*****************************************************************************
290 #define DES_DMAMIS_DOUT 0x00000004 // Data Out DMA Done Masked
291  // Interrupt Status
292 #define DES_DMAMIS_DIN 0x00000002 // Data In DMA Done Masked
293  // Interrupt Status
294 #define DES_DMAMIS_CIN 0x00000001 // Context In DMA Done Raw
295  // Interrupt Status
296 
297 //*****************************************************************************
298 //
299 // The following are defines for the bit fields in the DES_O_DMAIC register.
300 //
301 //*****************************************************************************
302 #define DES_DMAIC_DOUT 0x00000004 // Data Out DMA Done Interrupt
303  // Clear
304 #define DES_DMAIC_DIN 0x00000002 // Data In DMA Done Interrupt Clear
305 #define DES_DMAIC_CIN 0x00000001 // Context In DMA Done Raw
306  // Interrupt Status
307 
308 #endif // __HW_DES_H__
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