sysctl.h
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32 #ifndef __SYSCTL_H__
33 #define __SYSCTL_H__
34 
35 #include <stdint.h>
36 #include <ti/devices/msp432p4xx/inc/msp.h>
37 
38 /* Define to ensure that our current MSP432 has the SYSCTL module. This
39  definition is included in the device specific header file */
40 #ifdef __MCU_HAS_SYSCTL__
41 
42 //*****************************************************************************
43 //
46 //
47 //*****************************************************************************
48 
49 //*****************************************************************************
50 //
51 // If building with a C++ compiler, make all of the definitions in this header
52 // have a C binding.
53 //
54 //*****************************************************************************
55 #ifdef __cplusplus
56 extern "C"
57 {
58 #endif
59 
60 //*****************************************************************************
61 //
62 // Control specific variables
63 //
64 //*****************************************************************************
65 #define SYSCTL_SRAM_BANK7 SYSCTL_SRAM_BANKEN_BNK7_EN
66 #define SYSCTL_SRAM_BANK6 SYSCTL_SRAM_BANKEN_BNK6_EN
67 #define SYSCTL_SRAM_BANK5 SYSCTL_SRAM_BANKEN_BNK5_EN
68 #define SYSCTL_SRAM_BANK4 SYSCTL_SRAM_BANKEN_BNK4_EN
69 #define SYSCTL_SRAM_BANK3 SYSCTL_SRAM_BANKEN_BNK3_EN
70 #define SYSCTL_SRAM_BANK2 SYSCTL_SRAM_BANKEN_BNK2_EN
71 #define SYSCTL_SRAM_BANK1 SYSCTL_SRAM_BANKEN_BNK1_EN
72 
73 #define SYSCTL_HARD_RESET 1
74 #define SYSCTL_SOFT_RESET 0
75 
76 #define SYSCTL_PERIPH_DMA SYSCTL_PERIHALT_CTL_HALT_DMA
77 #define SYSCTL_PERIPH_WDT SYSCTL_PERIHALT_CTL_HALT_WDT
78 #define SYSCTL_PERIPH_ADC SYSCTL_PERIHALT_CTL_HALT_ADC
79 #define SYSCTL_PERIPH_EUSCIB3 SYSCTL_PERIHALT_CTL_HALT_EUB3
80 #define SYSCTL_PERIPH_EUSCIB2 SYSCTL_PERIHALT_CTL_HALT_EUB2
81 #define SYSCTL_PERIPH_EUSCIB1 SYSCTL_PERIHALT_CTL_HALT_EUB1
82 #define SYSCTL_PERIPH_EUSCIB0 SYSCTL_PERIHALT_CTL_HALT_EUB0
83 #define SYSCTL_PERIPH_EUSCIA3 SYSCTL_PERIHALT_CTL_HALT_EUA3
84 #define SYSCTL_PERIPH_EUSCIA2 SYSCTL_PERIHALT_CTL_HALT_EUA2
85 #define SYSCTL_PERIPH_EUSCIA1 SYSCTL_PERIHALT_CTL_HALT_EUA1
86 #define SYSCTL_PERIPH_EUSCIA0 SYSCTL_PERIHALT_CTL_HALT_EUA0
87 #define SYSCTL_PERIPH_TIMER32_0_MODULE SYSCTL_PERIHALT_CTL_HALT_T32_0
88 #define SYSCTL_PERIPH_TIMER16_3 SYSCTL_PERIHALT_CTL_HALT_T16_3
89 #define SYSCTL_PERIPH_TIMER16_2 SYSCTL_PERIHALT_CTL_HALT_T16_2
90 #define SYSCTL_PERIPH_TIMER16_1 SYSCTL_PERIHALT_CTL_HALT_T16_1
91 #define SYSCTL_PERIPH_TIMER16_0 SYSCTL_PERIHALT_CTL_HALT_T16_0
92 
93 #define SYSCTL_NMIPIN_SRC SYSCTL_NMI_CTLSTAT_PIN_SRC
94 #define SYSCTL_PCM_SRC SYSCTL_NMI_CTLSTAT_PCM_SRC
95 #define SYSCTL_PSS_SRC SYSCTL_NMI_CTLSTAT_PSS_SRC
96 #define SYSCTL_CS_SRC SYSCTL_NMI_CTLSTAT_CS_SRC
97 
98 #define SYSCTL_REBOOT_KEY 0x6900
99 
100 #define SYSCTL_1_2V_REF (uint32_t)&TLV->ADC14_REF1P2V_TS30C - (uint32_t)TLV_BASE
101 #define SYSCTL_1_45V_REF (uint32_t)&TLV->ADC14_REF1P45V_TS30C - (uint32_t)TLV_BASE
102 #define SYSCTL_2_5V_REF (uint32_t)&TLV->ADC14_REF2P5V_TS30C - (uint32_t)TLV_BASE
103 
104 #define SYSCTL_85_DEGREES_C 4
105 #define SYSCTL_30_DEGREES_C 0
106 
107 
108 #define TLV_START 0x00201004
109 #define TLV_TAG_RESERVED1 1
110 #define TLV_TAG_RESERVED2 2
111 #define TLV_TAG_CS 3
112 #define TLV_TAG_FLASHCTL 4
113 #define TLV_TAG_ADC14 5
114 #define TLV_TAG_RESERVED6 6
115 #define TLV_TAG_RESERVED7 7
116 #define TLV_TAG_REF 8
117 #define TLV_TAG_RESERVED9 9
118 #define TLV_TAG_RESERVED10 10
119 #define TLV_TAG_DEVINFO 11
120 #define TLV_TAG_DIEREC 12
121 #define TLV_TAG_RANDNUM 13
122 #define TLV_TAG_RESERVED14 14
123 #define TLV_TAG_BSL 15
124 #define TLV_TAGEND 0x0BD0E11D
125 
126 //*****************************************************************************
127 //
128 // Structures for TLV definitions
129 //
130 //*****************************************************************************
131 typedef struct
132 {
134  uint32_t maxErasePulses;
136 
137 typedef struct
138 {
155 
157 
158 //*****************************************************************************
159 //
160 // Prototypes for the APIs.
161 //
162 //*****************************************************************************
163 
164 //*****************************************************************************
165 //
169 //
170 //*****************************************************************************
171 extern uint_least32_t SysCtl_getSRAMSize(void);
172 
173 //*****************************************************************************
174 //
178 //
179 //*****************************************************************************
180 extern uint_least32_t SysCtl_getFlashSize(void);
181 
182 //*****************************************************************************
183 //
187 //
188 //*****************************************************************************
189 extern void SysCtl_rebootDevice(void);
190 
191 //*****************************************************************************
192 //
231 //
232 //*****************************************************************************
233 extern void SysCtl_getTLVInfo(uint_fast8_t tag, uint_fast8_t instance,
234  uint_fast8_t *length, uint32_t **data_address);
235 
236 //*****************************************************************************
237 //
258 //
259 //*****************************************************************************
260 extern void SysCtl_enableSRAMBank(uint_fast8_t sramBank);
261 
262 //*****************************************************************************
263 //
283 //
284 //*****************************************************************************
285 extern void SysCtl_disableSRAMBank(uint_fast8_t sramBank);
286 
287 //*****************************************************************************
288 //
309 //
310 //*****************************************************************************
311 extern void SysCtl_enableSRAMBankRetention(uint_fast8_t sramBank);
312 
313 //*****************************************************************************
314 //
334 //
335 //
336 //*****************************************************************************
337 extern void SysCtl_disableSRAMBankRetention(uint_fast8_t sramBank);
338 
339 //*****************************************************************************
340 //
366 //
367 //
368 //*****************************************************************************
369 extern void SysCtl_enablePeripheralAtCPUHalt(uint_fast16_t devices);
370 
371 //*****************************************************************************
372 //
400 //
401 //
402 //*****************************************************************************
403 extern void SysCtl_disablePeripheralAtCPUHalt(uint_fast16_t devices);
404 
405 //*****************************************************************************
406 //
416 //
417 //
418 //*****************************************************************************
419 extern void SysCtl_setWDTTimeoutResetType(uint_fast8_t resetType);
420 
421 //*****************************************************************************
422 //
433 //
434 //
435 //*****************************************************************************
436 extern void SysCtl_setWDTPasswordViolationResetType(uint_fast8_t resetType);
437 
438 //*****************************************************************************
439 //
450 //
451 //*****************************************************************************
452 extern void SysCtl_disableNMISource(uint_fast8_t flags);
453 
454 //*****************************************************************************
455 //
466 //
467 //*****************************************************************************
468 extern void SysCtl_enableNMISource(uint_fast8_t flags);
469 
470 //*****************************************************************************
471 //
475 //
476 //*****************************************************************************
477 extern uint_fast8_t SysCtl_getNMISourceStatus(void);
478 
479 //*****************************************************************************
480 //
485 //
486 //
487 //*****************************************************************************
488 extern void SysCtl_enableGlitchFilter(void);
489 
490 //*****************************************************************************
491 //
496 //
497 //
498 //*****************************************************************************
499 extern void SysCtl_disableGlitchFilter(void);
500 
501 //*****************************************************************************
502 //
521 //
522 //
523 //*****************************************************************************
524 extern uint_fast16_t SysCtl_getTempCalibrationConstant(uint32_t refVoltage,
525  uint32_t temperature);
526 
527 //*****************************************************************************
528 //
529 // Mark the end of the C bindings section for C++ compilers.
530 //
531 //*****************************************************************************
532 #ifdef __cplusplus
533 }
534 #endif
535 
536 //*****************************************************************************
537 //
538 // Close the Doxygen group.
540 //
541 //*****************************************************************************
542 
543 #endif /* __MCU_HAS_SYSCTL__ */
544 
545 #endif // __SYSCTL_H__
uint32_t rDCOIR_MAXNEGTUNE_RSEL5
Definition: sysctl.h:144
uint32_t maxErasePulses
Definition: sysctl.h:134
void SysCtl_enableSRAMBankRetention(uint_fast8_t sramBank)
Definition: sysctl.c:209
uint_fast16_t SysCtl_getTempCalibrationConstant(uint32_t refVoltage, uint32_t temperature)
Definition: sysctl.c:278
uint32_t rDCOIR_FCAL_RSEL5
Definition: sysctl.h:140
uint32_t rDCOIR_CONSTK_RSEL04
Definition: sysctl.h:145
uint_fast8_t SysCtl_getNMISourceStatus(void)
Definition: sysctl.c:146
void SysCtl_disableGlitchFilter(void)
Definition: sysctl.c:273
void SysCtl_getTLVInfo(uint_fast8_t tag, uint_fast8_t instance, uint_fast8_t *length, uint32_t **data_address)
Definition: sysctl.c:85
void SysCtl_enableGlitchFilter(void)
Definition: sysctl.c:268
uint32_t rDCOIR_FCAL_RSEL04
Definition: sysctl.h:139
uint_least32_t SysCtl_getFlashSize(void)
Definition: sysctl.c:131
void SysCtl_setWDTPasswordViolationResetType(uint_fast8_t resetType)
Definition: sysctl.c:257
uint32_t rDCOER_FCAL_RSEL04
Definition: sysctl.h:147
uint32_t rDCOER_MAXNEGTUNE_RSEL5
Definition: sysctl.h:152
Definition: sysctl.h:131
uint_least32_t SysCtl_getSRAMSize(void)
Definition: sysctl.c:126
uint32_t rDCOIR_MAXNEGTUNE_RSEL04
Definition: sysctl.h:142
void SysCtl_disableSRAMBankRetention(uint_fast8_t sramBank)
Definition: sysctl.c:220
Definition: sysctl.h:137
uint32_t rDCOER_FCAL_RSEL5
Definition: sysctl.h:148
void SysCtl_setWDTTimeoutResetType(uint_fast8_t resetType)
Definition: sysctl.c:248
uint32_t rDCOER_MAXPOSTUNE_RSEL5
Definition: sysctl.h:151
uint32_t rDCOIR_MAXPOSTUNE_RSEL04
Definition: sysctl.h:141
void SysCtl_disableSRAMBank(uint_fast8_t sramBank)
Definition: sysctl.c:165
void SysCtl_disableNMISource(uint_fast8_t flags)
Definition: sysctl.c:136
uint32_t rDCOER_MAXNEGTUNE_RSEL04
Definition: sysctl.h:150
uint32_t rDCOIR_CONSTK_RSEL5
Definition: sysctl.h:146
uint32_t rDCOER_CONSTK_RSEL04
Definition: sysctl.h:153
uint32_t rDCOIR_MAXPOSTUNE_RSEL5
Definition: sysctl.h:143
uint32_t maxProgramPulses
Definition: sysctl.h:133
uint32_t rDCOER_MAXPOSTUNE_RSEL04
Definition: sysctl.h:149
void SysCtl_enablePeripheralAtCPUHalt(uint_fast16_t devices)
Definition: sysctl.c:236
uint32_t rDCOER_CONSTK_RSEL5
Definition: sysctl.h:154
void SysCtl_disablePeripheralAtCPUHalt(uint_fast16_t devices)
Definition: sysctl.c:242
void SysCtl_rebootDevice(void)
Definition: sysctl.c:231
void SysCtl_enableNMISource(uint_fast8_t flags)
Definition: sysctl.c:141
void SysCtl_enableSRAMBank(uint_fast8_t sramBank)
Definition: sysctl.c:154

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