110 #ifndef ti_drivers_spi_SPIMSP432DMA__include 111 #define ti_drivers_spi_SPIMSP432DMA__include 119 #include <ti/devices/DeviceFamily.h> 121 #include <ti/drivers/dpl/HwiP.h> 122 #include <ti/drivers/dpl/SemaphoreP.h> 177 #define SPIMSP432DMA_P1_0_UCA0STE 0x00000110 178 #define SPIMSP432DMA_P1_1_UCA0CLK 0x00000111 179 #define SPIMSP432DMA_P1_2_UCA0SOMI 0x00000112 180 #define SPIMSP432DMA_P1_3_UCA0SIMO 0x00000113 183 #define SPIMSP432DMA_P1_4_UCB0STE 0x00000114 184 #define SPIMSP432DMA_P1_5_UCB0CLK 0x00000115 185 #define SPIMSP432DMA_P1_6_UCB0SIMO 0x00000116 186 #define SPIMSP432DMA_P1_7_UCB0SOMI 0x00000117 189 #define SPIMSP432DMA_P2_0_UCA0CLK ((PMAP_UCA0CLK << 10) | 0x20) 190 #define SPIMSP432DMA_P2_0_UCA0SIMO ((PMAP_UCA0SIMO << 10) | 0x20) 191 #define SPIMSP432DMA_P2_0_UCA0SOMI ((PMAP_UCA0SOMI << 10) | 0x20) 192 #define SPIMSP432DMA_P2_0_UCA1STE ((PMAP_UCA1STE << 10) | 0x20) 193 #define SPIMSP432DMA_P2_0_UCA1CLK ((PMAP_UCA1CLK << 10) | 0x20) 194 #define SPIMSP432DMA_P2_0_UCA1SIMO ((PMAP_UCA1SIMO << 10) | 0x20) 195 #define SPIMSP432DMA_P2_0_UCA1SOMI ((PMAP_UCA1SOMI << 10) | 0x20) 196 #define SPIMSP432DMA_P2_0_UCA2CLK ((PMAP_UCA2CLK << 10) | 0x20) 197 #define SPIMSP432DMA_P2_0_UCA2SIMO ((PMAP_UCA2SIMO << 10) | 0x20) 198 #define SPIMSP432DMA_P2_0_UCA2SOMI ((PMAP_UCA2SOMI << 10) | 0x20) 199 #define SPIMSP432DMA_P2_0_UCB0CLK ((PMAP_UCB0CLK << 10) | 0x20) 200 #define SPIMSP432DMA_P2_0_UCB0SIMO ((PMAP_UCB0SIMO << 10) | 0x20) 201 #define SPIMSP432DMA_P2_0_UCB0SOMI ((PMAP_UCB0SOMI << 10) | 0x20) 202 #define SPIMSP432DMA_P2_0_UCB2CLK ((PMAP_UCB2CLK << 10) | 0x20) 203 #define SPIMSP432DMA_P2_0_UCB2SIMO ((PMAP_UCB2SIMO << 10) | 0x20) 204 #define SPIMSP432DMA_P2_0_UCB2SOMI ((PMAP_UCB2SOMI << 10) | 0x20) 205 #define SPIMSP432DMA_P2_0_UCA2STE ((PMAP_UCA2STE << 10) | 0x20) 206 #define SPIMSP432DMA_P2_0_UCB2STE ((PMAP_UCB2STE << 10) | 0x20) 209 #define SPIMSP432DMA_P2_1_UCA0CLK ((PMAP_UCA0CLK << 10) | 0x21) 210 #define SPIMSP432DMA_P2_1_UCA0SIMO ((PMAP_UCA0SIMO << 10) | 0x21) 211 #define SPIMSP432DMA_P2_1_UCA0SOMI ((PMAP_UCA0SOMI << 10) | 0x21) 212 #define SPIMSP432DMA_P2_1_UCA1CLK ((PMAP_UCA1CLK << 10) | 0x21) 213 #define SPIMSP432DMA_P2_1_UCA1SIMO ((PMAP_UCA1SIMO << 10) | 0x21) 214 #define SPIMSP432DMA_P2_1_UCA1SOMI ((PMAP_UCA1SOMI << 10) | 0x21) 215 #define SPIMSP432DMA_P2_1_UCA2CLK ((PMAP_UCA2CLK << 10) | 0x21) 216 #define SPIMSP432DMA_P2_1_UCA2SIMO ((PMAP_UCA2SIMO << 10) | 0x21) 217 #define SPIMSP432DMA_P2_1_UCA2SOMI ((PMAP_UCA2SOMI << 10) | 0x21) 218 #define SPIMSP432DMA_P2_1_UCB0CLK ((PMAP_UCB0CLK << 10) | 0x21) 219 #define SPIMSP432DMA_P2_1_UCB0SIMO ((PMAP_UCB0SIMO << 10) | 0x21) 220 #define SPIMSP432DMA_P2_1_UCB0SOMI ((PMAP_UCB0SOMI << 10) | 0x21) 221 #define SPIMSP432DMA_P2_1_UCB2CLK ((PMAP_UCB2CLK << 10) | 0x21) 222 #define SPIMSP432DMA_P2_1_UCB2SIMO ((PMAP_UCB2SIMO << 10) | 0x21) 223 #define SPIMSP432DMA_P2_1_UCB2SOMI ((PMAP_UCB2SOMI << 10) | 0x21) 224 #define SPIMSP432DMA_P2_1_UCA1STE ((PMAP_UCA1STE << 10) | 0x21) 225 #define SPIMSP432DMA_P2_1_UCA2STE ((PMAP_UCA2STE << 10) | 0x21) 226 #define SPIMSP432DMA_P2_1_UCB2STE ((PMAP_UCB2STE << 10) | 0x21) 229 #define SPIMSP432DMA_P2_2_UCA0CLK ((PMAP_UCA0CLK << 10) | 0x22) 230 #define SPIMSP432DMA_P2_2_UCA0SIMO ((PMAP_UCA0SIMO << 10) | 0x22) 231 #define SPIMSP432DMA_P2_2_UCA0SOMI ((PMAP_UCA0SOMI << 10) | 0x22) 232 #define SPIMSP432DMA_P2_2_UCA1CLK ((PMAP_UCA1CLK << 10) | 0x22) 233 #define SPIMSP432DMA_P2_2_UCA1SIMO ((PMAP_UCA1SIMO << 10) | 0x22) 234 #define SPIMSP432DMA_P2_2_UCA1SOMI ((PMAP_UCA1SOMI << 10) | 0x22) 235 #define SPIMSP432DMA_P2_2_UCA2CLK ((PMAP_UCA2CLK << 10) | 0x22) 236 #define SPIMSP432DMA_P2_2_UCA2SIMO ((PMAP_UCA2SIMO << 10) | 0x22) 237 #define SPIMSP432DMA_P2_2_UCA2SOMI ((PMAP_UCA2SOMI << 10) | 0x22) 238 #define SPIMSP432DMA_P2_2_UCB0CLK ((PMAP_UCB0CLK << 10) | 0x22) 239 #define SPIMSP432DMA_P2_2_UCB0SIMO ((PMAP_UCB0SIMO << 10) | 0x22) 240 #define SPIMSP432DMA_P2_2_UCB0SOMI ((PMAP_UCB0SOMI << 10) | 0x22) 241 #define SPIMSP432DMA_P2_2_UCB2CLK ((PMAP_UCB2CLK << 10) | 0x22) 242 #define SPIMSP432DMA_P2_2_UCB2SIMO ((PMAP_UCB2SIMO << 10) | 0x22) 243 #define SPIMSP432DMA_P2_2_UCB2SOMI ((PMAP_UCB2SOMI << 10) | 0x22) 244 #define SPIMSP432DMA_P2_2_UCA1STE ((PMAP_UCA1STE << 10) | 0x22) 245 #define SPIMSP432DMA_P2_2_UCA2STE ((PMAP_UCA2STE << 10) | 0x22) 246 #define SPIMSP432DMA_P2_2_UCB2STE ((PMAP_UCB2STE << 10) | 0x22) 249 #define SPIMSP432DMA_P2_3_UCA0CLK ((PMAP_UCA0CLK << 10) | 0x23) 250 #define SPIMSP432DMA_P2_3_UCA0SIMO ((PMAP_UCA0SIMO << 10) | 0x23) 251 #define SPIMSP432DMA_P2_3_UCA0SOMI ((PMAP_UCA0SOMI << 10) | 0x23) 252 #define SPIMSP432DMA_P2_3_UCA1CLK ((PMAP_UCA1CLK << 10) | 0x23) 253 #define SPIMSP432DMA_P2_3_UCA1SIMO ((PMAP_UCA1SIMO << 10) | 0x23) 254 #define SPIMSP432DMA_P2_3_UCA1SOMI ((PMAP_UCA1SOMI << 10) | 0x23) 255 #define SPIMSP432DMA_P2_3_UCA2CLK ((PMAP_UCA2CLK << 10) | 0x23) 256 #define SPIMSP432DMA_P2_3_UCA2SIMO ((PMAP_UCA2SIMO << 10) | 0x23) 257 #define SPIMSP432DMA_P2_3_UCA2SOMI ((PMAP_UCA2SOMI << 10) | 0x23) 258 #define SPIMSP432DMA_P2_3_UCB0CLK ((PMAP_UCB0CLK << 10) | 0x23) 259 #define SPIMSP432DMA_P2_3_UCB0SIMO ((PMAP_UCB0SIMO << 10) | 0x23) 260 #define SPIMSP432DMA_P2_3_UCB0SOMI ((PMAP_UCB0SOMI << 10) | 0x23) 261 #define SPIMSP432DMA_P2_3_UCB2CLK ((PMAP_UCB2CLK << 10) | 0x23) 262 #define SPIMSP432DMA_P2_3_UCB2SIMO ((PMAP_UCB2SIMO << 10) | 0x23) 263 #define SPIMSP432DMA_P2_3_UCB2SOMI ((PMAP_UCB2SOMI << 10) | 0x23) 264 #define SPIMSP432DMA_P2_3_UCA1STE ((PMAP_UCA1STE << 10) | 0x23) 265 #define SPIMSP432DMA_P2_3_UCA2STE ((PMAP_UCA2STE << 10) | 0x23) 266 #define SPIMSP432DMA_P2_3_UCB2STE ((PMAP_UCB2STE << 10) | 0x23) 269 #define SPIMSP432DMA_P2_4_UCA0CLK ((PMAP_UCA0CLK << 10) | 0x24) 270 #define SPIMSP432DMA_P2_4_UCA0SIMO ((PMAP_UCA0SIMO << 10) | 0x24) 271 #define SPIMSP432DMA_P2_4_UCA0SOMI ((PMAP_UCA0SOMI << 10) | 0x24) 272 #define SPIMSP432DMA_P2_4_UCA1CLK ((PMAP_UCA1CLK << 10) | 0x24) 273 #define SPIMSP432DMA_P2_4_UCA1SIMO ((PMAP_UCA1SIMO << 10) | 0x24) 274 #define SPIMSP432DMA_P2_4_UCA1SOMI ((PMAP_UCA1SOMI << 10) | 0x24) 275 #define SPIMSP432DMA_P2_4_UCA2CLK ((PMAP_UCA2CLK << 10) | 0x24) 276 #define SPIMSP432DMA_P2_4_UCA2SIMO ((PMAP_UCA2SIMO << 10) | 0x24) 277 #define SPIMSP432DMA_P2_4_UCA2SOMI ((PMAP_UCA2SOMI << 10) | 0x24) 278 #define SPIMSP432DMA_P2_4_UCB0CLK ((PMAP_UCB0CLK << 10) | 0x24) 279 #define SPIMSP432DMA_P2_4_UCB0SIMO ((PMAP_UCB0SIMO << 10) | 0x24) 280 #define SPIMSP432DMA_P2_4_UCB0SOMI ((PMAP_UCB0SOMI << 10) | 0x24) 281 #define SPIMSP432DMA_P2_4_UCB2CLK ((PMAP_UCB2CLK << 10) | 0x24) 282 #define SPIMSP432DMA_P2_4_UCB2SIMO ((PMAP_UCB2SIMO << 10) | 0x24) 283 #define SPIMSP432DMA_P2_4_UCB2SOMI ((PMAP_UCB2SOMI << 10) | 0x24) 284 #define SPIMSP432DMA_P2_4_UCA1STE ((PMAP_UCA1STE << 10) | 0x24) 285 #define SPIMSP432DMA_P2_4_UCA2STE ((PMAP_UCA2STE << 10) | 0x24) 286 #define SPIMSP432DMA_P2_4_UCB2STE ((PMAP_UCB2STE << 10) | 0x24) 289 #define SPIMSP432DMA_P2_5_UCA0CLK ((PMAP_UCA0CLK << 10) | 0x25) 290 #define SPIMSP432DMA_P2_5_UCA0SIMO ((PMAP_UCA0SIMO << 10) | 0x25) 291 #define SPIMSP432DMA_P2_5_UCA0SOMI ((PMAP_UCA0SOMI << 10) | 0x25) 292 #define SPIMSP432DMA_P2_5_UCA1CLK ((PMAP_UCA1CLK << 10) | 0x25) 293 #define SPIMSP432DMA_P2_5_UCA1SIMO ((PMAP_UCA1SIMO << 10) | 0x25) 294 #define SPIMSP432DMA_P2_5_UCA1SOMI ((PMAP_UCA1SOMI << 10) | 0x25) 295 #define SPIMSP432DMA_P2_5_UCA2CLK ((PMAP_UCA2CLK << 10) | 0x25) 296 #define SPIMSP432DMA_P2_5_UCA2SIMO ((PMAP_UCA2SIMO << 10) | 0x25) 297 #define SPIMSP432DMA_P2_5_UCA2SOMI ((PMAP_UCA2SOMI << 10) | 0x25) 298 #define SPIMSP432DMA_P2_5_UCB0CLK ((PMAP_UCB0CLK << 10) | 0x25) 299 #define SPIMSP432DMA_P2_5_UCB0SIMO ((PMAP_UCB0SIMO << 10) | 0x25) 300 #define SPIMSP432DMA_P2_5_UCB0SOMI ((PMAP_UCB0SOMI << 10) | 0x25) 301 #define SPIMSP432DMA_P2_5_UCB2CLK ((PMAP_UCB2CLK << 10) | 0x25) 302 #define SPIMSP432DMA_P2_5_UCB2SIMO ((PMAP_UCB2SIMO << 10) | 0x25) 303 #define SPIMSP432DMA_P2_5_UCB2SOMI ((PMAP_UCB2SOMI << 10) | 0x25) 304 #define SPIMSP432DMA_P2_5_UCA1STE ((PMAP_UCA1STE << 10) | 0x25) 305 #define SPIMSP432DMA_P2_5_UCA2STE ((PMAP_UCA2STE << 10) | 0x25) 306 #define SPIMSP432DMA_P2_5_UCB2STE ((PMAP_UCB2STE << 10) | 0x25) 309 #define SPIMSP432DMA_P2_6_UCA0CLK ((PMAP_UCA0CLK << 10) | 0x26) 310 #define SPIMSP432DMA_P2_6_UCA0SIMO ((PMAP_UCA0SIMO << 10) | 0x26) 311 #define SPIMSP432DMA_P2_6_UCA0SOMI ((PMAP_UCA0SOMI << 10) | 0x26) 312 #define SPIMSP432DMA_P2_6_UCA1CLK ((PMAP_UCA1CLK << 10) | 0x26) 313 #define SPIMSP432DMA_P2_6_UCA1SIMO ((PMAP_UCA1SIMO << 10) | 0x26) 314 #define SPIMSP432DMA_P2_6_UCA1SOMI ((PMAP_UCA1SOMI << 10) | 0x26) 315 #define SPIMSP432DMA_P2_6_UCA2CLK ((PMAP_UCA2CLK << 10) | 0x26) 316 #define SPIMSP432DMA_P2_6_UCA2SIMO ((PMAP_UCA2SIMO << 10) | 0x26) 317 #define SPIMSP432DMA_P2_6_UCA2SOMI ((PMAP_UCA2SOMI << 10) | 0x26) 318 #define SPIMSP432DMA_P2_6_UCB0CLK ((PMAP_UCB0CLK << 10) | 0x26) 319 #define SPIMSP432DMA_P2_6_UCB0SIMO ((PMAP_UCB0SIMO << 10) | 0x26) 320 #define SPIMSP432DMA_P2_6_UCB0SOMI ((PMAP_UCB0SOMI << 10) | 0x26) 321 #define SPIMSP432DMA_P2_6_UCB2CLK ((PMAP_UCB2CLK << 10) | 0x26) 322 #define SPIMSP432DMA_P2_6_UCB2SIMO ((PMAP_UCB2SIMO << 10) | 0x26) 323 #define SPIMSP432DMA_P2_6_UCB2SOMI ((PMAP_UCB2SOMI << 10) | 0x26) 324 #define SPIMSP432DMA_P2_6_UCA1STE ((PMAP_UCA1STE << 10) | 0x26) 325 #define SPIMSP432DMA_P2_6_UCA2STE ((PMAP_UCA2STE << 10) | 0x26) 326 #define SPIMSP432DMA_P2_6_UCB2STE ((PMAP_UCB2STE << 10) | 0x26) 329 #define SPIMSP432DMA_P2_7_UCA0CLK ((PMAP_UCA0CLK << 10) | 0x27) 330 #define SPIMSP432DMA_P2_7_UCA0SIMO ((PMAP_UCA0SIMO << 10) | 0x27) 331 #define SPIMSP432DMA_P2_7_UCA0SOMI ((PMAP_UCA0SOMI << 10) | 0x27) 332 #define SPIMSP432DMA_P2_7_UCA1CLK ((PMAP_UCA1CLK << 10) | 0x27) 333 #define SPIMSP432DMA_P2_7_UCA1SIMO ((PMAP_UCA1SIMO << 10) | 0x27) 334 #define SPIMSP432DMA_P2_7_UCA1SOMI ((PMAP_UCA1SOMI << 10) | 0x27) 335 #define SPIMSP432DMA_P2_7_UCA2CLK ((PMAP_UCA2CLK << 10) | 0x27) 336 #define SPIMSP432DMA_P2_7_UCA2SIMO ((PMAP_UCA2SIMO << 10) | 0x27) 337 #define SPIMSP432DMA_P2_7_UCA2SOMI ((PMAP_UCA2SOMI << 10) | 0x27) 338 #define SPIMSP432DMA_P2_7_UCB0CLK ((PMAP_UCB0CLK << 10) | 0x27) 339 #define SPIMSP432DMA_P2_7_UCB0SIMO ((PMAP_UCB0SIMO << 10) | 0x27) 340 #define SPIMSP432DMA_P2_7_UCB0SOMI ((PMAP_UCB0SOMI << 10) | 0x27) 341 #define SPIMSP432DMA_P2_7_UCB2CLK ((PMAP_UCB2CLK << 10) | 0x27) 342 #define SPIMSP432DMA_P2_7_UCB2SIMO ((PMAP_UCB2SIMO << 10) | 0x27) 343 #define SPIMSP432DMA_P2_7_UCB2SOMI ((PMAP_UCB2SOMI << 10) | 0x27) 344 #define SPIMSP432DMA_P2_7_UCA1STE ((PMAP_UCA1STE << 10) | 0x27) 345 #define SPIMSP432DMA_P2_7_UCA2STE ((PMAP_UCA2STE << 10) | 0x27) 346 #define SPIMSP432DMA_P2_7_UCB2STE ((PMAP_UCB2STE << 10) | 0x27) 349 #define SPIMSP432DMA_P3_0_UCA0CLK ((PMAP_UCA0CLK << 10) | 0x30) 350 #define SPIMSP432DMA_P3_0_UCA0SIMO ((PMAP_UCA0SIMO << 10) | 0x30) 351 #define SPIMSP432DMA_P3_0_UCA0SOMI ((PMAP_UCA0SOMI << 10) | 0x30) 352 #define SPIMSP432DMA_P3_0_UCA1CLK ((PMAP_UCA1CLK << 10) | 0x30) 353 #define SPIMSP432DMA_P3_0_UCA1SIMO ((PMAP_UCA1SIMO << 10) | 0x30) 354 #define SPIMSP432DMA_P3_0_UCA1SOMI ((PMAP_UCA1SOMI << 10) | 0x30) 355 #define SPIMSP432DMA_P3_0_UCA2STE ((PMAP_UCA2STE << 10) | 0x30) 356 #define SPIMSP432DMA_P3_0_UCA2CLK ((PMAP_UCA2CLK << 10) | 0x30) 357 #define SPIMSP432DMA_P3_0_UCA2SIMO ((PMAP_UCA2SIMO << 10) | 0x30) 358 #define SPIMSP432DMA_P3_0_UCA2SOMI ((PMAP_UCA2SOMI << 10) | 0x30) 359 #define SPIMSP432DMA_P3_0_UCB0CLK ((PMAP_UCB0CLK << 10) | 0x30) 360 #define SPIMSP432DMA_P3_0_UCB0SIMO ((PMAP_UCB0SIMO << 10) | 0x30) 361 #define SPIMSP432DMA_P3_0_UCB0SOMI ((PMAP_UCB0SOMI << 10) | 0x30) 362 #define SPIMSP432DMA_P3_0_UCB2CLK ((PMAP_UCB2CLK << 10) | 0x30) 363 #define SPIMSP432DMA_P3_0_UCB2SIMO ((PMAP_UCB2SIMO << 10) | 0x30) 364 #define SPIMSP432DMA_P3_0_UCB2SOMI ((PMAP_UCB2SOMI << 10) | 0x30) 365 #define SPIMSP432DMA_P3_0_UCA1STE ((PMAP_UCA1STE << 10) | 0x30) 366 #define SPIMSP432DMA_P3_0_UCB2STE ((PMAP_UCB2STE << 10) | 0x30) 369 #define SPIMSP432DMA_P3_1_UCA0CLK ((PMAP_UCA0CLK << 10) | 0x31) 370 #define SPIMSP432DMA_P3_1_UCA0SIMO ((PMAP_UCA0SIMO << 10) | 0x31) 371 #define SPIMSP432DMA_P3_1_UCA0SOMI ((PMAP_UCA0SOMI << 10) | 0x31) 372 #define SPIMSP432DMA_P3_1_UCA1CLK ((PMAP_UCA1CLK << 10) | 0x31) 373 #define SPIMSP432DMA_P3_1_UCA1SIMO ((PMAP_UCA1SIMO << 10) | 0x31) 374 #define SPIMSP432DMA_P3_1_UCA1SOMI ((PMAP_UCA1SOMI << 10) | 0x31) 375 #define SPIMSP432DMA_P3_1_UCA2CLK ((PMAP_UCA2CLK << 10) | 0x31) 376 #define SPIMSP432DMA_P3_1_UCA2SIMO ((PMAP_UCA2SIMO << 10) | 0x31) 377 #define SPIMSP432DMA_P3_1_UCA2SOMI ((PMAP_UCA2SOMI << 10) | 0x31) 378 #define SPIMSP432DMA_P3_1_UCB0CLK ((PMAP_UCB0CLK << 10) | 0x31) 379 #define SPIMSP432DMA_P3_1_UCB0SIMO ((PMAP_UCB0SIMO << 10) | 0x31) 380 #define SPIMSP432DMA_P3_1_UCB0SOMI ((PMAP_UCB0SOMI << 10) | 0x31) 381 #define SPIMSP432DMA_P3_1_UCB2CLK ((PMAP_UCB2CLK << 10) | 0x31) 382 #define SPIMSP432DMA_P3_1_UCB2SIMO ((PMAP_UCB2SIMO << 10) | 0x31) 383 #define SPIMSP432DMA_P3_1_UCB2SOMI ((PMAP_UCB2SOMI << 10) | 0x31) 384 #define SPIMSP432DMA_P3_1_UCA1STE ((PMAP_UCA1STE << 10) | 0x31) 385 #define SPIMSP432DMA_P3_1_UCA2STE ((PMAP_UCA2STE << 10) | 0x31) 386 #define SPIMSP432DMA_P3_1_UCB2STE ((PMAP_UCB2STE << 10) | 0x31) 389 #define SPIMSP432DMA_P3_2_UCA0CLK ((PMAP_UCA0CLK << 10) | 0x32) 390 #define SPIMSP432DMA_P3_2_UCA0SIMO ((PMAP_UCA0SIMO << 10) | 0x32) 391 #define SPIMSP432DMA_P3_2_UCA0SOMI ((PMAP_UCA0SOMI << 10) | 0x32) 392 #define SPIMSP432DMA_P3_2_UCA1CLK ((PMAP_UCA1CLK << 10) | 0x32) 393 #define SPIMSP432DMA_P3_2_UCA1SIMO ((PMAP_UCA1SIMO << 10) | 0x32) 394 #define SPIMSP432DMA_P3_2_UCA1SOMI ((PMAP_UCA1SOMI << 10) | 0x32) 395 #define SPIMSP432DMA_P3_2_UCA2CLK ((PMAP_UCA2CLK << 10) | 0x32) 396 #define SPIMSP432DMA_P3_2_UCA2SIMO ((PMAP_UCA2SIMO << 10) | 0x32) 397 #define SPIMSP432DMA_P3_2_UCA2SOMI ((PMAP_UCA2SOMI << 10) | 0x32) 398 #define SPIMSP432DMA_P3_2_UCB0CLK ((PMAP_UCB0CLK << 10) | 0x32) 399 #define SPIMSP432DMA_P3_2_UCB0SIMO ((PMAP_UCB0SIMO << 10) | 0x32) 400 #define SPIMSP432DMA_P3_2_UCB0SOMI ((PMAP_UCB0SOMI << 10) | 0x32) 401 #define SPIMSP432DMA_P3_2_UCB2CLK ((PMAP_UCB2CLK << 10) | 0x32) 402 #define SPIMSP432DMA_P3_2_UCB2SIMO ((PMAP_UCB2SIMO << 10) | 0x32) 403 #define SPIMSP432DMA_P3_2_UCB2SOMI ((PMAP_UCB2SOMI << 10) | 0x32) 404 #define SPIMSP432DMA_P3_2_UCA1STE ((PMAP_UCA1STE << 10) | 0x32) 405 #define SPIMSP432DMA_P3_2_UCA2STE ((PMAP_UCA2STE << 10) | 0x32) 406 #define SPIMSP432DMA_P3_2_UCB2STE ((PMAP_UCB2STE << 10) | 0x32) 409 #define SPIMSP432DMA_P3_3_UCA0CLK ((PMAP_UCA0CLK << 10) | 0x33) 410 #define SPIMSP432DMA_P3_3_UCA0SIMO ((PMAP_UCA0SIMO << 10) | 0x33) 411 #define SPIMSP432DMA_P3_3_UCA0SOMI ((PMAP_UCA0SOMI << 10) | 0x33) 412 #define SPIMSP432DMA_P3_3_UCA1CLK ((PMAP_UCA1CLK << 10) | 0x33) 413 #define SPIMSP432DMA_P3_3_UCA1SIMO ((PMAP_UCA1SIMO << 10) | 0x33) 414 #define SPIMSP432DMA_P3_3_UCA1SOMI ((PMAP_UCA1SOMI << 10) | 0x33) 415 #define SPIMSP432DMA_P3_3_UCA2CLK ((PMAP_UCA2CLK << 10) | 0x33) 416 #define SPIMSP432DMA_P3_3_UCA2SIMO ((PMAP_UCA2SIMO << 10) | 0x33) 417 #define SPIMSP432DMA_P3_3_UCA2SOMI ((PMAP_UCA2SOMI << 10) | 0x33) 418 #define SPIMSP432DMA_P3_3_UCB0CLK ((PMAP_UCB0CLK << 10) | 0x33) 419 #define SPIMSP432DMA_P3_3_UCB0SIMO ((PMAP_UCB0SIMO << 10) | 0x33) 420 #define SPIMSP432DMA_P3_3_UCB0SOMI ((PMAP_UCB0SOMI << 10) | 0x33) 421 #define SPIMSP432DMA_P3_3_UCB2CLK ((PMAP_UCB2CLK << 10) | 0x33) 422 #define SPIMSP432DMA_P3_3_UCB2SIMO ((PMAP_UCB2SIMO << 10) | 0x33) 423 #define SPIMSP432DMA_P3_3_UCB2SOMI ((PMAP_UCB2SOMI << 10) | 0x33) 424 #define SPIMSP432DMA_P3_3_UCA1STE ((PMAP_UCA1STE << 10) | 0x33) 425 #define SPIMSP432DMA_P3_3_UCA2STE ((PMAP_UCA2STE << 10) | 0x33) 426 #define SPIMSP432DMA_P3_3_UCB2STE ((PMAP_UCB2STE << 10) | 0x33) 429 #define SPIMSP432DMA_P3_4_UCA0CLK ((PMAP_UCA0CLK << 10) | 0x34) 430 #define SPIMSP432DMA_P3_4_UCA0SIMO ((PMAP_UCA0SIMO << 10) | 0x34) 431 #define SPIMSP432DMA_P3_4_UCA0SOMI ((PMAP_UCA0SOMI << 10) | 0x34) 432 #define SPIMSP432DMA_P3_4_UCA1CLK ((PMAP_UCA1CLK << 10) | 0x34) 433 #define SPIMSP432DMA_P3_4_UCA1SIMO ((PMAP_UCA1SIMO << 10) | 0x34) 434 #define SPIMSP432DMA_P3_4_UCA1SOMI ((PMAP_UCA1SOMI << 10) | 0x34) 435 #define SPIMSP432DMA_P3_4_UCA2CLK ((PMAP_UCA2CLK << 10) | 0x34) 436 #define SPIMSP432DMA_P3_4_UCA2SIMO ((PMAP_UCA2SIMO << 10) | 0x34) 437 #define SPIMSP432DMA_P3_4_UCA2SOMI ((PMAP_UCA2SOMI << 10) | 0x34) 438 #define SPIMSP432DMA_P3_4_UCB0CLK ((PMAP_UCB0CLK << 10) | 0x34) 439 #define SPIMSP432DMA_P3_4_UCB0SIMO ((PMAP_UCB0SIMO << 10) | 0x34) 440 #define SPIMSP432DMA_P3_4_UCB0SOMI ((PMAP_UCB0SOMI << 10) | 0x34) 441 #define SPIMSP432DMA_P3_4_UCB2STE ((PMAP_UCB2STE << 10) | 0x34) 442 #define SPIMSP432DMA_P3_4_UCB2CLK ((PMAP_UCB2CLK << 10) | 0x34) 443 #define SPIMSP432DMA_P3_4_UCB2SIMO ((PMAP_UCB2SIMO << 10) | 0x34) 444 #define SPIMSP432DMA_P3_4_UCB2SOMI ((PMAP_UCB2SOMI << 10) | 0x34) 445 #define SPIMSP432DMA_P3_4_UCA1STE ((PMAP_UCA1STE << 10) | 0x34) 446 #define SPIMSP432DMA_P3_4_UCA2STE ((PMAP_UCA2STE << 10) | 0x34) 449 #define SPIMSP432DMA_P3_5_UCA0CLK ((PMAP_UCA0CLK << 10) | 0x35) 450 #define SPIMSP432DMA_P3_5_UCA0SIMO ((PMAP_UCA0SIMO << 10) | 0x35) 451 #define SPIMSP432DMA_P3_5_UCA0SOMI ((PMAP_UCA0SOMI << 10) | 0x35) 452 #define SPIMSP432DMA_P3_5_UCA1CLK ((PMAP_UCA1CLK << 10) | 0x35) 453 #define SPIMSP432DMA_P3_5_UCA1SIMO ((PMAP_UCA1SIMO << 10) | 0x35) 454 #define SPIMSP432DMA_P3_5_UCA1SOMI ((PMAP_UCA1SOMI << 10) | 0x35) 455 #define SPIMSP432DMA_P3_5_UCA2CLK ((PMAP_UCA2CLK << 10) | 0x35) 456 #define SPIMSP432DMA_P3_5_UCA2SIMO ((PMAP_UCA2SIMO << 10) | 0x35) 457 #define SPIMSP432DMA_P3_5_UCA2SOMI ((PMAP_UCA2SOMI << 10) | 0x35) 458 #define SPIMSP432DMA_P3_5_UCB0CLK ((PMAP_UCB0CLK << 10) | 0x35) 459 #define SPIMSP432DMA_P3_5_UCB0SIMO ((PMAP_UCB0SIMO << 10) | 0x35) 460 #define SPIMSP432DMA_P3_5_UCB0SOMI ((PMAP_UCB0SOMI << 10) | 0x35) 461 #define SPIMSP432DMA_P3_5_UCB2CLK ((PMAP_UCB2CLK << 10) | 0x35) 462 #define SPIMSP432DMA_P3_5_UCB2SIMO ((PMAP_UCB2SIMO << 10) | 0x35) 463 #define SPIMSP432DMA_P3_5_UCB2SOMI ((PMAP_UCB2SOMI << 10) | 0x35) 464 #define SPIMSP432DMA_P3_5_UCA1STE ((PMAP_UCA1STE << 10) | 0x35) 465 #define SPIMSP432DMA_P3_5_UCA2STE ((PMAP_UCA2STE << 10) | 0x35) 466 #define SPIMSP432DMA_P3_5_UCB2STE ((PMAP_UCB2STE << 10) | 0x35) 469 #define SPIMSP432DMA_P3_6_UCA0CLK ((PMAP_UCA0CLK << 10) | 0x36) 470 #define SPIMSP432DMA_P3_6_UCA0SIMO ((PMAP_UCA0SIMO << 10) | 0x36) 471 #define SPIMSP432DMA_P3_6_UCA0SOMI ((PMAP_UCA0SOMI << 10) | 0x36) 472 #define SPIMSP432DMA_P3_6_UCA1CLK ((PMAP_UCA1CLK << 10) | 0x36) 473 #define SPIMSP432DMA_P3_6_UCA1SIMO ((PMAP_UCA1SIMO << 10) | 0x36) 474 #define SPIMSP432DMA_P3_6_UCA1SOMI ((PMAP_UCA1SOMI << 10) | 0x36) 475 #define SPIMSP432DMA_P3_6_UCA2CLK ((PMAP_UCA2CLK << 10) | 0x36) 476 #define SPIMSP432DMA_P3_6_UCA2SIMO ((PMAP_UCA2SIMO << 10) | 0x36) 477 #define SPIMSP432DMA_P3_6_UCA2SOMI ((PMAP_UCA2SOMI << 10) | 0x36) 478 #define SPIMSP432DMA_P3_6_UCB0CLK ((PMAP_UCB0CLK << 10) | 0x36) 479 #define SPIMSP432DMA_P3_6_UCB0SIMO ((PMAP_UCB0SIMO << 10) | 0x36) 480 #define SPIMSP432DMA_P3_6_UCB0SOMI ((PMAP_UCB0SOMI << 10) | 0x36) 481 #define SPIMSP432DMA_P3_6_UCB2CLK ((PMAP_UCB2CLK << 10) | 0x36) 482 #define SPIMSP432DMA_P3_6_UCB2SIMO ((PMAP_UCB2SIMO << 10) | 0x36) 483 #define SPIMSP432DMA_P3_6_UCB2SOMI ((PMAP_UCB2SOMI << 10) | 0x36) 484 #define SPIMSP432DMA_P3_6_UCA1STE ((PMAP_UCA1STE << 10) | 0x36) 485 #define SPIMSP432DMA_P3_6_UCA2STE ((PMAP_UCA2STE << 10) | 0x36) 486 #define SPIMSP432DMA_P3_6_UCB2STE ((PMAP_UCB2STE << 10) | 0x36) 489 #define SPIMSP432DMA_P3_7_UCA0CLK ((PMAP_UCA0CLK << 10) | 0x37) 490 #define SPIMSP432DMA_P3_7_UCA0SIMO ((PMAP_UCA0SIMO << 10) | 0x37) 491 #define SPIMSP432DMA_P3_7_UCA0SOMI ((PMAP_UCA0SOMI << 10) | 0x37) 492 #define SPIMSP432DMA_P3_7_UCA1CLK ((PMAP_UCA1CLK << 10) | 0x37) 493 #define SPIMSP432DMA_P3_7_UCA1SIMO ((PMAP_UCA1SIMO << 10) | 0x37) 494 #define SPIMSP432DMA_P3_7_UCA1SOMI ((PMAP_UCA1SOMI << 10) | 0x37) 495 #define SPIMSP432DMA_P3_7_UCA2CLK ((PMAP_UCA2CLK << 10) | 0x37) 496 #define SPIMSP432DMA_P3_7_UCA2SIMO ((PMAP_UCA2SIMO << 10) | 0x37) 497 #define SPIMSP432DMA_P3_7_UCA2SOMI ((PMAP_UCA2SOMI << 10) | 0x37) 498 #define SPIMSP432DMA_P3_7_UCB0CLK ((PMAP_UCB0CLK << 10) | 0x37) 499 #define SPIMSP432DMA_P3_7_UCB0SIMO ((PMAP_UCB0SIMO << 10) | 0x37) 500 #define SPIMSP432DMA_P3_7_UCB0SOMI ((PMAP_UCB0SOMI << 10) | 0x37) 501 #define SPIMSP432DMA_P3_7_UCB2CLK ((PMAP_UCB2CLK << 10) | 0x37) 502 #define SPIMSP432DMA_P3_7_UCB2SIMO ((PMAP_UCB2SIMO << 10) | 0x37) 503 #define SPIMSP432DMA_P3_7_UCB2SOMI ((PMAP_UCB2SOMI << 10) | 0x37) 504 #define SPIMSP432DMA_P3_7_UCA1STE ((PMAP_UCA1STE << 10) | 0x37) 505 #define SPIMSP432DMA_P3_7_UCA2STE ((PMAP_UCA2STE << 10) | 0x37) 506 #define SPIMSP432DMA_P3_7_UCB2STE ((PMAP_UCB2STE << 10) | 0x37) 509 #define SPIMSP432DMA_P6_2_UCB1STE 0x00000162 510 #define SPIMSP432DMA_P6_3_UCB1CLK 0x00000163 511 #define SPIMSP432DMA_P6_4_UCB1SIMO 0x00000164 512 #define SPIMSP432DMA_P6_5_UCB1SOMI 0x00000165 513 #define SPIMSP432DMA_P6_6_UCB3SIMO 0x00000266 514 #define SPIMSP432DMA_P6_7_UCB3SOMI 0x00000267 517 #define SPIMSP432DMA_P7_0_UCA0CLK ((PMAP_UCA0CLK << 10) | 0x70) 518 #define SPIMSP432DMA_P7_0_UCA0SIMO ((PMAP_UCA0SIMO << 10) | 0x70) 519 #define SPIMSP432DMA_P7_0_UCA0SOMI ((PMAP_UCA0SOMI << 10) | 0x70) 520 #define SPIMSP432DMA_P7_0_UCA1CLK ((PMAP_UCA1CLK << 10) | 0x70) 521 #define SPIMSP432DMA_P7_0_UCA1SIMO ((PMAP_UCA1SIMO << 10) | 0x70) 522 #define SPIMSP432DMA_P7_0_UCA1SOMI ((PMAP_UCA1SOMI << 10) | 0x70) 523 #define SPIMSP432DMA_P7_0_UCA2CLK ((PMAP_UCA2CLK << 10) | 0x70) 524 #define SPIMSP432DMA_P7_0_UCA2SIMO ((PMAP_UCA2SIMO << 10) | 0x70) 525 #define SPIMSP432DMA_P7_0_UCA2SOMI ((PMAP_UCA2SOMI << 10) | 0x70) 526 #define SPIMSP432DMA_P7_0_UCB0CLK ((PMAP_UCB0CLK << 10) | 0x70) 527 #define SPIMSP432DMA_P7_0_UCB0SIMO ((PMAP_UCB0SIMO << 10) | 0x70) 528 #define SPIMSP432DMA_P7_0_UCB0SOMI ((PMAP_UCB0SOMI << 10) | 0x70) 529 #define SPIMSP432DMA_P7_0_UCB2CLK ((PMAP_UCB2CLK << 10) | 0x70) 530 #define SPIMSP432DMA_P7_0_UCB2SIMO ((PMAP_UCB2SIMO << 10) | 0x70) 531 #define SPIMSP432DMA_P7_0_UCB2SOMI ((PMAP_UCB2SOMI << 10) | 0x70) 532 #define SPIMSP432DMA_P7_0_UCA1STE ((PMAP_UCA1STE << 10) | 0x70) 533 #define SPIMSP432DMA_P7_0_UCA2STE ((PMAP_UCA2STE << 10) | 0x70) 534 #define SPIMSP432DMA_P7_0_UCB2STE ((PMAP_UCB2STE << 10) | 0x70) 537 #define SPIMSP432DMA_P7_1_UCA0CLK ((PMAP_UCA0CLK << 10) | 0x71) 538 #define SPIMSP432DMA_P7_1_UCA0SIMO ((PMAP_UCA0SIMO << 10) | 0x71) 539 #define SPIMSP432DMA_P7_1_UCA0SOMI ((PMAP_UCA0SOMI << 10) | 0x71) 540 #define SPIMSP432DMA_P7_1_UCA1CLK ((PMAP_UCA1CLK << 10) | 0x71) 541 #define SPIMSP432DMA_P7_1_UCA1SIMO ((PMAP_UCA1SIMO << 10) | 0x71) 542 #define SPIMSP432DMA_P7_1_UCA1SOMI ((PMAP_UCA1SOMI << 10) | 0x71) 543 #define SPIMSP432DMA_P7_1_UCA2CLK ((PMAP_UCA2CLK << 10) | 0x71) 544 #define SPIMSP432DMA_P7_1_UCA2SIMO ((PMAP_UCA2SIMO << 10) | 0x71) 545 #define SPIMSP432DMA_P7_1_UCA2SOMI ((PMAP_UCA2SOMI << 10) | 0x71) 546 #define SPIMSP432DMA_P7_1_UCB0CLK ((PMAP_UCB0CLK << 10) | 0x71) 547 #define SPIMSP432DMA_P7_1_UCB0SIMO ((PMAP_UCB0SIMO << 10) | 0x71) 548 #define SPIMSP432DMA_P7_1_UCB0SOMI ((PMAP_UCB0SOMI << 10) | 0x71) 549 #define SPIMSP432DMA_P7_1_UCB2CLK ((PMAP_UCB2CLK << 10) | 0x71) 550 #define SPIMSP432DMA_P7_1_UCB2SIMO ((PMAP_UCB2SIMO << 10) | 0x71) 551 #define SPIMSP432DMA_P7_1_UCB2SOMI ((PMAP_UCB2SOMI << 10) | 0x71) 552 #define SPIMSP432DMA_P7_1_UCA1STE ((PMAP_UCA1STE << 10) | 0x71) 553 #define SPIMSP432DMA_P7_1_UCA2STE ((PMAP_UCA2STE << 10) | 0x71) 554 #define SPIMSP432DMA_P7_1_UCB2STE ((PMAP_UCB2STE << 10) | 0x71) 557 #define SPIMSP432DMA_P7_2_UCA0CLK ((PMAP_UCA0CLK << 10) | 0x72) 558 #define SPIMSP432DMA_P7_2_UCA0SIMO ((PMAP_UCA0SIMO << 10) | 0x72) 559 #define SPIMSP432DMA_P7_2_UCA0SOMI ((PMAP_UCA0SOMI << 10) | 0x72) 560 #define SPIMSP432DMA_P7_2_UCA1CLK ((PMAP_UCA1CLK << 10) | 0x72) 561 #define SPIMSP432DMA_P7_2_UCA1SIMO ((PMAP_UCA1SIMO << 10) | 0x72) 562 #define SPIMSP432DMA_P7_2_UCA1SOMI ((PMAP_UCA1SOMI << 10) | 0x72) 563 #define SPIMSP432DMA_P7_2_UCA2CLK ((PMAP_UCA2CLK << 10) | 0x72) 564 #define SPIMSP432DMA_P7_2_UCA2SIMO ((PMAP_UCA2SIMO << 10) | 0x72) 565 #define SPIMSP432DMA_P7_2_UCA2SOMI ((PMAP_UCA2SOMI << 10) | 0x72) 566 #define SPIMSP432DMA_P7_2_UCB0CLK ((PMAP_UCB0CLK << 10) | 0x72) 567 #define SPIMSP432DMA_P7_2_UCB0SIMO ((PMAP_UCB0SIMO << 10) | 0x72) 568 #define SPIMSP432DMA_P7_2_UCB0SOMI ((PMAP_UCB0SOMI << 10) | 0x72) 569 #define SPIMSP432DMA_P7_2_UCB2CLK ((PMAP_UCB2CLK << 10) | 0x72) 570 #define SPIMSP432DMA_P7_2_UCB2SIMO ((PMAP_UCB2SIMO << 10) | 0x72) 571 #define SPIMSP432DMA_P7_2_UCB2SOMI ((PMAP_UCB2SOMI << 10) | 0x72) 572 #define SPIMSP432DMA_P7_2_UCA1STE ((PMAP_UCA1STE << 10) | 0x72) 573 #define SPIMSP432DMA_P7_2_UCA2STE ((PMAP_UCA2STE << 10) | 0x72) 574 #define SPIMSP432DMA_P7_2_UCB2STE ((PMAP_UCB2STE << 10) | 0x72) 577 #define SPIMSP432DMA_P7_3_UCA0CLK ((PMAP_UCA0CLK << 10) | 0x73) 578 #define SPIMSP432DMA_P7_3_UCA0SIMO ((PMAP_UCA0SIMO << 10) | 0x73) 579 #define SPIMSP432DMA_P7_3_UCA0SOMI ((PMAP_UCA0SOMI << 10) | 0x73) 580 #define SPIMSP432DMA_P7_3_UCA1CLK ((PMAP_UCA1CLK << 10) | 0x73) 581 #define SPIMSP432DMA_P7_3_UCA1SIMO ((PMAP_UCA1SIMO << 10) | 0x73) 582 #define SPIMSP432DMA_P7_3_UCA1SOMI ((PMAP_UCA1SOMI << 10) | 0x73) 583 #define SPIMSP432DMA_P7_3_UCA2CLK ((PMAP_UCA2CLK << 10) | 0x73) 584 #define SPIMSP432DMA_P7_3_UCA2SIMO ((PMAP_UCA2SIMO << 10) | 0x73) 585 #define SPIMSP432DMA_P7_3_UCA2SOMI ((PMAP_UCA2SOMI << 10) | 0x73) 586 #define SPIMSP432DMA_P7_3_UCB0CLK ((PMAP_UCB0CLK << 10) | 0x73) 587 #define SPIMSP432DMA_P7_3_UCB0SIMO ((PMAP_UCB0SIMO << 10) | 0x73) 588 #define SPIMSP432DMA_P7_3_UCB0SOMI ((PMAP_UCB0SOMI << 10) | 0x73) 589 #define SPIMSP432DMA_P7_3_UCB2CLK ((PMAP_UCB2CLK << 10) | 0x73) 590 #define SPIMSP432DMA_P7_3_UCB2SIMO ((PMAP_UCB2SIMO << 10) | 0x73) 591 #define SPIMSP432DMA_P7_3_UCB2SOMI ((PMAP_UCB2SOMI << 10) | 0x73) 592 #define SPIMSP432DMA_P7_3_UCA1STE ((PMAP_UCA1STE << 10) | 0x73) 593 #define SPIMSP432DMA_P7_3_UCA2STE ((PMAP_UCA2STE << 10) | 0x73) 594 #define SPIMSP432DMA_P7_3_UCB2STE ((PMAP_UCB2STE << 10) | 0x73) 597 #define SPIMSP432DMA_P7_4_UCA0CLK ((PMAP_UCA0CLK << 10) | 0x74) 598 #define SPIMSP432DMA_P7_4_UCA0SIMO ((PMAP_UCA0SIMO << 10) | 0x74) 599 #define SPIMSP432DMA_P7_4_UCA0SOMI ((PMAP_UCA0SOMI << 10) | 0x74) 600 #define SPIMSP432DMA_P7_4_UCA1CLK ((PMAP_UCA1CLK << 10) | 0x74) 601 #define SPIMSP432DMA_P7_4_UCA1SIMO ((PMAP_UCA1SIMO << 10) | 0x74) 602 #define SPIMSP432DMA_P7_4_UCA1SOMI ((PMAP_UCA1SOMI << 10) | 0x74) 603 #define SPIMSP432DMA_P7_4_UCA2CLK ((PMAP_UCA2CLK << 10) | 0x74) 604 #define SPIMSP432DMA_P7_4_UCA2SIMO ((PMAP_UCA2SIMO << 10) | 0x74) 605 #define SPIMSP432DMA_P7_4_UCA2SOMI ((PMAP_UCA2SOMI << 10) | 0x74) 606 #define SPIMSP432DMA_P7_4_UCB0CLK ((PMAP_UCB0CLK << 10) | 0x74) 607 #define SPIMSP432DMA_P7_4_UCB0SIMO ((PMAP_UCB0SIMO << 10) | 0x74) 608 #define SPIMSP432DMA_P7_4_UCB0SOMI ((PMAP_UCB0SOMI << 10) | 0x74) 609 #define SPIMSP432DMA_P7_4_UCB2CLK ((PMAP_UCB2CLK << 10) | 0x74) 610 #define SPIMSP432DMA_P7_4_UCB2SIMO ((PMAP_UCB2SIMO << 10) | 0x74) 611 #define SPIMSP432DMA_P7_4_UCB2SOMI ((PMAP_UCB2SOMI << 10) | 0x74) 612 #define SPIMSP432DMA_P7_4_UCA1STE ((PMAP_UCA1STE << 10) | 0x74) 613 #define SPIMSP432DMA_P7_4_UCA2STE ((PMAP_UCA2STE << 10) | 0x74) 614 #define SPIMSP432DMA_P7_4_UCB2STE ((PMAP_UCB2STE << 10) | 0x74) 617 #define SPIMSP432DMA_P7_5_UCA0CLK ((PMAP_UCA0CLK << 10) | 0x75) 618 #define SPIMSP432DMA_P7_5_UCA0SIMO ((PMAP_UCA0SIMO << 10) | 0x75) 619 #define SPIMSP432DMA_P7_5_UCA0SOMI ((PMAP_UCA0SOMI << 10) | 0x75) 620 #define SPIMSP432DMA_P7_5_UCA1CLK ((PMAP_UCA1CLK << 10) | 0x75) 621 #define SPIMSP432DMA_P7_5_UCA1SIMO ((PMAP_UCA1SIMO << 10) | 0x75) 622 #define SPIMSP432DMA_P7_5_UCA1SOMI ((PMAP_UCA1SOMI << 10) | 0x75) 623 #define SPIMSP432DMA_P7_5_UCA2CLK ((PMAP_UCA2CLK << 10) | 0x75) 624 #define SPIMSP432DMA_P7_5_UCA2SIMO ((PMAP_UCA2SIMO << 10) | 0x75) 625 #define SPIMSP432DMA_P7_5_UCA2SOMI ((PMAP_UCA2SOMI << 10) | 0x75) 626 #define SPIMSP432DMA_P7_5_UCB0CLK ((PMAP_UCB0CLK << 10) | 0x75) 627 #define SPIMSP432DMA_P7_5_UCB0SIMO ((PMAP_UCB0SIMO << 10) | 0x75) 628 #define SPIMSP432DMA_P7_5_UCB0SOMI ((PMAP_UCB0SOMI << 10) | 0x75) 629 #define SPIMSP432DMA_P7_5_UCB2CLK ((PMAP_UCB2CLK << 10) | 0x75) 630 #define SPIMSP432DMA_P7_5_UCB2SIMO ((PMAP_UCB2SIMO << 10) | 0x75) 631 #define SPIMSP432DMA_P7_5_UCB2SOMI ((PMAP_UCB2SOMI << 10) | 0x75) 632 #define SPIMSP432DMA_P7_5_UCA1STE ((PMAP_UCA1STE << 10) | 0x75) 633 #define SPIMSP432DMA_P7_5_UCA2STE ((PMAP_UCA2STE << 10) | 0x75) 634 #define SPIMSP432DMA_P7_5_UCB2STE ((PMAP_UCB2STE << 10) | 0x75) 637 #define SPIMSP432DMA_P7_6_UCA0CLK ((PMAP_UCA0CLK << 10) | 0x76) 638 #define SPIMSP432DMA_P7_6_UCA0SIMO ((PMAP_UCA0SIMO << 10) | 0x76) 639 #define SPIMSP432DMA_P7_6_UCA0SOMI ((PMAP_UCA0SOMI << 10) | 0x76) 640 #define SPIMSP432DMA_P7_6_UCA1CLK ((PMAP_UCA1CLK << 10) | 0x76) 641 #define SPIMSP432DMA_P7_6_UCA1SIMO ((PMAP_UCA1SIMO << 10) | 0x76) 642 #define SPIMSP432DMA_P7_6_UCA1SOMI ((PMAP_UCA1SOMI << 10) | 0x76) 643 #define SPIMSP432DMA_P7_6_UCA2CLK ((PMAP_UCA2CLK << 10) | 0x76) 644 #define SPIMSP432DMA_P7_6_UCA2SIMO ((PMAP_UCA2SIMO << 10) | 0x76) 645 #define SPIMSP432DMA_P7_6_UCA2SOMI ((PMAP_UCA2SOMI << 10) | 0x76) 646 #define SPIMSP432DMA_P7_6_UCB0CLK ((PMAP_UCB0CLK << 10) | 0x76) 647 #define SPIMSP432DMA_P7_6_UCB0SIMO ((PMAP_UCB0SIMO << 10) | 0x76) 648 #define SPIMSP432DMA_P7_6_UCB0SOMI ((PMAP_UCB0SOMI << 10) | 0x76) 649 #define SPIMSP432DMA_P7_6_UCB2CLK ((PMAP_UCB2CLK << 10) | 0x76) 650 #define SPIMSP432DMA_P7_6_UCB2SIMO ((PMAP_UCB2SIMO << 10) | 0x76) 651 #define SPIMSP432DMA_P7_6_UCB2SOMI ((PMAP_UCB2SOMI << 10) | 0x76) 652 #define SPIMSP432DMA_P7_6_UCA1STE ((PMAP_UCA1STE << 10) | 0x76) 653 #define SPIMSP432DMA_P7_6_UCA2STE ((PMAP_UCA2STE << 10) | 0x76) 654 #define SPIMSP432DMA_P7_6_UCB2STE ((PMAP_UCB2STE << 10) | 0x76) 657 #define SPIMSP432DMA_P7_7_UCA0CLK ((PMAP_UCA0CLK << 10) | 0x77) 658 #define SPIMSP432DMA_P7_7_UCA0SIMO ((PMAP_UCA0SIMO << 10) | 0x77) 659 #define SPIMSP432DMA_P7_7_UCA0SOMI ((PMAP_UCA0SOMI << 10) | 0x77) 660 #define SPIMSP432DMA_P7_7_UCA1CLK ((PMAP_UCA1CLK << 10) | 0x77) 661 #define SPIMSP432DMA_P7_7_UCA1SIMO ((PMAP_UCA1SIMO << 10) | 0x77) 662 #define SPIMSP432DMA_P7_7_UCA1SOMI ((PMAP_UCA1SOMI << 10) | 0x77) 663 #define SPIMSP432DMA_P7_7_UCA2CLK ((PMAP_UCA2CLK << 10) | 0x77) 664 #define SPIMSP432DMA_P7_7_UCA2SIMO ((PMAP_UCA2SIMO << 10) | 0x77) 665 #define SPIMSP432DMA_P7_7_UCA2SOMI ((PMAP_UCA2SOMI << 10) | 0x77) 666 #define SPIMSP432DMA_P7_7_UCB0CLK ((PMAP_UCB0CLK << 10) | 0x77) 667 #define SPIMSP432DMA_P7_7_UCB0SIMO ((PMAP_UCB0SIMO << 10) | 0x77) 668 #define SPIMSP432DMA_P7_7_UCB0SOMI ((PMAP_UCB0SOMI << 10) | 0x77) 669 #define SPIMSP432DMA_P7_7_UCB2CLK ((PMAP_UCB2CLK << 10) | 0x77) 670 #define SPIMSP432DMA_P7_7_UCB2SIMO ((PMAP_UCB2SIMO << 10) | 0x77) 671 #define SPIMSP432DMA_P7_7_UCB2SOMI ((PMAP_UCB2SOMI << 10) | 0x77) 672 #define SPIMSP432DMA_P7_7_UCA1STE ((PMAP_UCA1STE << 10) | 0x77) 673 #define SPIMSP432DMA_P7_7_UCA2STE ((PMAP_UCA2STE << 10) | 0x77) 674 #define SPIMSP432DMA_P7_7_UCB2STE ((PMAP_UCB2STE << 10) | 0x77) 677 #define SPIMSP432DMA_P8_0_UCB3STE 0x00000180 678 #define SPIMSP432DMA_P8_1_UCB3CLK 0x00000181 681 #define SPIMSP432DMA_P9_4_UCA3STE 0x00000194 682 #define SPIMSP432DMA_P9_5_UCA3CLK 0x00000195 683 #define SPIMSP432DMA_P9_6_UCA3SOMI 0x00000196 684 #define SPIMSP432DMA_P9_7_UCA3SIMO 0x00000197 687 #define SPIMSP432DMA_P10_0_UCB3STE 0x000001A0 688 #define SPIMSP432DMA_P10_1_UCB3CLK 0x000001A1 689 #define SPIMSP432DMA_P10_2_UCB3SIMO 0x000001A2 690 #define SPIMSP432DMA_P10_3_UCB3SOMI 0x000001A3 SPI_TransferMode transferMode
Definition: SPIMSP432DMA.h:819
void(* SPI_CallbackFxn)(SPI_Handle handle, SPI_Transaction *transaction)
The definition of a callback function used by the SPI driver when used in SPI_MODE_CALLBACK.
Definition: SPI.h:540
uint16_t clockPhase
Definition: SPIMSP432DMA.h:826
enum SPI_Mode_ SPI_Mode
Definitions for various SPI modes of operation.
SPIMSP432DMA Hardware attributes These fields, with the exception of intPriority, are used by driverl...
Definition: SPIMSP432DMA.h:786
SPI_Mode spiMode
Definition: SPIMSP432DMA.h:820
A SPI_Transaction data structure is used with SPI_transfer(). It indicates how many SPI_FrameFormat f...
Definition: SPI.h:522
struct SPIMSP432DMA_HWAttrsV1 SPIMSP432DMA_HWAttrsV1
SPIMSP432DMA Hardware attributes These fields, with the exception of intPriority, are used by driverl...
uint16_t pinMode
Definition: SPIMSP432DMA.h:803
uint16_t bitOrder
Definition: SPIMSP432DMA.h:788
uint32_t baseAddr
Definition: SPIMSP432DMA.h:787
UDMAMSP432_Handle dmaHandle
Definition: SPIMSP432DMA.h:831
Power notify object structure.
Definition: Power.h:113
HwiP_Handle hwiHandle
Definition: SPIMSP432DMA.h:814
uint32_t txDMAChannelIndex
Definition: SPIMSP432DMA.h:796
SPIMSP432DMA Object.
Definition: SPIMSP432DMA.h:812
uint8_t defaultTxBufValue
Definition: SPIMSP432DMA.h:791
enum SPI_TransferMode_ SPI_TransferMode
SPI transfer mode determines the whether the SPI controller operates synchronously or asynchronously...
The definition of a SPI function table that contains the required set of functions to control a speci...
Definition: SPI.h:652
SPI_Transaction * transaction
Definition: SPIMSP432DMA.h:817
uint16_t stePin
Definition: SPIMSP432DMA.h:801
struct SPIMSP432DMA_Object SPIMSP432DMA_Object
SPIMSP432DMA Object.
uDMA driver implementation for MSP432.
uint8_t dmaIntNum
Definition: SPIMSP432DMA.h:793
uint16_t somiPin
Definition: SPIMSP432DMA.h:799
uint8_t scratchBuffer
Definition: SPIMSP432DMA.h:821
uint16_t clockPolarity
Definition: SPIMSP432DMA.h:827
UDMAMSP432 Global configuration.
Definition: UDMAMSP432.h:135
Power_NotifyObj perfChangeNotify
Definition: SPIMSP432DMA.h:829
uint32_t perfConstraintMask
Definition: SPIMSP432DMA.h:830
uint32_t bitRate
Definition: SPIMSP432DMA.h:825
const SPI_FxnTable SPIMSP432DMA_fxnTable
SPI_CallbackFxn transferCallbackFxn
Definition: SPIMSP432DMA.h:816
SemaphoreP_Handle transferComplete
Definition: SPIMSP432DMA.h:813
uint8_t clockSource
Definition: SPIMSP432DMA.h:789
bool isOpen
Definition: SPIMSP432DMA.h:823
struct SPIMSP432DMA_Object * SPIMSP432DMA_Handle
uint32_t intPriority
Definition: SPIMSP432DMA.h:794
uint16_t clkPin
Definition: SPIMSP432DMA.h:800
uint32_t rxDMAChannelIndex
Definition: SPIMSP432DMA.h:795
uint16_t simoPin
Definition: SPIMSP432DMA.h:798