50 #ifndef ti_drivers_i2c_I2CMSP432__include 51 #define ti_drivers_i2c_I2CMSP432__include 61 #include <ti/drivers/dpl/HwiP.h> 62 #include <ti/drivers/dpl/SemaphoreP.h> 113 #define I2CMSP432_P1_6_UCB0SDA 0x00000116 115 #define I2CMSP432_P1_7_UCB0SCL 0x00000117 118 #define I2CMSP432_P2_0_UCB0SDA ((PMAP_UCB0SDA << 10) | 0x20) 120 #define I2CMSP432_P2_0_UCB0SCL ((PMAP_UCB0SCL << 10) | 0x20) 122 #define I2CMSP432_P2_0_UCB2SDA ((PMAP_UCB2SDA << 10) | 0x20) 124 #define I2CMSP432_P2_0_UCB2SCL ((PMAP_UCB2SCL << 10) | 0x20) 127 #define I2CMSP432_P2_1_UCB0SDA ((PMAP_UCB0SDA << 10) | 0x21) 129 #define I2CMSP432_P2_1_UCB0SCL ((PMAP_UCB0SCL << 10) | 0x21) 131 #define I2CMSP432_P2_1_UCB2SDA ((PMAP_UCB2SDA << 10) | 0x21) 133 #define I2CMSP432_P2_1_UCB2SCL ((PMAP_UCB2SCL << 10) | 0x21) 136 #define I2CMSP432_P2_2_UCB0SDA ((PMAP_UCB0SDA << 10) | 0x22) 138 #define I2CMSP432_P2_2_UCB0SCL ((PMAP_UCB0SCL << 10) | 0x22) 140 #define I2CMSP432_P2_2_UCB2SDA ((PMAP_UCB2SDA << 10) | 0x22) 142 #define I2CMSP432_P2_2_UCB2SCL ((PMAP_UCB2SCL << 10) | 0x22) 145 #define I2CMSP432_P2_3_UCB0SDA ((PMAP_UCB0SDA << 10) | 0x23) 147 #define I2CMSP432_P2_3_UCB0SCL ((PMAP_UCB0SCL << 10) | 0x23) 149 #define I2CMSP432_P2_3_UCB2SDA ((PMAP_UCB2SDA << 10) | 0x23) 151 #define I2CMSP432_P2_3_UCB2SCL ((PMAP_UCB2SCL << 10) | 0x23) 154 #define I2CMSP432_P2_4_UCB0SDA ((PMAP_UCB0SDA << 10) | 0x24) 156 #define I2CMSP432_P2_4_UCB0SCL ((PMAP_UCB0SCL << 10) | 0x24) 158 #define I2CMSP432_P2_4_UCB2SDA ((PMAP_UCB2SDA << 10) | 0x24) 160 #define I2CMSP432_P2_4_UCB2SCL ((PMAP_UCB2SCL << 10) | 0x24) 163 #define I2CMSP432_P2_5_UCB0SDA ((PMAP_UCB0SDA << 10) | 0x25) 165 #define I2CMSP432_P2_5_UCB0SCL ((PMAP_UCB0SCL << 10) | 0x25) 167 #define I2CMSP432_P2_5_UCB2SDA ((PMAP_UCB2SDA << 10) | 0x25) 169 #define I2CMSP432_P2_5_UCB2SCL ((PMAP_UCB2SCL << 10) | 0x25) 172 #define I2CMSP432_P2_6_UCB0SDA ((PMAP_UCB0SDA << 10) | 0x26) 174 #define I2CMSP432_P2_6_UCB0SCL ((PMAP_UCB0SCL << 10) | 0x26) 176 #define I2CMSP432_P2_6_UCB2SDA ((PMAP_UCB2SDA << 10) | 0x26) 178 #define I2CMSP432_P2_6_UCB2SCL ((PMAP_UCB2SCL << 10) | 0x26) 181 #define I2CMSP432_P2_7_UCB0SDA ((PMAP_UCB0SDA << 10) | 0x27) 183 #define I2CMSP432_P2_7_UCB0SCL ((PMAP_UCB0SCL << 10) | 0x27) 185 #define I2CMSP432_P2_7_UCB2SDA ((PMAP_UCB2SDA << 10) | 0x27) 187 #define I2CMSP432_P2_7_UCB2SCL ((PMAP_UCB2SCL << 10) | 0x27) 190 #define I2CMSP432_P3_0_UCB0SDA ((PMAP_UCB0SDA << 10) | 0x30) 192 #define I2CMSP432_P3_0_UCB0SCL ((PMAP_UCB0SCL << 10) | 0x30) 194 #define I2CMSP432_P3_0_UCB2SDA ((PMAP_UCB2SDA << 10) | 0x30) 196 #define I2CMSP432_P3_0_UCB2SCL ((PMAP_UCB2SCL << 10) | 0x30) 199 #define I2CMSP432_P3_1_UCB0SDA ((PMAP_UCB0SDA << 10) | 0x31) 201 #define I2CMSP432_P3_1_UCB0SCL ((PMAP_UCB0SCL << 10) | 0x31) 203 #define I2CMSP432_P3_1_UCB2SDA ((PMAP_UCB2SDA << 10) | 0x31) 205 #define I2CMSP432_P3_1_UCB2SCL ((PMAP_UCB2SCL << 10) | 0x31) 208 #define I2CMSP432_P3_2_UCB0SDA ((PMAP_UCB0SDA << 10) | 0x32) 210 #define I2CMSP432_P3_2_UCB0SCL ((PMAP_UCB0SCL << 10) | 0x32) 212 #define I2CMSP432_P3_2_UCB2SDA ((PMAP_UCB2SDA << 10) | 0x32) 214 #define I2CMSP432_P3_2_UCB2SCL ((PMAP_UCB2SCL << 10) | 0x32) 217 #define I2CMSP432_P3_3_UCB0SDA ((PMAP_UCB0SDA << 10) | 0x33) 219 #define I2CMSP432_P3_3_UCB0SCL ((PMAP_UCB0SCL << 10) | 0x33) 221 #define I2CMSP432_P3_3_UCB2SDA ((PMAP_UCB2SDA << 10) | 0x33) 223 #define I2CMSP432_P3_3_UCB2SCL ((PMAP_UCB2SCL << 10) | 0x33) 226 #define I2CMSP432_P3_4_UCB0SDA ((PMAP_UCB0SDA << 10) | 0x34) 228 #define I2CMSP432_P3_4_UCB0SCL ((PMAP_UCB0SCL << 10) | 0x34) 230 #define I2CMSP432_P3_4_UCB2SDA ((PMAP_UCB2SDA << 10) | 0x34) 232 #define I2CMSP432_P3_4_UCB2SCL ((PMAP_UCB2SCL << 10) | 0x34) 235 #define I2CMSP432_P3_5_UCB0SDA ((PMAP_UCB0SDA << 10) | 0x35) 237 #define I2CMSP432_P3_5_UCB0SCL ((PMAP_UCB0SCL << 10) | 0x35) 239 #define I2CMSP432_P3_5_UCB2SDA ((PMAP_UCB2SDA << 10) | 0x35) 241 #define I2CMSP432_P3_5_UCB2SCL ((PMAP_UCB2SCL << 10) | 0x35) 244 #define I2CMSP432_P3_6_UCB0SDA ((PMAP_UCB0SDA << 10) | 0x36) 246 #define I2CMSP432_P3_6_UCB0SCL ((PMAP_UCB0SCL << 10) | 0x36) 248 #define I2CMSP432_P3_6_UCB2SDA ((PMAP_UCB2SDA << 10) | 0x36) 250 #define I2CMSP432_P3_6_UCB2SCL ((PMAP_UCB2SCL << 10) | 0x36) 253 #define I2CMSP432_P3_7_UCB0SDA ((PMAP_UCB0SDA << 10) | 0x37) 255 #define I2CMSP432_P3_7_UCB0SCL ((PMAP_UCB0SCL << 10) | 0x37) 257 #define I2CMSP432_P3_7_UCB2SDA ((PMAP_UCB2SDA << 10) | 0x37) 259 #define I2CMSP432_P3_7_UCB2SCL ((PMAP_UCB2SCL << 10) | 0x37) 262 #define I2CMSP432_P6_4_UCB1SDA 0x00000164 264 #define I2CMSP432_P6_5_UCB1SCL 0x00000165 266 #define I2CMSP432_P6_6_UCB3SDA 0x00000266 268 #define I2CMSP432_P6_7_UCB3SCL 0x00000267 271 #define I2CMSP432_P7_0_UCB0SDA ((PMAP_UCB0SDA << 10) | 0x70) 273 #define I2CMSP432_P7_0_UCB0SCL ((PMAP_UCB0SCL << 10) | 0x70) 275 #define I2CMSP432_P7_0_UCB2SDA ((PMAP_UCB2SDA << 10) | 0x70) 277 #define I2CMSP432_P7_0_UCB2SCL ((PMAP_UCB2SCL << 10) | 0x70) 280 #define I2CMSP432_P7_1_UCB0SDA ((PMAP_UCB0SDA << 10) | 0x71) 282 #define I2CMSP432_P7_1_UCB0SCL ((PMAP_UCB0SCL << 10) | 0x71) 284 #define I2CMSP432_P7_1_UCB2SDA ((PMAP_UCB2SDA << 10) | 0x71) 286 #define I2CMSP432_P7_1_UCB2SCL ((PMAP_UCB2SCL << 10) | 0x71) 289 #define I2CMSP432_P7_2_UCB0SDA ((PMAP_UCB0SDA << 10) | 0x72) 291 #define I2CMSP432_P7_2_UCB0SCL ((PMAP_UCB0SCL << 10) | 0x72) 293 #define I2CMSP432_P7_2_UCB2SDA ((PMAP_UCB2SDA << 10) | 0x72) 295 #define I2CMSP432_P7_2_UCB2SCL ((PMAP_UCB2SCL << 10) | 0x72) 298 #define I2CMSP432_P7_3_UCB0SDA ((PMAP_UCB0SDA << 10) | 0x73) 300 #define I2CMSP432_P7_3_UCB0SCL ((PMAP_UCB0SCL << 10) | 0x73) 302 #define I2CMSP432_P7_3_UCB2SDA ((PMAP_UCB2SDA << 10) | 0x73) 304 #define I2CMSP432_P7_3_UCB2SCL ((PMAP_UCB2SCL << 10) | 0x73) 307 #define I2CMSP432_P7_4_UCB0SDA ((PMAP_UCB0SDA << 10) | 0x74) 309 #define I2CMSP432_P7_4_UCB0SCL ((PMAP_UCB0SCL << 10) | 0x74) 311 #define I2CMSP432_P7_4_UCB2SDA ((PMAP_UCB2SDA << 10) | 0x74) 313 #define I2CMSP432_P7_4_UCB2SCL ((PMAP_UCB2SCL << 10) | 0x74) 316 #define I2CMSP432_P7_5_UCB0SDA ((PMAP_UCB0SDA << 10) | 0x75) 318 #define I2CMSP432_P7_5_UCB0SCL ((PMAP_UCB0SCL << 10) | 0x75) 320 #define I2CMSP432_P7_5_UCB2SDA ((PMAP_UCB2SDA << 10) | 0x75) 322 #define I2CMSP432_P7_5_UCB2SCL ((PMAP_UCB2SCL << 10) | 0x75) 325 #define I2CMSP432_P7_6_UCB0SDA ((PMAP_UCB0SDA << 10) | 0x76) 327 #define I2CMSP432_P7_6_UCB0SCL ((PMAP_UCB0SCL << 10) | 0x76) 329 #define I2CMSP432_P7_6_UCB2SDA ((PMAP_UCB2SDA << 10) | 0x76) 331 #define I2CMSP432_P7_6_UCB2SCL ((PMAP_UCB2SCL << 10) | 0x76) 334 #define I2CMSP432_P7_7_UCB0SDA ((PMAP_UCB0SDA << 10) | 0x77) 336 #define I2CMSP432_P7_7_UCB0SCL ((PMAP_UCB0SCL << 10) | 0x77) 338 #define I2CMSP432_P7_7_UCB2SDA ((PMAP_UCB2SDA << 10) | 0x77) 340 #define I2CMSP432_P7_7_UCB2SCL ((PMAP_UCB2SCL << 10) | 0x77) 343 #define I2CMSP432_P10_2_UCB3SDA 0x000001A2 345 #define I2CMSP432_P10_3_UCB3SCL 0x000001A3 385 typedef enum I2CMSP432_Mode {
386 I2CMSP432_IDLE_MODE = 0,
387 I2CMSP432_WRITE_MODE,
389 I2CMSP432_ERROR = 0xFF
450 typedef struct I2CMSP432_Object {
451 SemaphoreP_Handle mutex;
452 SemaphoreP_Handle transferComplete;
454 HwiP_Handle hwiHandle;
463 uint8_t *writeBufIdx;
464 size_t writeCountIdx;
470 uint32_t perfConstraintMask;
472 volatile I2CMSP432_Mode mode;
uint16_t clkPin
Definition: I2CMSP432.h:440
I2C transaction.
Definition: I2C.h:464
struct I2CMSP432_HWAttrsV1 I2CMSP432_HWAttrsV1
I2CMSP432 Hardware attributes.
const I2C_FxnTable I2CMSP432_fxnTable
Power notify object structure.
Definition: Power.h:113
uint32_t intNum
Definition: I2CMSP432.h:434
enum I2C_TransferMode_ I2C_TransferMode
I2C transfer mode.
The definition of an I2C function table that contains the required set of functions to control a spec...
Definition: I2C.h:593
enum I2C_BitRate_ I2C_BitRate
I2C bitRate.
uint16_t dataPin
Definition: I2CMSP432.h:442
uint32_t intPriority
Definition: I2CMSP432.h:436
uint8_t clockSource
Definition: I2CMSP432.h:438
void(* I2C_CallbackFxn)(I2C_Handle handle, I2C_Transaction *transaction, bool transferStatus)
I2C callback function.
Definition: I2C.h:506
uint32_t baseAddr
Definition: I2CMSP432.h:432
I2CMSP432 Hardware attributes.
Definition: I2CMSP432.h:430