36 #include <ti/devices/msp432p4xx/inc/msp.h>
40 #ifdef __MCU_HAS_SYSCTL__
65 #define SYSCTL_SRAM_BANK7 SYSCTL_SRAM_BANKEN_BNK7_EN
66 #define SYSCTL_SRAM_BANK6 SYSCTL_SRAM_BANKEN_BNK6_EN
67 #define SYSCTL_SRAM_BANK5 SYSCTL_SRAM_BANKEN_BNK5_EN
68 #define SYSCTL_SRAM_BANK4 SYSCTL_SRAM_BANKEN_BNK4_EN
69 #define SYSCTL_SRAM_BANK3 SYSCTL_SRAM_BANKEN_BNK3_EN
70 #define SYSCTL_SRAM_BANK2 SYSCTL_SRAM_BANKEN_BNK2_EN
71 #define SYSCTL_SRAM_BANK1 SYSCTL_SRAM_BANKEN_BNK1_EN
73 #define SYSCTL_HARD_RESET 1
74 #define SYSCTL_SOFT_RESET 0
76 #define SYSCTL_PERIPH_DMA SYSCTL_PERIHALT_CTL_HALT_DMA
77 #define SYSCTL_PERIPH_WDT SYSCTL_PERIHALT_CTL_HALT_WDT
78 #define SYSCTL_PERIPH_ADC SYSCTL_PERIHALT_CTL_HALT_ADC
79 #define SYSCTL_PERIPH_EUSCIB3 SYSCTL_PERIHALT_CTL_HALT_EUB3
80 #define SYSCTL_PERIPH_EUSCIB2 SYSCTL_PERIHALT_CTL_HALT_EUB2
81 #define SYSCTL_PERIPH_EUSCIB1 SYSCTL_PERIHALT_CTL_HALT_EUB1
82 #define SYSCTL_PERIPH_EUSCIB0 SYSCTL_PERIHALT_CTL_HALT_EUB0
83 #define SYSCTL_PERIPH_EUSCIA3 SYSCTL_PERIHALT_CTL_HALT_EUA3
84 #define SYSCTL_PERIPH_EUSCIA2 SYSCTL_PERIHALT_CTL_HALT_EUA2
85 #define SYSCTL_PERIPH_EUSCIA1 SYSCTL_PERIHALT_CTL_HALT_EUA1
86 #define SYSCTL_PERIPH_EUSCIA0 SYSCTL_PERIHALT_CTL_HALT_EUA0
87 #define SYSCTL_PERIPH_TIMER32_0_MODULE SYSCTL_PERIHALT_CTL_HALT_T32_0
88 #define SYSCTL_PERIPH_TIMER16_3 SYSCTL_PERIHALT_CTL_HALT_T16_3
89 #define SYSCTL_PERIPH_TIMER16_2 SYSCTL_PERIHALT_CTL_HALT_T16_2
90 #define SYSCTL_PERIPH_TIMER16_1 SYSCTL_PERIHALT_CTL_HALT_T16_1
91 #define SYSCTL_PERIPH_TIMER16_0 SYSCTL_PERIHALT_CTL_HALT_T16_0
93 #define SYSCTL_NMIPIN_SRC SYSCTL_NMI_CTLSTAT_PIN_SRC
94 #define SYSCTL_PCM_SRC SYSCTL_NMI_CTLSTAT_PCM_SRC
95 #define SYSCTL_PSS_SRC SYSCTL_NMI_CTLSTAT_PSS_SRC
96 #define SYSCTL_CS_SRC SYSCTL_NMI_CTLSTAT_CS_SRC
98 #define SYSCTL_REBOOT_KEY 0x6900
100 #define SYSCTL_1_2V_REF (uint32_t)&TLV->ADC14_REF1P2V_TS30C - (uint32_t)TLV_BASE
101 #define SYSCTL_1_45V_REF (uint32_t)&TLV->ADC14_REF1P45V_TS30C - (uint32_t)TLV_BASE
102 #define SYSCTL_2_5V_REF (uint32_t)&TLV->ADC14_REF2P5V_TS30C - (uint32_t)TLV_BASE
104 #define SYSCTL_85_DEGREES_C 4
105 #define SYSCTL_30_DEGREES_C 0
108 #define TLV_START 0x00201004
109 #define TLV_TAG_RESERVED1 1
110 #define TLV_TAG_RESERVED2 2
112 #define TLV_TAG_FLASHCTL 4
113 #define TLV_TAG_ADC14 5
114 #define TLV_TAG_RESERVED6 6
115 #define TLV_TAG_RESERVED7 7
116 #define TLV_TAG_REF 8
117 #define TLV_TAG_RESERVED9 9
118 #define TLV_TAG_RESERVED10 10
119 #define TLV_TAG_DEVINFO 11
120 #define TLV_TAG_DIEREC 12
121 #define TLV_TAG_RANDNUM 13
122 #define TLV_TAG_RESERVED14 14
123 #define TLV_TAG_BSL 15
124 #define TLV_TAGEND 0x0BD0E11D
133 uint32_t maxProgramPulses;
134 uint32_t maxErasePulses;
135 } SysCtl_FlashTLV_Info;
139 uint32_t rDCOIR_FCAL_RSEL04;
140 uint32_t rDCOIR_FCAL_RSEL5;
141 uint32_t rDCOIR_MAXPOSTUNE_RSEL04;
142 uint32_t rDCOIR_MAXNEGTUNE_RSEL04;
143 uint32_t rDCOIR_MAXPOSTUNE_RSEL5;
144 uint32_t rDCOIR_MAXNEGTUNE_RSEL5;
145 uint32_t rDCOIR_CONSTK_RSEL04;
146 uint32_t rDCOIR_CONSTK_RSEL5;
147 uint32_t rDCOER_FCAL_RSEL04;
148 uint32_t rDCOER_FCAL_RSEL5;
149 uint32_t rDCOER_MAXPOSTUNE_RSEL04;
150 uint32_t rDCOER_MAXNEGTUNE_RSEL04;
151 uint32_t rDCOER_MAXPOSTUNE_RSEL5;
152 uint32_t rDCOER_MAXNEGTUNE_RSEL5;
153 uint32_t rDCOER_CONSTK_RSEL04;
154 uint32_t rDCOER_CONSTK_RSEL5;
156 } SysCtl_CSCalTLV_Info;
171 extern uint_least32_t SysCtl_getSRAMSize(
void);
180 extern uint_least32_t SysCtl_getFlashSize(
void);
189 extern void SysCtl_rebootDevice(
void);
233 extern void SysCtl_getTLVInfo(uint_fast8_t tag, uint_fast8_t instance,
234 uint_fast8_t *length, uint32_t **data_address);
260 extern void SysCtl_enableSRAMBank(uint_fast8_t sramBank);
285 extern void SysCtl_disableSRAMBank(uint_fast8_t sramBank);
311 extern void SysCtl_enableSRAMBankRetention(uint_fast8_t sramBank);
337 extern void SysCtl_disableSRAMBankRetention(uint_fast8_t sramBank);
369 extern void SysCtl_enablePeripheralAtCPUHalt(uint_fast16_t devices);
403 extern void SysCtl_disablePeripheralAtCPUHalt(uint_fast16_t devices);
419 extern void SysCtl_setWDTTimeoutResetType(uint_fast8_t resetType);
436 extern void SysCtl_setWDTPasswordViolationResetType(uint_fast8_t resetType);
452 extern void SysCtl_disableNMISource(uint_fast8_t flags);
468 extern void SysCtl_enableNMISource(uint_fast8_t flags);
477 extern uint_fast8_t SysCtl_getNMISourceStatus(
void);
488 extern void SysCtl_enableGlitchFilter(
void);
499 extern void SysCtl_disableGlitchFilter(
void);
524 extern uint_fast16_t SysCtl_getTempCalibrationConstant(uint32_t refVoltage,
525 uint32_t temperature);
545 #endif // __SYSCTL_H__