hw_cpu_itm.h
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32 
33 #ifndef __HW_CPU_ITM_H__
34 #define __HW_CPU_ITM_H__
35 
36 //*****************************************************************************
37 //
38 // This section defines the register offsets of
39 // CPU_ITM component
40 //
41 //*****************************************************************************
42 // Stimulus Port 0
43 #define CPU_ITM_O_STIM0 0x00000000
44 
45 // Stimulus Port 1
46 #define CPU_ITM_O_STIM1 0x00000004
47 
48 // Stimulus Port 2
49 #define CPU_ITM_O_STIM2 0x00000008
50 
51 // Stimulus Port 3
52 #define CPU_ITM_O_STIM3 0x0000000C
53 
54 // Stimulus Port 4
55 #define CPU_ITM_O_STIM4 0x00000010
56 
57 // Stimulus Port 5
58 #define CPU_ITM_O_STIM5 0x00000014
59 
60 // Stimulus Port 6
61 #define CPU_ITM_O_STIM6 0x00000018
62 
63 // Stimulus Port 7
64 #define CPU_ITM_O_STIM7 0x0000001C
65 
66 // Stimulus Port 8
67 #define CPU_ITM_O_STIM8 0x00000020
68 
69 // Stimulus Port 9
70 #define CPU_ITM_O_STIM9 0x00000024
71 
72 // Stimulus Port 10
73 #define CPU_ITM_O_STIM10 0x00000028
74 
75 // Stimulus Port 11
76 #define CPU_ITM_O_STIM11 0x0000002C
77 
78 // Stimulus Port 12
79 #define CPU_ITM_O_STIM12 0x00000030
80 
81 // Stimulus Port 13
82 #define CPU_ITM_O_STIM13 0x00000034
83 
84 // Stimulus Port 14
85 #define CPU_ITM_O_STIM14 0x00000038
86 
87 // Stimulus Port 15
88 #define CPU_ITM_O_STIM15 0x0000003C
89 
90 // Stimulus Port 16
91 #define CPU_ITM_O_STIM16 0x00000040
92 
93 // Stimulus Port 17
94 #define CPU_ITM_O_STIM17 0x00000044
95 
96 // Stimulus Port 18
97 #define CPU_ITM_O_STIM18 0x00000048
98 
99 // Stimulus Port 19
100 #define CPU_ITM_O_STIM19 0x0000004C
101 
102 // Stimulus Port 20
103 #define CPU_ITM_O_STIM20 0x00000050
104 
105 // Stimulus Port 21
106 #define CPU_ITM_O_STIM21 0x00000054
107 
108 // Stimulus Port 22
109 #define CPU_ITM_O_STIM22 0x00000058
110 
111 // Stimulus Port 23
112 #define CPU_ITM_O_STIM23 0x0000005C
113 
114 // Stimulus Port 24
115 #define CPU_ITM_O_STIM24 0x00000060
116 
117 // Stimulus Port 25
118 #define CPU_ITM_O_STIM25 0x00000064
119 
120 // Stimulus Port 26
121 #define CPU_ITM_O_STIM26 0x00000068
122 
123 // Stimulus Port 27
124 #define CPU_ITM_O_STIM27 0x0000006C
125 
126 // Stimulus Port 28
127 #define CPU_ITM_O_STIM28 0x00000070
128 
129 // Stimulus Port 29
130 #define CPU_ITM_O_STIM29 0x00000074
131 
132 // Stimulus Port 30
133 #define CPU_ITM_O_STIM30 0x00000078
134 
135 // Stimulus Port 31
136 #define CPU_ITM_O_STIM31 0x0000007C
137 
138 // Trace Enable
139 #define CPU_ITM_O_TER 0x00000E00
140 
141 // Trace Privilege
142 #define CPU_ITM_O_TPR 0x00000E40
143 
144 // Trace Control
145 #define CPU_ITM_O_TCR 0x00000E80
146 
147 // Lock Access
148 #define CPU_ITM_O_LAR 0x00000FB0
149 
150 // Lock Status
151 #define CPU_ITM_O_LSR 0x00000FB4
152 
153 //*****************************************************************************
154 //
155 // Register: CPU_ITM_O_STIM0
156 //
157 //*****************************************************************************
158 // Field: [31:0] STIM0
159 //
160 // A write to this location causes data to be written into the FIFO if
161 // TER.STIMENA0 is set. Reading from the stimulus port returns the FIFO status
162 // in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not
163 // provide an atomic read-modify-write, so it's users responsibility to ensure
164 // exclusive read-modify-write if this ITM port is used concurrently by
165 // interrupts or other threads.
166 #define CPU_ITM_STIM0_STIM0_W 32
167 #define CPU_ITM_STIM0_STIM0_M 0xFFFFFFFF
168 #define CPU_ITM_STIM0_STIM0_S 0
169 
170 //*****************************************************************************
171 //
172 // Register: CPU_ITM_O_STIM1
173 //
174 //*****************************************************************************
175 // Field: [31:0] STIM1
176 //
177 // A write to this location causes data to be written into the FIFO if
178 // TER.STIMENA1 is set. Reading from the stimulus port returns the FIFO status
179 // in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not
180 // provide an atomic read-modify-write, so it's users responsibility to ensure
181 // exclusive read-modify-write if this ITM port is used concurrently by
182 // interrupts or other threads.
183 #define CPU_ITM_STIM1_STIM1_W 32
184 #define CPU_ITM_STIM1_STIM1_M 0xFFFFFFFF
185 #define CPU_ITM_STIM1_STIM1_S 0
186 
187 //*****************************************************************************
188 //
189 // Register: CPU_ITM_O_STIM2
190 //
191 //*****************************************************************************
192 // Field: [31:0] STIM2
193 //
194 // A write to this location causes data to be written into the FIFO if
195 // TER.STIMENA2 is set. Reading from the stimulus port returns the FIFO status
196 // in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not
197 // provide an atomic read-modify-write, so it's users responsibility to ensure
198 // exclusive read-modify-write if this ITM port is used concurrently by
199 // interrupts or other threads.
200 #define CPU_ITM_STIM2_STIM2_W 32
201 #define CPU_ITM_STIM2_STIM2_M 0xFFFFFFFF
202 #define CPU_ITM_STIM2_STIM2_S 0
203 
204 //*****************************************************************************
205 //
206 // Register: CPU_ITM_O_STIM3
207 //
208 //*****************************************************************************
209 // Field: [31:0] STIM3
210 //
211 // A write to this location causes data to be written into the FIFO if
212 // TER.STIMENA3 is set. Reading from the stimulus port returns the FIFO status
213 // in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not
214 // provide an atomic read-modify-write, so it's users responsibility to ensure
215 // exclusive read-modify-write if this ITM port is used concurrently by
216 // interrupts or other threads.
217 #define CPU_ITM_STIM3_STIM3_W 32
218 #define CPU_ITM_STIM3_STIM3_M 0xFFFFFFFF
219 #define CPU_ITM_STIM3_STIM3_S 0
220 
221 //*****************************************************************************
222 //
223 // Register: CPU_ITM_O_STIM4
224 //
225 //*****************************************************************************
226 // Field: [31:0] STIM4
227 //
228 // A write to this location causes data to be written into the FIFO if
229 // TER.STIMENA4 is set. Reading from the stimulus port returns the FIFO status
230 // in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not
231 // provide an atomic read-modify-write, so it's users responsibility to ensure
232 // exclusive read-modify-write if this ITM port is used concurrently by
233 // interrupts or other threads.
234 #define CPU_ITM_STIM4_STIM4_W 32
235 #define CPU_ITM_STIM4_STIM4_M 0xFFFFFFFF
236 #define CPU_ITM_STIM4_STIM4_S 0
237 
238 //*****************************************************************************
239 //
240 // Register: CPU_ITM_O_STIM5
241 //
242 //*****************************************************************************
243 // Field: [31:0] STIM5
244 //
245 // A write to this location causes data to be written into the FIFO if
246 // TER.STIMENA5 is set. Reading from the stimulus port returns the FIFO status
247 // in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not
248 // provide an atomic read-modify-write, so it's users responsibility to ensure
249 // exclusive read-modify-write if this ITM port is used concurrently by
250 // interrupts or other threads.
251 #define CPU_ITM_STIM5_STIM5_W 32
252 #define CPU_ITM_STIM5_STIM5_M 0xFFFFFFFF
253 #define CPU_ITM_STIM5_STIM5_S 0
254 
255 //*****************************************************************************
256 //
257 // Register: CPU_ITM_O_STIM6
258 //
259 //*****************************************************************************
260 // Field: [31:0] STIM6
261 //
262 // A write to this location causes data to be written into the FIFO if
263 // TER.STIMENA6 is set. Reading from the stimulus port returns the FIFO status
264 // in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not
265 // provide an atomic read-modify-write, so it's users responsibility to ensure
266 // exclusive read-modify-write if this ITM port is used concurrently by
267 // interrupts or other threads.
268 #define CPU_ITM_STIM6_STIM6_W 32
269 #define CPU_ITM_STIM6_STIM6_M 0xFFFFFFFF
270 #define CPU_ITM_STIM6_STIM6_S 0
271 
272 //*****************************************************************************
273 //
274 // Register: CPU_ITM_O_STIM7
275 //
276 //*****************************************************************************
277 // Field: [31:0] STIM7
278 //
279 // A write to this location causes data to be written into the FIFO if
280 // TER.STIMENA7 is set. Reading from the stimulus port returns the FIFO status
281 // in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not
282 // provide an atomic read-modify-write, so it's users responsibility to ensure
283 // exclusive read-modify-write if this ITM port is used concurrently by
284 // interrupts or other threads.
285 #define CPU_ITM_STIM7_STIM7_W 32
286 #define CPU_ITM_STIM7_STIM7_M 0xFFFFFFFF
287 #define CPU_ITM_STIM7_STIM7_S 0
288 
289 //*****************************************************************************
290 //
291 // Register: CPU_ITM_O_STIM8
292 //
293 //*****************************************************************************
294 // Field: [31:0] STIM8
295 //
296 // A write to this location causes data to be written into the FIFO if
297 // TER.STIMENA8 is set. Reading from the stimulus port returns the FIFO status
298 // in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not
299 // provide an atomic read-modify-write, so it's users responsibility to ensure
300 // exclusive read-modify-write if this ITM port is used concurrently by
301 // interrupts or other threads.
302 #define CPU_ITM_STIM8_STIM8_W 32
303 #define CPU_ITM_STIM8_STIM8_M 0xFFFFFFFF
304 #define CPU_ITM_STIM8_STIM8_S 0
305 
306 //*****************************************************************************
307 //
308 // Register: CPU_ITM_O_STIM9
309 //
310 //*****************************************************************************
311 // Field: [31:0] STIM9
312 //
313 // A write to this location causes data to be written into the FIFO if
314 // TER.STIMENA9 is set. Reading from the stimulus port returns the FIFO status
315 // in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not
316 // provide an atomic read-modify-write, so it's users responsibility to ensure
317 // exclusive read-modify-write if this ITM port is used concurrently by
318 // interrupts or other threads.
319 #define CPU_ITM_STIM9_STIM9_W 32
320 #define CPU_ITM_STIM9_STIM9_M 0xFFFFFFFF
321 #define CPU_ITM_STIM9_STIM9_S 0
322 
323 //*****************************************************************************
324 //
325 // Register: CPU_ITM_O_STIM10
326 //
327 //*****************************************************************************
328 // Field: [31:0] STIM10
329 //
330 // A write to this location causes data to be written into the FIFO if
331 // TER.STIMENA10 is set. Reading from the stimulus port returns the FIFO status
332 // in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not
333 // provide an atomic read-modify-write, so it's users responsibility to ensure
334 // exclusive read-modify-write if this ITM port is used concurrently by
335 // interrupts or other threads.
336 #define CPU_ITM_STIM10_STIM10_W 32
337 #define CPU_ITM_STIM10_STIM10_M 0xFFFFFFFF
338 #define CPU_ITM_STIM10_STIM10_S 0
339 
340 //*****************************************************************************
341 //
342 // Register: CPU_ITM_O_STIM11
343 //
344 //*****************************************************************************
345 // Field: [31:0] STIM11
346 //
347 // A write to this location causes data to be written into the FIFO if
348 // TER.STIMENA11 is set. Reading from the stimulus port returns the FIFO status
349 // in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not
350 // provide an atomic read-modify-write, so it's users responsibility to ensure
351 // exclusive read-modify-write if this ITM port is used concurrently by
352 // interrupts or other threads.
353 #define CPU_ITM_STIM11_STIM11_W 32
354 #define CPU_ITM_STIM11_STIM11_M 0xFFFFFFFF
355 #define CPU_ITM_STIM11_STIM11_S 0
356 
357 //*****************************************************************************
358 //
359 // Register: CPU_ITM_O_STIM12
360 //
361 //*****************************************************************************
362 // Field: [31:0] STIM12
363 //
364 // A write to this location causes data to be written into the FIFO if
365 // TER.STIMENA12 is set. Reading from the stimulus port returns the FIFO status
366 // in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not
367 // provide an atomic read-modify-write, so it's users responsibility to ensure
368 // exclusive read-modify-write if this ITM port is used concurrently by
369 // interrupts or other threads.
370 #define CPU_ITM_STIM12_STIM12_W 32
371 #define CPU_ITM_STIM12_STIM12_M 0xFFFFFFFF
372 #define CPU_ITM_STIM12_STIM12_S 0
373 
374 //*****************************************************************************
375 //
376 // Register: CPU_ITM_O_STIM13
377 //
378 //*****************************************************************************
379 // Field: [31:0] STIM13
380 //
381 // A write to this location causes data to be written into the FIFO if
382 // TER.STIMENA13 is set. Reading from the stimulus port returns the FIFO status
383 // in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not
384 // provide an atomic read-modify-write, so it's users responsibility to ensure
385 // exclusive read-modify-write if this ITM port is used concurrently by
386 // interrupts or other threads.
387 #define CPU_ITM_STIM13_STIM13_W 32
388 #define CPU_ITM_STIM13_STIM13_M 0xFFFFFFFF
389 #define CPU_ITM_STIM13_STIM13_S 0
390 
391 //*****************************************************************************
392 //
393 // Register: CPU_ITM_O_STIM14
394 //
395 //*****************************************************************************
396 // Field: [31:0] STIM14
397 //
398 // A write to this location causes data to be written into the FIFO if
399 // TER.STIMENA14 is set. Reading from the stimulus port returns the FIFO status
400 // in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not
401 // provide an atomic read-modify-write, so it's users responsibility to ensure
402 // exclusive read-modify-write if this ITM port is used concurrently by
403 // interrupts or other threads.
404 #define CPU_ITM_STIM14_STIM14_W 32
405 #define CPU_ITM_STIM14_STIM14_M 0xFFFFFFFF
406 #define CPU_ITM_STIM14_STIM14_S 0
407 
408 //*****************************************************************************
409 //
410 // Register: CPU_ITM_O_STIM15
411 //
412 //*****************************************************************************
413 // Field: [31:0] STIM15
414 //
415 // A write to this location causes data to be written into the FIFO if
416 // TER.STIMENA15 is set. Reading from the stimulus port returns the FIFO status
417 // in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not
418 // provide an atomic read-modify-write, so it's users responsibility to ensure
419 // exclusive read-modify-write if this ITM port is used concurrently by
420 // interrupts or other threads.
421 #define CPU_ITM_STIM15_STIM15_W 32
422 #define CPU_ITM_STIM15_STIM15_M 0xFFFFFFFF
423 #define CPU_ITM_STIM15_STIM15_S 0
424 
425 //*****************************************************************************
426 //
427 // Register: CPU_ITM_O_STIM16
428 //
429 //*****************************************************************************
430 // Field: [31:0] STIM16
431 //
432 // A write to this location causes data to be written into the FIFO if
433 // TER.STIMENA16 is set. Reading from the stimulus port returns the FIFO status
434 // in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not
435 // provide an atomic read-modify-write, so it's users responsibility to ensure
436 // exclusive read-modify-write if this ITM port is used concurrently by
437 // interrupts or other threads.
438 #define CPU_ITM_STIM16_STIM16_W 32
439 #define CPU_ITM_STIM16_STIM16_M 0xFFFFFFFF
440 #define CPU_ITM_STIM16_STIM16_S 0
441 
442 //*****************************************************************************
443 //
444 // Register: CPU_ITM_O_STIM17
445 //
446 //*****************************************************************************
447 // Field: [31:0] STIM17
448 //
449 // A write to this location causes data to be written into the FIFO if
450 // TER.STIMENA17 is set. Reading from the stimulus port returns the FIFO status
451 // in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not
452 // provide an atomic read-modify-write, so it's users responsibility to ensure
453 // exclusive read-modify-write if this ITM port is used concurrently by
454 // interrupts or other threads.
455 #define CPU_ITM_STIM17_STIM17_W 32
456 #define CPU_ITM_STIM17_STIM17_M 0xFFFFFFFF
457 #define CPU_ITM_STIM17_STIM17_S 0
458 
459 //*****************************************************************************
460 //
461 // Register: CPU_ITM_O_STIM18
462 //
463 //*****************************************************************************
464 // Field: [31:0] STIM18
465 //
466 // A write to this location causes data to be written into the FIFO if
467 // TER.STIMENA18 is set. Reading from the stimulus port returns the FIFO status
468 // in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not
469 // provide an atomic read-modify-write, so it's users responsibility to ensure
470 // exclusive read-modify-write if this ITM port is used concurrently by
471 // interrupts or other threads.
472 #define CPU_ITM_STIM18_STIM18_W 32
473 #define CPU_ITM_STIM18_STIM18_M 0xFFFFFFFF
474 #define CPU_ITM_STIM18_STIM18_S 0
475 
476 //*****************************************************************************
477 //
478 // Register: CPU_ITM_O_STIM19
479 //
480 //*****************************************************************************
481 // Field: [31:0] STIM19
482 //
483 // A write to this location causes data to be written into the FIFO if
484 // TER.STIMENA19 is set. Reading from the stimulus port returns the FIFO status
485 // in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not
486 // provide an atomic read-modify-write, so it's users responsibility to ensure
487 // exclusive read-modify-write if this ITM port is used concurrently by
488 // interrupts or other threads.
489 #define CPU_ITM_STIM19_STIM19_W 32
490 #define CPU_ITM_STIM19_STIM19_M 0xFFFFFFFF
491 #define CPU_ITM_STIM19_STIM19_S 0
492 
493 //*****************************************************************************
494 //
495 // Register: CPU_ITM_O_STIM20
496 //
497 //*****************************************************************************
498 // Field: [31:0] STIM20
499 //
500 // A write to this location causes data to be written into the FIFO if
501 // TER.STIMENA20 is set. Reading from the stimulus port returns the FIFO status
502 // in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not
503 // provide an atomic read-modify-write, so it's users responsibility to ensure
504 // exclusive read-modify-write if this ITM port is used concurrently by
505 // interrupts or other threads.
506 #define CPU_ITM_STIM20_STIM20_W 32
507 #define CPU_ITM_STIM20_STIM20_M 0xFFFFFFFF
508 #define CPU_ITM_STIM20_STIM20_S 0
509 
510 //*****************************************************************************
511 //
512 // Register: CPU_ITM_O_STIM21
513 //
514 //*****************************************************************************
515 // Field: [31:0] STIM21
516 //
517 // A write to this location causes data to be written into the FIFO if
518 // TER.STIMENA21 is set. Reading from the stimulus port returns the FIFO status
519 // in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not
520 // provide an atomic read-modify-write, so it's users responsibility to ensure
521 // exclusive read-modify-write if this ITM port is used concurrently by
522 // interrupts or other threads.
523 #define CPU_ITM_STIM21_STIM21_W 32
524 #define CPU_ITM_STIM21_STIM21_M 0xFFFFFFFF
525 #define CPU_ITM_STIM21_STIM21_S 0
526 
527 //*****************************************************************************
528 //
529 // Register: CPU_ITM_O_STIM22
530 //
531 //*****************************************************************************
532 // Field: [31:0] STIM22
533 //
534 // A write to this location causes data to be written into the FIFO if
535 // TER.STIMENA22 is set. Reading from the stimulus port returns the FIFO status
536 // in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not
537 // provide an atomic read-modify-write, so it's users responsibility to ensure
538 // exclusive read-modify-write if this ITM port is used concurrently by
539 // interrupts or other threads.
540 #define CPU_ITM_STIM22_STIM22_W 32
541 #define CPU_ITM_STIM22_STIM22_M 0xFFFFFFFF
542 #define CPU_ITM_STIM22_STIM22_S 0
543 
544 //*****************************************************************************
545 //
546 // Register: CPU_ITM_O_STIM23
547 //
548 //*****************************************************************************
549 // Field: [31:0] STIM23
550 //
551 // A write to this location causes data to be written into the FIFO if
552 // TER.STIMENA23 is set. Reading from the stimulus port returns the FIFO status
553 // in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not
554 // provide an atomic read-modify-write, so it's users responsibility to ensure
555 // exclusive read-modify-write if this ITM port is used concurrently by
556 // interrupts or other threads.
557 #define CPU_ITM_STIM23_STIM23_W 32
558 #define CPU_ITM_STIM23_STIM23_M 0xFFFFFFFF
559 #define CPU_ITM_STIM23_STIM23_S 0
560 
561 //*****************************************************************************
562 //
563 // Register: CPU_ITM_O_STIM24
564 //
565 //*****************************************************************************
566 // Field: [31:0] STIM24
567 //
568 // A write to this location causes data to be written into the FIFO if
569 // TER.STIMENA24 is set. Reading from the stimulus port returns the FIFO status
570 // in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not
571 // provide an atomic read-modify-write, so it's users responsibility to ensure
572 // exclusive read-modify-write if this ITM port is used concurrently by
573 // interrupts or other threads.
574 #define CPU_ITM_STIM24_STIM24_W 32
575 #define CPU_ITM_STIM24_STIM24_M 0xFFFFFFFF
576 #define CPU_ITM_STIM24_STIM24_S 0
577 
578 //*****************************************************************************
579 //
580 // Register: CPU_ITM_O_STIM25
581 //
582 //*****************************************************************************
583 // Field: [31:0] STIM25
584 //
585 // A write to this location causes data to be written into the FIFO if
586 // TER.STIMENA25 is set. Reading from the stimulus port returns the FIFO status
587 // in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not
588 // provide an atomic read-modify-write, so it's users responsibility to ensure
589 // exclusive read-modify-write if this ITM port is used concurrently by
590 // interrupts or other threads.
591 #define CPU_ITM_STIM25_STIM25_W 32
592 #define CPU_ITM_STIM25_STIM25_M 0xFFFFFFFF
593 #define CPU_ITM_STIM25_STIM25_S 0
594 
595 //*****************************************************************************
596 //
597 // Register: CPU_ITM_O_STIM26
598 //
599 //*****************************************************************************
600 // Field: [31:0] STIM26
601 //
602 // A write to this location causes data to be written into the FIFO if
603 // TER.STIMENA26 is set. Reading from the stimulus port returns the FIFO status
604 // in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not
605 // provide an atomic read-modify-write, so it's users responsibility to ensure
606 // exclusive read-modify-write if this ITM port is used concurrently by
607 // interrupts or other threads.
608 #define CPU_ITM_STIM26_STIM26_W 32
609 #define CPU_ITM_STIM26_STIM26_M 0xFFFFFFFF
610 #define CPU_ITM_STIM26_STIM26_S 0
611 
612 //*****************************************************************************
613 //
614 // Register: CPU_ITM_O_STIM27
615 //
616 //*****************************************************************************
617 // Field: [31:0] STIM27
618 //
619 // A write to this location causes data to be written into the FIFO if
620 // TER.STIMENA27 is set. Reading from the stimulus port returns the FIFO status
621 // in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not
622 // provide an atomic read-modify-write, so it's users responsibility to ensure
623 // exclusive read-modify-write if this ITM port is used concurrently by
624 // interrupts or other threads.
625 #define CPU_ITM_STIM27_STIM27_W 32
626 #define CPU_ITM_STIM27_STIM27_M 0xFFFFFFFF
627 #define CPU_ITM_STIM27_STIM27_S 0
628 
629 //*****************************************************************************
630 //
631 // Register: CPU_ITM_O_STIM28
632 //
633 //*****************************************************************************
634 // Field: [31:0] STIM28
635 //
636 // A write to this location causes data to be written into the FIFO if
637 // TER.STIMENA28 is set. Reading from the stimulus port returns the FIFO status
638 // in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not
639 // provide an atomic read-modify-write, so it's users responsibility to ensure
640 // exclusive read-modify-write if this ITM port is used concurrently by
641 // interrupts or other threads.
642 #define CPU_ITM_STIM28_STIM28_W 32
643 #define CPU_ITM_STIM28_STIM28_M 0xFFFFFFFF
644 #define CPU_ITM_STIM28_STIM28_S 0
645 
646 //*****************************************************************************
647 //
648 // Register: CPU_ITM_O_STIM29
649 //
650 //*****************************************************************************
651 // Field: [31:0] STIM29
652 //
653 // A write to this location causes data to be written into the FIFO if
654 // TER.STIMENA29 is set. Reading from the stimulus port returns the FIFO status
655 // in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not
656 // provide an atomic read-modify-write, so it's users responsibility to ensure
657 // exclusive read-modify-write if this ITM port is used concurrently by
658 // interrupts or other threads.
659 #define CPU_ITM_STIM29_STIM29_W 32
660 #define CPU_ITM_STIM29_STIM29_M 0xFFFFFFFF
661 #define CPU_ITM_STIM29_STIM29_S 0
662 
663 //*****************************************************************************
664 //
665 // Register: CPU_ITM_O_STIM30
666 //
667 //*****************************************************************************
668 // Field: [31:0] STIM30
669 //
670 // A write to this location causes data to be written into the FIFO if
671 // TER.STIMENA30 is set. Reading from the stimulus port returns the FIFO status
672 // in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not
673 // provide an atomic read-modify-write, so it's users responsibility to ensure
674 // exclusive read-modify-write if this ITM port is used concurrently by
675 // interrupts or other threads.
676 #define CPU_ITM_STIM30_STIM30_W 32
677 #define CPU_ITM_STIM30_STIM30_M 0xFFFFFFFF
678 #define CPU_ITM_STIM30_STIM30_S 0
679 
680 //*****************************************************************************
681 //
682 // Register: CPU_ITM_O_STIM31
683 //
684 //*****************************************************************************
685 // Field: [31:0] STIM31
686 //
687 // A write to this location causes data to be written into the FIFO if
688 // TER.STIMENA31 is set. Reading from the stimulus port returns the FIFO status
689 // in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not
690 // provide an atomic read-modify-write, so it's users responsibility to ensure
691 // exclusive read-modify-write if this ITM port is used concurrently by
692 // interrupts or other threads.
693 #define CPU_ITM_STIM31_STIM31_W 32
694 #define CPU_ITM_STIM31_STIM31_M 0xFFFFFFFF
695 #define CPU_ITM_STIM31_STIM31_S 0
696 
697 //*****************************************************************************
698 //
699 // Register: CPU_ITM_O_TER
700 //
701 //*****************************************************************************
702 // Field: [31] STIMENA31
703 //
704 // Bit mask to enable tracing on ITM stimulus port 31.
705 #define CPU_ITM_TER_STIMENA31 0x80000000
706 #define CPU_ITM_TER_STIMENA31_BITN 31
707 #define CPU_ITM_TER_STIMENA31_M 0x80000000
708 #define CPU_ITM_TER_STIMENA31_S 31
709 
710 // Field: [30] STIMENA30
711 //
712 // Bit mask to enable tracing on ITM stimulus port 30.
713 #define CPU_ITM_TER_STIMENA30 0x40000000
714 #define CPU_ITM_TER_STIMENA30_BITN 30
715 #define CPU_ITM_TER_STIMENA30_M 0x40000000
716 #define CPU_ITM_TER_STIMENA30_S 30
717 
718 // Field: [29] STIMENA29
719 //
720 // Bit mask to enable tracing on ITM stimulus port 29.
721 #define CPU_ITM_TER_STIMENA29 0x20000000
722 #define CPU_ITM_TER_STIMENA29_BITN 29
723 #define CPU_ITM_TER_STIMENA29_M 0x20000000
724 #define CPU_ITM_TER_STIMENA29_S 29
725 
726 // Field: [28] STIMENA28
727 //
728 // Bit mask to enable tracing on ITM stimulus port 28.
729 #define CPU_ITM_TER_STIMENA28 0x10000000
730 #define CPU_ITM_TER_STIMENA28_BITN 28
731 #define CPU_ITM_TER_STIMENA28_M 0x10000000
732 #define CPU_ITM_TER_STIMENA28_S 28
733 
734 // Field: [27] STIMENA27
735 //
736 // Bit mask to enable tracing on ITM stimulus port 27.
737 #define CPU_ITM_TER_STIMENA27 0x08000000
738 #define CPU_ITM_TER_STIMENA27_BITN 27
739 #define CPU_ITM_TER_STIMENA27_M 0x08000000
740 #define CPU_ITM_TER_STIMENA27_S 27
741 
742 // Field: [26] STIMENA26
743 //
744 // Bit mask to enable tracing on ITM stimulus port 26.
745 #define CPU_ITM_TER_STIMENA26 0x04000000
746 #define CPU_ITM_TER_STIMENA26_BITN 26
747 #define CPU_ITM_TER_STIMENA26_M 0x04000000
748 #define CPU_ITM_TER_STIMENA26_S 26
749 
750 // Field: [25] STIMENA25
751 //
752 // Bit mask to enable tracing on ITM stimulus port 25.
753 #define CPU_ITM_TER_STIMENA25 0x02000000
754 #define CPU_ITM_TER_STIMENA25_BITN 25
755 #define CPU_ITM_TER_STIMENA25_M 0x02000000
756 #define CPU_ITM_TER_STIMENA25_S 25
757 
758 // Field: [24] STIMENA24
759 //
760 // Bit mask to enable tracing on ITM stimulus port 24.
761 #define CPU_ITM_TER_STIMENA24 0x01000000
762 #define CPU_ITM_TER_STIMENA24_BITN 24
763 #define CPU_ITM_TER_STIMENA24_M 0x01000000
764 #define CPU_ITM_TER_STIMENA24_S 24
765 
766 // Field: [23] STIMENA23
767 //
768 // Bit mask to enable tracing on ITM stimulus port 23.
769 #define CPU_ITM_TER_STIMENA23 0x00800000
770 #define CPU_ITM_TER_STIMENA23_BITN 23
771 #define CPU_ITM_TER_STIMENA23_M 0x00800000
772 #define CPU_ITM_TER_STIMENA23_S 23
773 
774 // Field: [22] STIMENA22
775 //
776 // Bit mask to enable tracing on ITM stimulus port 22.
777 #define CPU_ITM_TER_STIMENA22 0x00400000
778 #define CPU_ITM_TER_STIMENA22_BITN 22
779 #define CPU_ITM_TER_STIMENA22_M 0x00400000
780 #define CPU_ITM_TER_STIMENA22_S 22
781 
782 // Field: [21] STIMENA21
783 //
784 // Bit mask to enable tracing on ITM stimulus port 21.
785 #define CPU_ITM_TER_STIMENA21 0x00200000
786 #define CPU_ITM_TER_STIMENA21_BITN 21
787 #define CPU_ITM_TER_STIMENA21_M 0x00200000
788 #define CPU_ITM_TER_STIMENA21_S 21
789 
790 // Field: [20] STIMENA20
791 //
792 // Bit mask to enable tracing on ITM stimulus port 20.
793 #define CPU_ITM_TER_STIMENA20 0x00100000
794 #define CPU_ITM_TER_STIMENA20_BITN 20
795 #define CPU_ITM_TER_STIMENA20_M 0x00100000
796 #define CPU_ITM_TER_STIMENA20_S 20
797 
798 // Field: [19] STIMENA19
799 //
800 // Bit mask to enable tracing on ITM stimulus port 19.
801 #define CPU_ITM_TER_STIMENA19 0x00080000
802 #define CPU_ITM_TER_STIMENA19_BITN 19
803 #define CPU_ITM_TER_STIMENA19_M 0x00080000
804 #define CPU_ITM_TER_STIMENA19_S 19
805 
806 // Field: [18] STIMENA18
807 //
808 // Bit mask to enable tracing on ITM stimulus port 18.
809 #define CPU_ITM_TER_STIMENA18 0x00040000
810 #define CPU_ITM_TER_STIMENA18_BITN 18
811 #define CPU_ITM_TER_STIMENA18_M 0x00040000
812 #define CPU_ITM_TER_STIMENA18_S 18
813 
814 // Field: [17] STIMENA17
815 //
816 // Bit mask to enable tracing on ITM stimulus port 17.
817 #define CPU_ITM_TER_STIMENA17 0x00020000
818 #define CPU_ITM_TER_STIMENA17_BITN 17
819 #define CPU_ITM_TER_STIMENA17_M 0x00020000
820 #define CPU_ITM_TER_STIMENA17_S 17
821 
822 // Field: [16] STIMENA16
823 //
824 // Bit mask to enable tracing on ITM stimulus port 16.
825 #define CPU_ITM_TER_STIMENA16 0x00010000
826 #define CPU_ITM_TER_STIMENA16_BITN 16
827 #define CPU_ITM_TER_STIMENA16_M 0x00010000
828 #define CPU_ITM_TER_STIMENA16_S 16
829 
830 // Field: [15] STIMENA15
831 //
832 // Bit mask to enable tracing on ITM stimulus port 15.
833 #define CPU_ITM_TER_STIMENA15 0x00008000
834 #define CPU_ITM_TER_STIMENA15_BITN 15
835 #define CPU_ITM_TER_STIMENA15_M 0x00008000
836 #define CPU_ITM_TER_STIMENA15_S 15
837 
838 // Field: [14] STIMENA14
839 //
840 // Bit mask to enable tracing on ITM stimulus port 14.
841 #define CPU_ITM_TER_STIMENA14 0x00004000
842 #define CPU_ITM_TER_STIMENA14_BITN 14
843 #define CPU_ITM_TER_STIMENA14_M 0x00004000
844 #define CPU_ITM_TER_STIMENA14_S 14
845 
846 // Field: [13] STIMENA13
847 //
848 // Bit mask to enable tracing on ITM stimulus port 13.
849 #define CPU_ITM_TER_STIMENA13 0x00002000
850 #define CPU_ITM_TER_STIMENA13_BITN 13
851 #define CPU_ITM_TER_STIMENA13_M 0x00002000
852 #define CPU_ITM_TER_STIMENA13_S 13
853 
854 // Field: [12] STIMENA12
855 //
856 // Bit mask to enable tracing on ITM stimulus port 12.
857 #define CPU_ITM_TER_STIMENA12 0x00001000
858 #define CPU_ITM_TER_STIMENA12_BITN 12
859 #define CPU_ITM_TER_STIMENA12_M 0x00001000
860 #define CPU_ITM_TER_STIMENA12_S 12
861 
862 // Field: [11] STIMENA11
863 //
864 // Bit mask to enable tracing on ITM stimulus port 11.
865 #define CPU_ITM_TER_STIMENA11 0x00000800
866 #define CPU_ITM_TER_STIMENA11_BITN 11
867 #define CPU_ITM_TER_STIMENA11_M 0x00000800
868 #define CPU_ITM_TER_STIMENA11_S 11
869 
870 // Field: [10] STIMENA10
871 //
872 // Bit mask to enable tracing on ITM stimulus port 10.
873 #define CPU_ITM_TER_STIMENA10 0x00000400
874 #define CPU_ITM_TER_STIMENA10_BITN 10
875 #define CPU_ITM_TER_STIMENA10_M 0x00000400
876 #define CPU_ITM_TER_STIMENA10_S 10
877 
878 // Field: [9] STIMENA9
879 //
880 // Bit mask to enable tracing on ITM stimulus port 9.
881 #define CPU_ITM_TER_STIMENA9 0x00000200
882 #define CPU_ITM_TER_STIMENA9_BITN 9
883 #define CPU_ITM_TER_STIMENA9_M 0x00000200
884 #define CPU_ITM_TER_STIMENA9_S 9
885 
886 // Field: [8] STIMENA8
887 //
888 // Bit mask to enable tracing on ITM stimulus port 8.
889 #define CPU_ITM_TER_STIMENA8 0x00000100
890 #define CPU_ITM_TER_STIMENA8_BITN 8
891 #define CPU_ITM_TER_STIMENA8_M 0x00000100
892 #define CPU_ITM_TER_STIMENA8_S 8
893 
894 // Field: [7] STIMENA7
895 //
896 // Bit mask to enable tracing on ITM stimulus port 7.
897 #define CPU_ITM_TER_STIMENA7 0x00000080
898 #define CPU_ITM_TER_STIMENA7_BITN 7
899 #define CPU_ITM_TER_STIMENA7_M 0x00000080
900 #define CPU_ITM_TER_STIMENA7_S 7
901 
902 // Field: [6] STIMENA6
903 //
904 // Bit mask to enable tracing on ITM stimulus port 6.
905 #define CPU_ITM_TER_STIMENA6 0x00000040
906 #define CPU_ITM_TER_STIMENA6_BITN 6
907 #define CPU_ITM_TER_STIMENA6_M 0x00000040
908 #define CPU_ITM_TER_STIMENA6_S 6
909 
910 // Field: [5] STIMENA5
911 //
912 // Bit mask to enable tracing on ITM stimulus port 5.
913 #define CPU_ITM_TER_STIMENA5 0x00000020
914 #define CPU_ITM_TER_STIMENA5_BITN 5
915 #define CPU_ITM_TER_STIMENA5_M 0x00000020
916 #define CPU_ITM_TER_STIMENA5_S 5
917 
918 // Field: [4] STIMENA4
919 //
920 // Bit mask to enable tracing on ITM stimulus port 4.
921 #define CPU_ITM_TER_STIMENA4 0x00000010
922 #define CPU_ITM_TER_STIMENA4_BITN 4
923 #define CPU_ITM_TER_STIMENA4_M 0x00000010
924 #define CPU_ITM_TER_STIMENA4_S 4
925 
926 // Field: [3] STIMENA3
927 //
928 // Bit mask to enable tracing on ITM stimulus port 3.
929 #define CPU_ITM_TER_STIMENA3 0x00000008
930 #define CPU_ITM_TER_STIMENA3_BITN 3
931 #define CPU_ITM_TER_STIMENA3_M 0x00000008
932 #define CPU_ITM_TER_STIMENA3_S 3
933 
934 // Field: [2] STIMENA2
935 //
936 // Bit mask to enable tracing on ITM stimulus port 2.
937 #define CPU_ITM_TER_STIMENA2 0x00000004
938 #define CPU_ITM_TER_STIMENA2_BITN 2
939 #define CPU_ITM_TER_STIMENA2_M 0x00000004
940 #define CPU_ITM_TER_STIMENA2_S 2
941 
942 // Field: [1] STIMENA1
943 //
944 // Bit mask to enable tracing on ITM stimulus port 1.
945 #define CPU_ITM_TER_STIMENA1 0x00000002
946 #define CPU_ITM_TER_STIMENA1_BITN 1
947 #define CPU_ITM_TER_STIMENA1_M 0x00000002
948 #define CPU_ITM_TER_STIMENA1_S 1
949 
950 // Field: [0] STIMENA0
951 //
952 // Bit mask to enable tracing on ITM stimulus port 0.
953 #define CPU_ITM_TER_STIMENA0 0x00000001
954 #define CPU_ITM_TER_STIMENA0_BITN 0
955 #define CPU_ITM_TER_STIMENA0_M 0x00000001
956 #define CPU_ITM_TER_STIMENA0_S 0
957 
958 //*****************************************************************************
959 //
960 // Register: CPU_ITM_O_TPR
961 //
962 //*****************************************************************************
963 // Field: [3:0] PRIVMASK
964 //
965 // Bit mask to enable unprivileged (User) access to ITM stimulus ports:
966 //
967 // Bit [0] enables stimulus ports 0, 1, ..., and 7.
968 // Bit [1] enables stimulus ports 8, 9, ..., and 15.
969 // Bit [2] enables stimulus ports 16, 17, ..., and 23.
970 // Bit [3] enables stimulus ports 24, 25, ..., and 31.
971 //
972 // 0: User access allowed to stimulus ports
973 // 1: Privileged access only to stimulus ports
974 #define CPU_ITM_TPR_PRIVMASK_W 4
975 #define CPU_ITM_TPR_PRIVMASK_M 0x0000000F
976 #define CPU_ITM_TPR_PRIVMASK_S 0
977 
978 //*****************************************************************************
979 //
980 // Register: CPU_ITM_O_TCR
981 //
982 //*****************************************************************************
983 // Field: [23] BUSY
984 //
985 // Set when ITM events present and being drained.
986 #define CPU_ITM_TCR_BUSY 0x00800000
987 #define CPU_ITM_TCR_BUSY_BITN 23
988 #define CPU_ITM_TCR_BUSY_M 0x00800000
989 #define CPU_ITM_TCR_BUSY_S 23
990 
991 // Field: [22:16] ATBID
992 //
993 // Trace Bus ID for CoreSight system. Optional identifier for multi-source
994 // trace stream formatting. If multi-source trace is in use, this field must be
995 // written with a non-zero value.
996 #define CPU_ITM_TCR_ATBID_W 7
997 #define CPU_ITM_TCR_ATBID_M 0x007F0000
998 #define CPU_ITM_TCR_ATBID_S 16
999 
1000 // Field: [9:8] TSPRESCALE
1001 //
1002 // Timestamp prescaler
1003 // ENUMs:
1004 // DIV64 Divide by 64
1005 // DIV16 Divide by 16
1006 // DIV4 Divide by 4
1007 // NOPRESCALING No prescaling
1008 #define CPU_ITM_TCR_TSPRESCALE_W 2
1009 #define CPU_ITM_TCR_TSPRESCALE_M 0x00000300
1010 #define CPU_ITM_TCR_TSPRESCALE_S 8
1011 #define CPU_ITM_TCR_TSPRESCALE_DIV64 0x00000300
1012 #define CPU_ITM_TCR_TSPRESCALE_DIV16 0x00000200
1013 #define CPU_ITM_TCR_TSPRESCALE_DIV4 0x00000100
1014 #define CPU_ITM_TCR_TSPRESCALE_NOPRESCALING 0x00000000
1015 
1016 // Field: [4] SWOENA
1017 //
1018 // Enables asynchronous clocking of the timestamp counter (when TSENA = 1). If
1019 // TSENA = 0, writing this bit to 1 does not enable asynchronous clocking of
1020 // the timestamp counter.
1021 //
1022 // 0x0: Mode disabled. Timestamp counter uses system clock from the core and
1023 // counts continuously.
1024 // 0x1: Timestamp counter uses lineout (data related) clock from TPIU
1025 // interface. The timestamp counter is held in reset while the output line is
1026 // idle.
1027 #define CPU_ITM_TCR_SWOENA 0x00000010
1028 #define CPU_ITM_TCR_SWOENA_BITN 4
1029 #define CPU_ITM_TCR_SWOENA_M 0x00000010
1030 #define CPU_ITM_TCR_SWOENA_S 4
1031 
1032 // Field: [3] DWTENA
1033 //
1034 // Enables the DWT stimulus (hardware event packet emission to the TPIU from
1035 // the DWT)
1036 #define CPU_ITM_TCR_DWTENA 0x00000008
1037 #define CPU_ITM_TCR_DWTENA_BITN 3
1038 #define CPU_ITM_TCR_DWTENA_M 0x00000008
1039 #define CPU_ITM_TCR_DWTENA_S 3
1040 
1041 // Field: [2] SYNCENA
1042 //
1043 // Enables synchronization packet transmission for a synchronous TPIU.
1044 // CPU_DWT:CTRL.SYNCTAP must be configured for the correct synchronization
1045 // speed.
1046 #define CPU_ITM_TCR_SYNCENA 0x00000004
1047 #define CPU_ITM_TCR_SYNCENA_BITN 2
1048 #define CPU_ITM_TCR_SYNCENA_M 0x00000004
1049 #define CPU_ITM_TCR_SYNCENA_S 2
1050 
1051 // Field: [1] TSENA
1052 //
1053 // Enables differential timestamps. Differential timestamps are emitted when a
1054 // packet is written to the FIFO with a non-zero timestamp counter, and when
1055 // the timestamp counter overflows. Timestamps are emitted during idle times
1056 // after a fixed number of two million cycles. This provides a time reference
1057 // for packets and inter-packet gaps. If SWOENA (bit [4]) is set, timestamps
1058 // are triggered by activity on the internal trace bus only. In this case there
1059 // is no regular timestamp output when the ITM is idle.
1060 #define CPU_ITM_TCR_TSENA 0x00000002
1061 #define CPU_ITM_TCR_TSENA_BITN 1
1062 #define CPU_ITM_TCR_TSENA_M 0x00000002
1063 #define CPU_ITM_TCR_TSENA_S 1
1064 
1065 // Field: [0] ITMENA
1066 //
1067 // Enables ITM. This is the master enable, and must be set before ITM Stimulus
1068 // and Trace Enable registers can be written.
1069 #define CPU_ITM_TCR_ITMENA 0x00000001
1070 #define CPU_ITM_TCR_ITMENA_BITN 0
1071 #define CPU_ITM_TCR_ITMENA_M 0x00000001
1072 #define CPU_ITM_TCR_ITMENA_S 0
1073 
1074 //*****************************************************************************
1075 //
1076 // Register: CPU_ITM_O_LAR
1077 //
1078 //*****************************************************************************
1079 // Field: [31:0] LOCK_ACCESS
1080 //
1081 // A privileged write of 0xC5ACCE55 enables more write access to Control
1082 // Registers TER, TPR and TCR. An invalid write removes write access.
1083 #define CPU_ITM_LAR_LOCK_ACCESS_W 32
1084 #define CPU_ITM_LAR_LOCK_ACCESS_M 0xFFFFFFFF
1085 #define CPU_ITM_LAR_LOCK_ACCESS_S 0
1086 
1087 //*****************************************************************************
1088 //
1089 // Register: CPU_ITM_O_LSR
1090 //
1091 //*****************************************************************************
1092 // Field: [2] BYTEACC
1093 //
1094 // Reads 0 which means 8-bit lock access is not be implemented.
1095 #define CPU_ITM_LSR_BYTEACC 0x00000004
1096 #define CPU_ITM_LSR_BYTEACC_BITN 2
1097 #define CPU_ITM_LSR_BYTEACC_M 0x00000004
1098 #define CPU_ITM_LSR_BYTEACC_S 2
1099 
1100 // Field: [1] ACCESS
1101 //
1102 // Write access to component is blocked. All writes are ignored, reads are
1103 // permitted.
1104 #define CPU_ITM_LSR_ACCESS 0x00000002
1105 #define CPU_ITM_LSR_ACCESS_BITN 1
1106 #define CPU_ITM_LSR_ACCESS_M 0x00000002
1107 #define CPU_ITM_LSR_ACCESS_S 1
1108 
1109 // Field: [0] PRESENT
1110 //
1111 // Indicates that a lock mechanism exists for this component.
1112 #define CPU_ITM_LSR_PRESENT 0x00000001
1113 #define CPU_ITM_LSR_PRESENT_BITN 0
1114 #define CPU_ITM_LSR_PRESENT_M 0x00000001
1115 #define CPU_ITM_LSR_PRESENT_S 0
1116 
1117 #endif // __CPU_ITM__
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