TCAN455X_reg.h
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32 /*!*****************************************************************************
33  * @file TCAN455X_reg.h
34  * @brief TCAN455X device-specific register definitions
35  *******************************************************************************
36  */
37 
38 #ifndef __TCAN455X_REG_H__
39 #define __TCAN455X_REG_H__
40 
41 /******************************************************************************/
42 /* Device ID and Interrupt/Diagnostic Flag Register Addresses */
43 /******************************************************************************/
44 #define TCAN455X_DEVICE_ID0 0x0000
45 #define TCAN455X_DEVICE_ID1 0x0004
46 #define TCAN455X_REVISION 0x0008
47 #define TCAN455X_STATUS 0x000C
48 
49 /******************************************************************************/
50 /* Device Configuration Register Addresses */
51 /******************************************************************************/
52 #define TCAN455X_MODE 0x0800
53 #define TCAN455X_TS_PRESCALER 0x0804
54 #define TCAN455X_TEST 0x0808
55 #define TCAN455X_IR 0x0820
56 #define TCAN455X_IE 0x0830
57 
58 /******************************************************************************/
59 /* MCAN and MRAM Register Address */
60 /******************************************************************************/
61 #define TCAN455X_MCAN 0x1000U
62 #define TCAN455X_MRAM 0x8000U
63 
64 /******************************************************************************/
65 /* Device Register Bit Field Defines */
66 /******************************************************************************/
67 
68 /* Modes of Operation and Pin Configuration Registers (0x0800) */
69 
71 #define TCAN455X_MODE_FORCED_SET_BITS 0x00000020
72 
73 /* Wake pin */
74 #define TCAN455X_MODE_WAKE_PIN_MASK 0xC0000000
75 #define TCAN455X_MODE_WAKE_PIN_DIS 0x00000000
76 #define TCAN455X_MODE_WAKE_PIN_RISING 0x40000000
77 #define TCAN455X_MODE_WAKE_PIN_FALLING 0x80000000
78 #define TCAN455X_MODE_WAKE_PIN_BOTHEDGES 0xC0000000
79 
80 /* GPO2 Pin Configuration */
81 #define TCAN455X_MODE_GPO2_MASK 0x00C00000
82 #define TCAN455X_MODE_GPO2_CAN_FAULT 0x00000000
83 #define TCAN455X_MODE_GPO2_MCAN_INT0 0x00400000
84 #define TCAN455X_MODE_GPO2_WDT 0x00800000
85 #define TCAN455X_MODE_GPO2_NINT 0x00C00000
86 
87 /* Test Mode Enable Bit */
88 #define TCAN455X_MODE_TESTMODE_ENMASK 0x00200000
89 #define TCAN455X_MODE_TESTMODE_EN 0x00200000
90 #define TCAN455X_MODE_TESTMODE_DIS 0x00000000
91 
92 /* nWKRQ Pin GPO Voltage Rail COnfiguration */
93 #define TCAN455X_MODE_NWKRQ_VOLT_MASK 0x00080000
94 #define TCAN455X_MODE_NWKRQ_VOLT_INTERNAL 0x00000000
95 #define TCAN455X_MODE_NWKRQ_VOLT_VIO 0x00080000
96 
97 /* WD_BIT */
98 #define TCAN455X_MODE_WDT_RESET_BIT 0x00040000
99 
100 /* WD_ACTION */
101 #define TCAN455X_MODE_WDT_ACTION_MASK 0x00020000
102 #define TCAN455X_MODE_WDT_ACTION_INT 0x00000000
103 #define TCAN455X_MODE_WDT_ACTION_INH_PULSE 0x00010000
104 #define TCAN455X_MODE_WDT_ACTION_WDT_PULSE 0x00020000
105 
106 /* CLKOUT/GPO1 Pin Mode Select */
107 #define TCAN455X_MODE_GPO1_MODE_MASK 0x0000C000
108 #define TCAN455X_MODE_GPO1_MODE_GPO 0x00000000
109 #define TCAN455X_MODE_GPO1_MODE_CLKOUT 0x00004000
110 #define TCAN455X_MODE_GPO1_MODE_GPI 0x00008000
111 
112 /* Fail Safe Enable */
113 #define TCAN455X_MODE_FAIL_SAFE_MASK 0x00002000
114 #define TCAN455X_MODE_FAIL_SAFE_EN 0x00002000
115 #define TCAN455X_MODE_FAIL_SAFE_DIS 0x00000000
116 
117 /* CLKOUT Prescaler */
118 #define TCAN455X_MODE_CLKOUT_MASK 0x00001000
119 #define TCAN455X_MODE_CLKOUT_DIV1 0x00000000
120 #define TCAN455X_MODE_CLKOUT_DIV2 0x00001000
121 
122 /* GPO1 Function Select */
123 #define TCAN455X_MODE_GPO1_FUNC_MASK 0x00000C00
124 #define TCAN455X_MODE_GPO1_FUNC_SPI_INT 0x00000000
125 #define TCAN455X_MODE_GPO1_FUNC_MCAN_INT1 0x00000400
126 #define TCAN455X_MODE_GPO1_FUNC_UVLO_THERM 0x00000800
127 
128 /* INH Pin Disable */
129 #define TCAN455X_MODE_INH_MASK 0x00000200
130 #define TCAN455X_MODE_INH_DIS 0x00000200
131 #define TCAN455X_MODE_INH_EN 0x00000000
132 
133 /* nWKRQ Pin Configuration */
134 #define TCAN455X_MODE_NWKRQ_CONFIG_MASK 0x00000100
135 #define TCAN455X_MODE_NWKRQ_CONFIG_INH 0x00000000
136 #define TCAN455X_MODE_NWKRQ_CONFIG_WKRQ 0x00000100
137 
138 /* Mode of Operation */
139 #define TCAN455X_MODE_OPMODE_MASK 0x000000C0
140 #define TCAN455X_MODE_OPMODE_SLEEP 0x00000000
141 #define TCAN455X_MODE_OPMODE_STANDBY 0x00000040
142 #define TCAN455X_MODE_OPMODE_NORMAL 0x00000080
143 
144 /* WDT_EN */
145 #define TCAN455X_MODE_WDT_MASK 0x00000008
146 #define TCAN455X_MODE_WDT_EN 0x00000008
147 #define TCAN455X_MODE_WDT_DIS 0x00000000
148 
149 /* Dev Reset */
150 #define TCAN455X_MODE_RESET 0x00000004
151 
152 /* SWE_DIS: Sleep Wake Error Disable */
153 #define TCAN455X_MODE_SWE_MASK 0x00000002
154 #define TCAN455X_MODE_SWE_DIS 0x00000002
155 #define TCAN455X_MODE_SWE_EN 0x00000000
156 
157 /* Test Mode Configuration */
158 #define TCAN455X_MODE_TESTMODE_MASK 0x00000001
159 #define TCAN455X_MODE_TESTMODE_PHY 0x00000000
160 #define TCAN455X_MODE_TESTMODE_CONTROLLER 0x00000001
161 
162 /* Device Interrupt Register values (0x0820) */
163 #define TCAN455X_IR_CANLGND 0x08000000
164 #define TCAN455X_IR_CANBUSOPEN 0x04000000
165 #define TCAN455X_IR_CANBUSGND 0x02000000
166 #define TCAN455X_IR_CANBUSBAT 0x01000000
167 #define TCAN455X_IR_RSVD3 0x00800000
168 #define TCAN455X_IR_UVSUP 0x00400000
169 #define TCAN455X_IR_UVIO 0x00200000
170 #define TCAN455X_IR_PWRON 0x00100000
171 #define TCAN455X_IR_TSD 0x00080000
172 #define TCAN455X_IR_WDTO 0x00040000
173 #define TCAN455X_IR_RSVD2 0x00020000
174 #define TCAN455X_IR_ECCERR 0x00010000
175 #define TCAN455X_IR_CANINT 0x00008000
176 #define TCAN455X_IR_LWU 0x00004000
177 #define TCAN455X_IR_WKERR 0x00002000
178 #define TCAN455X_IR_FRAME_OVF 0x00001000
179 #define TCAN455X_IR_RSVD1 0x00000800
180 #define TCAN455X_IR_CANSLNT 0x00000400
181 #define TCAN455X_IR_RSVD0 0x00000200
182 #define TCAN455X_IR_CANDOM 0x00000100
183 #define TCAN455X_IR_GLOBALERR 0x00000080
184 #define TCAN455X_IR_nWKRQ 0x00000040
185 #define TCAN455X_IR_CANERR 0x00000020
186 #define TCAN455X_IR_CANBUSFAULT 0x00000010
187 #define TCAN455X_IR_SPIERR 0x00000008
188 #define TCAN455X_IR_SWERR 0x00000004
189 #define TCAN455X_IR_M_CAN_INT 0x00000002
190 #define TCAN455X_IR_VTWD 0x00000001
191 
192 /* Device Interrupt Enable Values (0x0830) */
193 #define TCAN455X_IE_UVCCOUT 0x00800000
194 #define TCAN455X_IE_UVSUP 0x00400000
195 #define TCAN455X_IE_UVIO 0x00200000
196 #define TCAN455X_IE_PWRON 0x00100000
197 #define TCAN455X_IE_TSD 0x00080000
198 #define TCAN455X_IE_WDTO 0x00040000
199 #define TCAN455X_IE_RSVD2 0x00020000
200 #define TCAN455X_IE_ECCERR 0x00010000
201 #define TCAN455X_IE_CANINT 0x00008000
202 #define TCAN455X_IE_LWU 0x00004000
203 #define TCAN455X_IE_WKERR 0x00002000
204 #define TCAN455X_IE_FRAME_OVF 0x00001000
205 #define TCAN455X_IE_RSVD1 0x00000800
206 #define TCAN455X_IE_CANSLNT 0x00000400
207 #define TCAN455X_IE_RSVD0 0x00000200
208 #define TCAN455X_IE_CANDOM 0x00000100
209 #define TCAN455X_IE_MASK 0xFF69D700
210 
211 #endif /* __TCAN455X_REG_H__ */
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