PowerCC27XX.h

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/*
 * Copyright (c) 2022-2024, Texas Instruments Incorporated
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * *  Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *
 * *  Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * *  Neither the name of Texas Instruments Incorporated nor the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
#ifndef ti_drivers_power_PowerCC27XX_
#define ti_drivers_power_PowerCC27XX_

#include <ti/drivers/dpl/HwiP.h>
#include <ti/drivers/dpl/ClockP.h>
#include <ti/drivers/Power.h>

#include <ti/devices/DeviceFamily.h>
#include DeviceFamily_constructPath(inc/hw_pmctl.h)
#include DeviceFamily_constructPath(inc/hw_clkctl.h)
#include DeviceFamily_constructPath(inc/hw_lrfddbell.h)
#include DeviceFamily_constructPath(inc/hw_memmap.h)
#include DeviceFamily_constructPath(inc/hw_types.h)
#include DeviceFamily_constructPath(driverlib/pmctl.h)

#ifdef __cplusplus
extern "C" {
#endif

#define PowerCC27XX_RESUMETIMESTANDBY 400

#define PowerCC27XX_TOTALTIMESTANDBY 1000

#define PowerCC27XX_WAKEDELAYSTANDBY 500

/* \cond */
/* The control of the peripherals are split between multiple groups.
 * These defines are used to differentiate between the groups.
 * The bits in the PowerCC27XX_PERIPH_GROUP_M mask is used to store the group id,
 * and the bits in the PowerCC27XX_PERIPH_BIT_INDEX_M mask is used to store the
 * bit index shift value in the register for the given group.
 */
#define PowerCC27XX_PERIPH_GROUP_M       0xFF00
#define PowerCC27XX_PERIPH_GROUP_CLKCTL0 0x0000
#define PowerCC27XX_PERIPH_GROUP_CLKCTL1 0x0100
#define PowerCC27XX_PERIPH_GROUP_LRFD    0x0200
#define PowerCC27XX_PERIPH_BIT_INDEX_M   0x00FF

/* \endcond */

/* \cond */
typedef uint16_t PowerLPF3_Resource; /* Power resource identifier */
/* \endcond */

/* Resource IDs */

#define PowerLPF3_PERIPH_GPIO (PowerCC27XX_PERIPH_GROUP_CLKCTL0 | CLKCTL_DESCEX0_GPIO_S)

#define PowerLPF3_PERIPH_UART0 (PowerCC27XX_PERIPH_GROUP_CLKCTL0 | CLKCTL_DESCEX0_UART0_S)

#define PowerLPF3_PERIPH_UART1 (PowerCC27XX_PERIPH_GROUP_CLKCTL0 | CLKCTL_DESCEX0_UART1_S)

#define PowerLPF3_PERIPH_I2C0 (PowerCC27XX_PERIPH_GROUP_CLKCTL0 | CLKCTL_DESCEX0_I2C0_S)

#define PowerLPF3_PERIPH_SPI0 (PowerCC27XX_PERIPH_GROUP_CLKCTL0 | CLKCTL_DESCEX0_SPI0_S)

#define PowerLPF3_PERIPH_SPI1 (PowerCC27XX_PERIPH_GROUP_CLKCTL0 | CLKCTL_DESCEX0_SPI1_S)

#define PowerLPF3_PERIPH_ADC0 (PowerCC27XX_PERIPH_GROUP_CLKCTL0 | CLKCTL_DESCEX0_ADC0_S)

#define PowerLPF3_PERIPH_AES (PowerCC27XX_PERIPH_GROUP_CLKCTL0 | CLKCTL_DESCEX0_LAES_S)

#define PowerLPF3_PERIPH_DMA (PowerCC27XX_PERIPH_GROUP_CLKCTL0 | CLKCTL_DESCEX0_DMA_S)

#define PowerLPF3_PERIPH_I2S (PowerCC27XX_PERIPH_GROUP_CLKCTL0 | CLKCTL_DESCEX0_I2S_S)

#define PowerLPF3_PERIPH_LGPT0 (PowerCC27XX_PERIPH_GROUP_CLKCTL0 | CLKCTL_DESCEX0_LGPT0_S)

#define PowerLPF3_PERIPH_LGPT1 (PowerCC27XX_PERIPH_GROUP_CLKCTL0 | CLKCTL_DESCEX0_LGPT1_S)

#define PowerLPF3_PERIPH_LGPT2 (PowerCC27XX_PERIPH_GROUP_CLKCTL0 | CLKCTL_DESCEX0_LGPT2_S)

#define PowerLPF3_PERIPH_LGPT3 (PowerCC27XX_PERIPH_GROUP_CLKCTL0 | CLKCTL_DESCEX0_LGPT3_S)

#define PowerLPF3_PERIPH_HSM (PowerCC27XX_PERIPH_GROUP_CLKCTL1 | CLKCTL_DESCEX1_HSM_S)

#define PowerLPF3_PERIPH_VCE (PowerCC27XX_PERIPH_GROUP_CLKCTL1 | CLKCTL_DESCEX1_VCE_S)

#define PowerLPF3_PERIPH_MCAN (PowerCC27XX_PERIPH_GROUP_CLKCTL1 | CLKCTL_DESCEX1_MCAN_S)

#define PowerLPF3_PERIPH_LFRD_TRC (PowerCC27XX_PERIPH_GROUP_LRFD | LRFDDBELL_CLKCTL_TRC_S)

#define PowerLPF3_PERIPH_LFRD_S2RRAM (PowerCC27XX_PERIPH_GROUP_LRFD | LRFDDBELL_CLKCTL_S2RRAM_S)

/* \cond */
/* Number of resources in the different resource groups. This is possibly larger
 * than the peripheral instance count on various device variants. This is
 * because some indexes might not be used for a given variant, resulting in a
 * sparse table.
 */
#define PowerCC27XX_NUMRESOURCES_CLKCTL0 31
#define PowerCC27XX_NUMRESOURCES_CLKCTL1 7
#define PowerCC27XX_NUMRESOURCES_LRFD    12

/* \endcond */

#define PowerLPF3_STANDBY 0x1 
/* \cond */
/* Internal flags for enabling/disabling resources */
#define PowerLPF3_ENABLE  1
#define PowerLPF3_DISABLE 0
/* \endcond */

/* Constraints
 *
 * Constraints restrict a specific system behavior from occurring or guarantee
 * a specified effect until released.
 */

#define PowerLPF3_DISALLOW_SHUTDOWN 0

#define PowerLPF3_DISALLOW_STANDBY 1

#define PowerLPF3_DISALLOW_IDLE 2

#define PowerLPF3_NEED_FLASH_IN_IDLE 3

/* \cond */
#define PowerCC27XX_NUMCONSTRAINTS 4 /* Number of constraints supported */
/* \endcond */

/*
 *  Events
 *
 *  Each event must be a power of two and must be sequential
 *  without any gaps.
 */

#define PowerLPF3_ENTERING_STANDBY (1 << 0)

#define PowerLPF3_ENTERING_SHUTDOWN (1 << 1)

#define PowerLPF3_AWAKE_STANDBY (1 << 2)

#define PowerLPF3_HFXT_AVAILABLE (1 << 3)

#define PowerLPF3_LFCLK_SWITCHED (1 << 4)

/* \cond */
#define PowerCC27XX_NUMEVENTS 5 /* Number of events supported */
/* \endcond */

typedef void (*PowerLPF3_StartInitialHfxtAmpCompFxn)(void);

typedef struct
{
    Power_PolicyInitFxn policyInitFxn;
    Power_PolicyFxn policyFxn;

    PowerLPF3_StartInitialHfxtAmpCompFxn startInitialHfxtAmpCompFxn;
} PowerCC27XX_Config;

typedef enum
{
    PowerLPF3_RESET_SHUTDOWN_IO  = PMCTL_RESET_SHUTDOWN_IO,
    PowerLPF3_RESET_SHUTDOWN_SWD = PMCTL_RESET_SHUTDOWN_SWD,
    PowerLPF3_RESET_WATCHDOG     = PMCTL_RESET_WATCHDOG,
    PowerLPF3_RESET_SYSTEM       = PMCTL_RESET_SYSTEM,
    PowerLPF3_RESET_CPU          = PMCTL_RESET_CPU,
    PowerLPF3_RESET_LOCKUP       = PMCTL_RESET_LOCKUP,
    PowerLPF3_RESET_TSD          = PMCTL_RESET_TSD,
    PowerLPF3_RESET_SWD          = PMCTL_RESET_SWD,
    PowerLPF3_RESET_LFXT         = PMCTL_RESET_LFXT,
    PowerLPF3_RESET_VDDR         = PMCTL_RESET_VDDR,
    PowerLPF3_RESET_VDDS         = PMCTL_RESET_VDDS,
    PowerLPF3_RESET_PIN          = PMCTL_RESET_PIN,
    PowerLPF3_RESET_POR          = PMCTL_RESET_POR,
} PowerLPF3_ResetReason;

typedef enum
{
    PowerLPF3_AFOSC_FREQ_80MHZ      = 80000000, 
    PowerLPF3_AFOSC_FREQ_90P3168MHZ = 90316800, 
    PowerLPF3_AFOSC_FREQ_98P304MHZ  = 98304000, 
} PowerLPF3_AfoscFreq;

typedef enum
{
    PowerLPF3_LFOSC_PPM_500 = 500,
} PowerLPF3_LfoscCompensationPpmRequirement;

typedef struct
{
    uint32_t systemWakeupIntervalUsec;

    PowerLPF3_LfoscCompensationPpmRequirement ppmRequirement;

    uint16_t temperatureGradientMilliCelsiusPerSec;

} PowerLPF3_LfoscCompensationProfile;

void PowerCC27XX_doWFI(void);

static inline PowerLPF3_ResetReason PowerLPF3_getResetReason(void)
{
    return (PowerLPF3_ResetReason)PMCTLGetResetReason();
}

static inline void PowerLPF3_releaseLatches(void)
{
    HWREG(PMCTL_BASE + PMCTL_O_SLPCTL) = PMCTL_SLPCTL_SLPN_DIS;
}

void PowerCC27XX_standbyPolicy(void);

void PowerLPF3_selectLFOSC(void);

void PowerLPF3_selectLFXT(void);

void PowerLPF3_selectEXTLF(void);

int_fast16_t PowerLPF3_startAFOSC(PowerLPF3_AfoscFreq frequency);

void PowerLPF3_stopAFOSC(void);

void PowerLPF3_startInitialHfxtAmpComp(void);

int_fast8_t PowerLPF3_getHfxtAmpAdjustment(void);

void PowerLPF3_adjustHfxtAmp(int_fast8_t adjustment);

void PowerLPF3_initLfoscCompensation(void);

void PowerLPF3_setLfoscCompensationProfile(const PowerLPF3_LfoscCompensationProfile *profile);

void PowerLPF3_enableLfoscCompensation(void);

void PowerLPF3_disableLfoscCompensation(void);

void PowerCC27XX_schedulerDisable(void);
void PowerCC27XX_schedulerRestore(void);

#ifdef __cplusplus
}
#endif

#endif /* POWER_CC27XX_ */