Instance: SCSCS
Component: SCSCS
Base address: 0xE000EFC0
|
Register Name |
Type |
Register Width (Bits) |
Register Reset |
Address Offset |
Physical Address |
|
32 |
0x0000 0004 |
0x0000 0010 |
0xE000 EFD0 |
||
|
32 |
0x0000 0000 |
0x0000 0014 |
0xE000 EFD4 |
||
|
32 |
0x0000 0000 |
0x0000 0018 |
0xE000 EFD8 |
||
|
32 |
0x0000 0000 |
0x0000 001C |
0xE000 EFDC |
||
|
32 |
0x0000 0008 |
0x0000 0020 |
0xE000 EFE0 |
||
|
32 |
0x0000 00B0 |
0x0000 0024 |
0xE000 EFE4 |
||
|
32 |
0x0000 000B |
0x0000 0028 |
0xE000 EFE8 |
||
|
32 |
0x0000 0000 |
0x0000 002C |
0xE000 EFEC |
||
|
32 |
0x0000 000D |
0x0000 0030 |
0xE000 EFF0 |
||
|
32 |
0x0000 00E0 |
0x0000 0034 |
0xE000 EFF4 |
||
|
32 |
0x0000 0005 |
0x0000 0038 |
0xE000 EFF8 |
||
|
32 |
0x0000 00B1 |
0x0000 003C |
0xE000 EFFC |
| Address Offset | 0x0000 0010 | ||
| Physical Address | 0xE000 EFD0 | Instance | 0xE000 EFD0 |
| Description | Peripheral ID Register 4 Part of the set of Peripheral Identification registers. Contains part of the designer identity and the memory footprint indicator. |
||
| Type | |||
| Bits | Field Name | Description | Type | Reset | ||
| 31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 0000 | ||
| 7:4 | SIZE | This is a 4-bit value that indicates the total contiguous size of the memory window used by this component in powers of 2 from the standard 4KB. If a component only requires the standard 4KB then this should read as 0x0, 4KB only, for 8KB set to 0x1, 16KB == 0x2, 32KB == 0x3, and so on. | RO | 0x0 | ||
| 3:0 | DES_2 | Number of JEDEC continuation codes. Indicates the designer of the component (along with the identity code) | RO | 0x4 | ||
| Address Offset | 0x0000 0014 | ||
| Physical Address | 0xE000 EFD4 | Instance | 0xE000 EFD4 |
| Description | Peripheral ID Register 5 Reserved |
||
| Type | |||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | RESERVED0 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0000 0000 | ||
| Address Offset | 0x0000 0018 | ||
| Physical Address | 0xE000 EFD8 | Instance | 0xE000 EFD8 |
| Description | Peripheral ID Register 6 Reserved |
||
| Type | |||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | RESERVED0 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0000 0000 | ||
| Address Offset | 0x0000 001C | ||
| Physical Address | 0xE000 EFDC | Instance | 0xE000 EFDC |
| Description | Peripheral ID Register 7 Reserved |
||
| Type | |||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | RESERVED0 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0000 0000 | ||
| Address Offset | 0x0000 0020 | ||
| Physical Address | 0xE000 EFE0 | Instance | 0xE000 EFE0 |
| Description | Peripheral ID Register 0 Part of the set of Peripheral Identification registers. Contains part of the designer specific part number. |
||
| Type | |||
| Bits | Field Name | Description | Type | Reset | ||
| 31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 0000 | ||
| 7:0 | PART_0 | Bits [7:0] of the component's part number. This is selected by the designer of the component. | RO | 0x08 | ||
| Address Offset | 0x0000 0024 | ||
| Physical Address | 0xE000 EFE4 | Instance | 0xE000 EFE4 |
| Description | Peripheral ID Register 1 Part of the set of Peripheral Identification registers. Contains part of the designer specific part number and part of the designer identity. |
||
| Type | |||
| Bits | Field Name | Description | Type | Reset | ||
| 31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 0000 | ||
| 7:4 | DES_0 | Bits [3:0] of the JEDEC identity code indicating the designer of the component (along with the continuation code) | RO | 0xB | ||
| 3:0 | PART_1 | Bits [11:8] of the component's part number. This is selected by the designer of the component. | RO | 0x0 | ||
| Address Offset | 0x0000 0028 | ||
| Physical Address | 0xE000 EFE8 | Instance | 0xE000 EFE8 |
| Description | Peripheral ID Register 2 Part of the set of Peripheral Identification registers. Contains part of the designer identity and the product revision. |
||
| Type | |||
| Bits | Field Name | Description | Type | Reset | ||
| 31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 0000 | ||
| 7:4 | REVISION | The Revision field is an incremental value starting at 0x0 for the first design of this component. This only increases by 1 for both major and minor revisions and is simply used as a look-up to establish the exact major/minor revision. | RO | 0x0 | ||
| 3 | JEDEC | Always set. Indicates that a JEDEC assigned value is used | RO | 1 | ||
| 2:0 | DES_1 | Bits [6:4] of the JEDEC identity code indicating the designer of the component (along with the continuation code) | RO | 0b011 | ||
| Address Offset | 0x0000 002C | ||
| Physical Address | 0xE000 EFEC | Instance | 0xE000 EFEC |
| Description | Peripheral ID Register 3 Part of the set of Peripheral Identification registers. Contains the RevAnd and Customer Modified fields. |
||
| Type | |||
| Bits | Field Name | Description | Type | Reset | ||
| 31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 0000 | ||
| 7:4 | REVAND | This field indicates minor errata fixes specific to this design, for example metal fixes after implementation. In most cases this field is zero. It is recommended that component designers ensure this field can be changed by a metal fix if required, for example by driving it from registers that reset to zero. | RO | 0x0 | ||
| 3:0 | CMOD | Where the component is reusable IP, this value indicates if the customer has modified the behavior of the component. In most cases this field is zero. | RO | 0x0 | ||
| Address Offset | 0x0000 0030 | ||
| Physical Address | 0xE000 EFF0 | Instance | 0xE000 EFF0 |
| Description | Component ID Register 0 A component identification register, that indicates that the identification registers are present. |
||
| Type | |||
| Bits | Field Name | Description | Type | Reset | ||
| 31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 0000 | ||
| 7:0 | PRMBL_0 | Contains bits [7:0] of the component identification | RO | 0x0D | ||
| Address Offset | 0x0000 0034 | ||
| Physical Address | 0xE000 EFF4 | Instance | 0xE000 EFF4 |
| Description | Component ID Register 1 A component identification register, that indicates that the identification registers are present. This register also indicates the component class. |
||
| Type | |||
| Bits | Field Name | Description | Type | Reset | ||
| 31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 0000 | ||
| 7:4 | CLASS | Class of the component. E.g. ROM table, CoreSight component etc. Constitutes bits [15:12] of the component identification. | RO | 0xE | ||
| 3:0 | PRMBL_1 | Contains bits [11:8] of the component identification | RO | 0x0 | ||
| Address Offset | 0x0000 0038 | ||
| Physical Address | 0xE000 EFF8 | Instance | 0xE000 EFF8 |
| Description | Component ID Register 2 A component identification register, that indicates that the identification registers are present. |
||
| Type | |||
| Bits | Field Name | Description | Type | Reset | ||
| 31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 0000 | ||
| 7:0 | PRMBL_2 | Contains bits [23:16] of the component identification | RO | 0x05 | ||
| Address Offset | 0x0000 003C | ||
| Physical Address | 0xE000 EFFC | Instance | 0xE000 EFFC |
| Description | Component ID Register 3 A component identification register, that indicates that the identification registers are present. |
||
| Type | |||
| Bits | Field Name | Description | Type | Reset | ||
| 31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 0000 | ||
| 7:0 | PRMBL_3 | Contains bits [31:24] of the component identification | RO | 0xB1 | ||
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