Instance: SCB
Component: SCB
Base address: 0xE000ED00
|
Register Name |
Type |
Register Width (Bits) |
Register Reset |
Address Offset |
Physical Address |
|
32 |
0x410C C601 |
0x0000 0000 |
0xE000 ED00 |
||
|
32 |
0x0000 0000 |
0x0000 0004 |
0xE000 ED04 |
||
|
32 |
0x0000 0000 |
0x0000 0008 |
0xE000 ED08 |
||
|
32 |
0xFA05 8000 |
0x0000 000C |
0xE000 ED0C |
||
|
32 |
0x0000 0000 |
0x0000 0010 |
0xE000 ED10 |
||
|
32 |
0x0000 0208 |
0x0000 0014 |
0xE000 ED14 |
||
|
32 |
0x0000 0000 |
0x0000 001C |
0xE000 ED1C |
||
|
32 |
0x0000 0000 |
0x0000 0020 |
0xE000 ED20 |
||
|
32 |
0x0000 0000 |
0x0000 0024 |
0xE000 ED24 |
| Address Offset | 0x0000 0000 | ||
| Physical Address | 0xE000 ED00 | Instance | 0xE000 ED00 |
| Description | CPUID Base Register Read the CPU ID Base Register to determine: the ID number of the processor core, the version number of the processor core, the implementation details of the processor core. |
||
| Type | |||
| Bits | Field Name | Description | Type | Reset | ||
| 31:24 | IMPLEMENTER | Implementor code: 0x41 = ARM | RO | 0x41 | ||
| 23:20 | VARIANT | Implementation defined variant number: 0x0 (for r0) | RO | 0x0 | ||
| 19:16 | CONSTANT | Reads as 0xC | RO | 0xC | ||
| 15:4 | PARTNO | Number of processor within family: 0xC20 | RO | 0xC60 | ||
| 3:0 | REVISION | Implementation defined revision number: 0x1 = processor p1 revision. | RO | 0x1 | ||
| Address Offset | 0x0000 0004 | ||
| Physical Address | 0xE000 ED04 | Instance | 0xE000 ED04 |
| Description | Interrupt Control State Register Use the Interrupt Control State Register to set a pending Non-Maskable Interrupt (NMI), set or clear a pending PendSV, set or clear a pending SysTick, check for pending exceptions, check the vector number of the highest priority pended exception, check the vector number of the active exception. |
||
| Type | |||
| Bits | Field Name | Description | Type | Reset | ||
| 31 | NMIPENDSET | Setting this bit will activate an NMI. Since NMI is the highest priority exception, it will activate as soon as it is registered. Reads back with current state (1 if Pending, 0 if not). 0x0:No effect 0x1:Set pending nmi |
RW | 0 | ||
| 30:29 | RESERVED29 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 | ||
| 28 | PENDSVSET | Set pending PendSV bit. On reads this bit returns the pending state of PendSV 0x0:No effect 0x1:Set pending pendsv |
RW | 0 | ||
| 27 | PENDSVCLR | Clear pending PendSV bit 0x0:No effect 0x1:Clear pending pendsv |
WO | 0 | ||
| 26 | PENDSTSET | Set a pending SysTick bit. On reads this bit returns the pending state of SysTick. 0x0:No effect 0x1:Set pending systick |
RW | 0 | ||
| 25 | PENDSTCLR | Clear pending SysTick bit 0x0:No effect 0x1:Clear pending systick |
WO | 0 | ||
| 24 | RESERVED24 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0 | ||
| 23 | ISRPREEMPT | The system can only access this bit when the core is halted. It indicates that a pending interrupt is to be taken in the next running cycle. If C_MASKINTS is clear in the Debug Halting Control and Status Register, the interrupt is serviced. 0x0:A pending exception is not serviced. 0x1:A pending exception is serviced on exit from the debug halt state |
RO | 0 | ||
| 22 | ISRPENDING | External interrupt pending flag 0x0:Interrupt not pending 0x1:Interrupt pending |
RO | 0 | ||
| 21 | RESERVED21 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0 | ||
| 20:12 | VECTPENDING | Indicates the exception number for the highest priority pending exception: 0 = no pending exceptions. Non zero = The pending state includes the effect of memory-mapped enable and mask registers. It does not include the PRIMASK special-purpose register qualifier. | RO | 0b0 0000 0000 | ||
| 11:9 | RESERVED9 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 | ||
| 8:0 | VECTACTIVE | Active exception number field. Reset clears the VECTACTIVE field. | RO | 0b0 0000 0000 | ||
| Address Offset | 0x0000 0008 | ||
| Physical Address | 0xE000 ED08 | Instance | 0xE000 ED08 |
| Description | Vector Table Offset Register The VTOR holds the vector table offset address. |
||
| Type | |||
| Bits | Field Name | Description | Type | Reset | ||
| 31:8 | TBLOFF | Bits [31:8] of the indicate the vector table offset address. | RW | 0x00 0000 | ||
| 7:0 | RESERVED0 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 | ||
| Address Offset | 0x0000 000C | ||
| Physical Address | 0xE000 ED0C | Instance | 0xE000 ED0C |
| Description | Application Interrupt and Reset Control Register Use the Application Interrupt and Reset Control Register to: determine data endianness, clear all active state information from debug halt mode, request a system reset. |
||
| Type | |||
| Bits | Field Name | Description | Type | Reset | ||
| 31:16 | VECTKEY | Register key. To write to other parts of this register, you must ensure 0x5FA is written into the VECTKEY field. | WO | 0xFA05 | ||
| 15 | ENDIANESS | Data endianness bit. The read value depends on the endian configuration implemented 0x0:Little endian 0x1:Be-8 big-endian |
RO | 1 | ||
| 14:3 | RESERVED3 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x000 | ||
| 2 | SYSRESETREQ | Writing 1 to this bit causes the SYSRESETREQ signal to the outer system to be asserted to request a reset. The intention is to force a large system reset of all major components except for debug. The C_HALT bit in the DHCSR is cleared as a result of the system reset requested. The debugger does not lose contact with the device. | WO | 0 | ||
| 1 | VECTCLRACTIVE | Clears all active state information for fixed and configurable exceptions. This bit: is self-clearing, can only be set by the DAP when the core is halted. When set: clears all active exception status of the processor, forces a return to Thread mode, forces an IPSR of 0. A debugger must re-initialize the stack. | WO | 0 | ||
| 0 | RESERVED0 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0 | ||
| Address Offset | 0x0000 0010 | ||
| Physical Address | 0xE000 ED10 | Instance | 0xE000 ED10 |
| Description | System Control Register System Control Register. Use the System Control Register for power-management functions: signal to the system when the processor can enter a low power state, control how the processor enters and exits low power states. |
||
| Type | |||
| Bits | Field Name | Description | Type | Reset | |||||||||||
| 31:5 | RESERVED5 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 0000 | |||||||||||
| 4 | SEVONPEND | When enabled, this causes WFE to wake up when an interrupt moves from inactive to pended. Otherwise, WFE only wakes up from an event signal, external and SEV instruction generated. The event input, RXEV, is registered even when not waiting for an event, and so effects the next WFE. | RW | 0 | |||||||||||
| 3 | RESERVED3 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0 | |||||||||||
| 2 | SLEEPDEEP | Sleep deep bit.
|
RW | 0 | |||||||||||
| 1 | SLEEPONEXIT | Sleep on exit when returning from Handler mode to Thread mode. Enables interrupt driven applications to avoid returning to empty main application.
|
RW | 0 | |||||||||||
| 0 | RESERVED0 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0 | |||||||||||
| Address Offset | 0x0000 0014 | ||
| Physical Address | 0xE000 ED14 | Instance | 0xE000 ED14 |
| Description | Configuration and Control Register The Configuration and Control Register permanently enables stack alignment and causes unaligned accesses to result in a Hard Fault. |
||
| Type | |||
| Bits | Field Name | Description | Type | Reset | ||
| 31:10 | RESERVED10 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 0000 0000 0000 0000 | ||
| 9 | STKALIGN | Always set to 1. On exception entry, all exceptions are entered with 8-byte stack alignment and the context to restore it is saved. The SP is restored on the associated exception return. | RO | 1 | ||
| 8:4 | RESERVED4 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 | ||
| 3 | UNALIGN_TRP | Indicates that all unaligned accesses results in a Hard Fault. Trap for unaligned access is fixed at 1. | RO | 1 | ||
| 2:0 | RESERVED0 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 | ||
| Address Offset | 0x0000 001C | ||
| Physical Address | 0xE000 ED1C | Instance | 0xE000 ED1C |
| Description | System Handler Priority Register 2 System handlers are a special class of exception handler that can have their priority set to any of the priority levels. Use the System Handler Priority Register 2 to set the priority of SVCall. |
||
| Type | |||
| Bits | Field Name | Description | Type | Reset | ||
| 31:30 | PRI_11 | Priority of system handler 11, SVCall | RW | 0b00 | ||
| 29:0 | RESERVED0 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 0000 0000 0000 0000 0000 0000 | ||
| Address Offset | 0x0000 0020 | ||
| Physical Address | 0xE000 ED20 | Instance | 0xE000 ED20 |
| Description | System Handler Priority Register 3 System handlers are a special class of exception handler that can have their priority set to any of the priority levels. Use the System Handler Priority Register 3 to set the priority of PendSV and SysTick. |
||
| Type | |||
| Bits | Field Name | Description | Type | Reset | ||
| 31:30 | PRI_15 | Priority of system handler 15, SysTick | RW | 0b00 | ||
| 29:24 | RESERVED24 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 | ||
| 23:22 | PRI_14 | Priority of system handler 14, PendSV | RW | 0b00 | ||
| 21:0 | RESERVED0 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 0000 0000 0000 0000 | ||
| Address Offset | 0x0000 0024 | ||
| Physical Address | 0xE000 ED24 | Instance | 0xE000 ED24 |
| Description | System Handler Control and State Register Use the System Handler Control and State Register to determine or clear the pending status of SVCall. |
||
| Type | |||
| Bits | Field Name | Description | Type | Reset | ||
| 31:16 | RESERVED16 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0000 | ||
| 15 | SVCALLPENDED | Reads as 1 if SVCall is Pending. Write 1 to set pending SVCall, write 0 to clear pending SVCall. | RW | 0 | ||
| 14:0 | RESERVED0 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 | ||
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