PMCTL

Instance: PMCTL
Component: PMCTL
Base address: 0x40000000


This component is the Power Management controller. Together with the System Controller, it controls system resets and the power states of the device.

TOP:PMCTL Register Summary

Register Name

Type

Register Width (Bits)

Register Reset

Address Offset

Physical Address

DESC

RO

32

0xD741 0010

0x0000 0000

0x4000 0000

DESCEX

RO

32

0xFC00 0000

0x0000 0004

0x4000 0004

SHTDWN

WO

32

0x0000 0000

0x0000 0008

0x4000 0008

SLPCTL

RW

32

0x0000 0000

0x0000 000C

0x4000 000C

WUSTA

RO

32

0x0000 0001

0x0000 0010

0x4000 0010

VDDRCTL

RW

32

0x0000 0000

0x0000 0014

0x4000 0014

SYSFSET

WO

32

0x0000 0000

0x0000 0020

0x4000 0020

SYSFCLR

WO

32

0x0000 0000

0x0000 0024

0x4000 0024

SYSFSTA

RO

32

0x0000 0000

0x0000 0028

0x4000 0028

RSTCTL

RW

32

0x0000 0000

0x0000 002C

0x4000 002C

RSTSTA

RO

32

0x0000 0000

0x0000 0030

0x4000 0030

BOOTSTA

RW

32

0x0000 0000

0x0000 0034

0x4000 0034

AONRSTA1

RO

32

0x0000 0000

0x0000 003C

0x4000 003C

AONRSET1

WO

32

0x0000 0000

0x0000 0040

0x4000 0040

AONRCLR1

WO

32

0x0000 0000

0x0000 0044

0x4000 0044

ETPP

RW

32

0x0000 0000

0x0000 0064

0x4000 0064

RETCFG0

RW

32

0x0000 0001

0x0000 007C

0x4000 007C

RETCFG1

RW

32

0x0000 0000

0x0000 0080

0x4000 0080

RETCFG2

RW

32

0x0000 0002

0x0000 0084

0x4000 0084

RETCFG3

RW

32

0x0000 0000

0x0000 0088

0x4000 0088

RETCFG4

RW

32

0x0000 0000

0x0000 008C

0x4000 008C

RETCFG5

RW

32

0x0000 0000

0x0000 0090

0x4000 0090

RETCFG6

RW

32

0x0000 0000

0x0000 0094

0x4000 0094

RETCFG7

RW

32

0x0000 0000

0x0000 0098

0x4000 0098

TOP:PMCTL Register Descriptions

TOP:PMCTL:DESC

Address Offset 0x0000 0000
Physical Address 0x4000 0000 Instance 0x4000 0000
Description Description Register.
This register provides IP module ID, revision information, instance index and standard MMR registers offset.
Type RO
Bits Field Name Description Type Reset
31:16 MODID Module identifier used to uniquely identify this IP. RO 0xD741
15:12 STDIPOFF Standard IP MMR block offset. Standard IP MMRs are the set of from aggregated IRQ registers till DTB.

0: Standard IP MMRs do not exist
0x1-0xF: Standard IP MMRs begin at offset of (64*STDIPOFF from the base IP address)		 RO 0x0
11:8 INSTIDX IP Instance ID number. If multiple instances of IP exist in the device, this field can identify the instance number (0-15). RO 0x0
7:4 MAJREV Major revision of IP (0-15). RO 0x1
3:0 MINREV Minor revision of IP (0-15). RO 0x0

TOP:PMCTL:DESCEX

Address Offset 0x0000 0004
Physical Address 0x4000 0004 Instance 0x4000 0004
Description Extended Description Register.
This register shows ULL IP availability and memory size configuration.
Type RO
Bits Field Name Description Type Reset
31:30 FLASHSZ System flash availability
Value ENUM Name Description
0x0 SZ0 Flash size set to level 0 (Min size)
0x1 SZ1 Flash size set to level 1
0x2 SZ2 Flash size set to level 2
0x3 SZ3 Flash size set to level 3 (Max size)
RO 0b11
29:28 SRAMSZ System SRAM availability
Value ENUM Name Description
0x0 SZ0 SRAM size set to level 0 (Min size)
0x1 SZ1 SRAM size set to level 1
0x2 SZ2 SRAM size set to level 2
0x3 SZ3 SRAM size set to level 3 (Max size)
RO 0b11
27 TSD TSD (thermal shutdown) IP status on device
Value ENUM Name Description
0x0 IP_UNAVAIL IP is unavailable
0x1 IP_AVAIL IP is available
RO 1
26 LPCMP LPCMP (low power comparator) IP status on device
Value ENUM Name Description
0x0 IP_UNAVAIL IP is unavailable
0x1 IP_AVAIL IP is available
RO 1
25:0 RESERVED0 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000 0000 0000 0000 0000

TOP:PMCTL:SHTDWN

Address Offset 0x0000 0008
Physical Address 0x4000 0008 Instance 0x4000 0008
Description Shutdown Register.
This register controls SHUTDOWN mode entry.
Type WO
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 KEY Setting a valid key will trigger the device to enter SHUTDOWN mode.
Value ENUM Name Description
0xA5A5 VALID This is the only valid key value that will trigger SHUTDOWN mode.
All other values are invalid and will have no effect.
WO 0x0000

TOP:PMCTL:SLPCTL

Address Offset 0x0000 000C
Physical Address 0x4000 000C Instance 0x4000 000C
Description Sleep Control Register.
This register controls I/O pad sleep mode. When I/O pad sleep mode is enabled all I/O pad outputs and I/O pad configurations are latched. Inputs are transparent if I/O pad is configured as input.
Type RW
Bits Field Name Description Type Reset
31:1 RESERVED1 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RW 0b000 0000 0000 0000 0000 0000 0000 0000
0 SLPN The boot code will set this bit field and disable sleep mode, automatically unless waking up from a SHUTDOWN RSTSTA.SDDET is set.
Application software must reconfigure the state for all IO's before setting this bit field upon waking up from a SHUTDOWN to avoid glitches on pins.
Value ENUM Name Description
0x0 EN I/O pad sleep mode is enabled
0x1 DIS I/O pad sleep mode is disabled
RW 0

TOP:PMCTL:WUSTA

Address Offset 0x0000 0010
Physical Address 0x4000 0010 Instance 0x4000 0010
Description Wakeup Status Register
This register shows the device wakeup source. Used to distinguish between wakeup from STANDBY, SHUTDOWN and reset.
Type RO
Bits Field Name Description Type Reset
31:2 RESERVED2 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000 0000 0000 0000 0000 0000
1:0 SRC This field shows the device wakeup source.
Value ENUM Name Description
0x1 RST_SHTDWN Wakeup from system reset / SHUTDOWN mode.
See RSTSTA for more status information.
0x2 STBY Wakeup from STANDBY mode.
RO 0b01

TOP:PMCTL:VDDRCTL

Address Offset 0x0000 0014
Physical Address 0x4000 0014 Instance 0x4000 0014
Description VDDR Control Register.
This register contains VDDR regulator settings for the device.
Type RW
Bits Field Name Description Type Reset
31:2 RESERVED2 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000 0000 0000 0000 0000 0000
1 STBY Select between continuous or duty-cycled VDDR regulation in STANDBY mode.
Value ENUM Name Description
0x0 NORMAL Duty-cycled VDDR regulation in STANDBY mode.
0x1 PSUEDO Continuous VDDR regulation in STANDBY mode.
RW 0
0 SELECT Select between GLDO and DCDC as VDDR regulator (in ACTIVE, IDLE and STANDBY mode).
Value ENUM Name Description
0x0 GLDO GLDO enabled for regulation of VDDR voltage
0x1 DCDC DCDC enabled for regulation of VDDR voltage
RW 0

TOP:PMCTL:SYSFSET

Address Offset 0x0000 0020
Physical Address 0x4000 0020 Instance 0x4000 0020
Description Internal. Only to be used through TI provided API.
Type WO
Bits Field Name Description Type Reset
31:3 RESERVED3 Internal. Only to be used through TI provided API. RO 0b0 0000 0000 0000 0000 0000 0000 0000
2 FLAG2 Internal. Only to be used through TI provided API.
Value ENUM Name Description
0x0 NOEFF Internal. Only to be used through TI provided API.
0x1 SET Internal. Only to be used through TI provided API.
WO 0
1 FLAG1 Internal. Only to be used through TI provided API.
Value ENUM Name Description
0x0 NOEFF Internal. Only to be used through TI provided API.
0x1 SET Internal. Only to be used through TI provided API.
WO 0
0 FLAG0 Internal. Only to be used through TI provided API.
Value ENUM Name Description
0x0 NOEFF Internal. Only to be used through TI provided API.
0x1 SET Internal. Only to be used through TI provided API.
WO 0

TOP:PMCTL:SYSFCLR

Address Offset 0x0000 0024
Physical Address 0x4000 0024 Instance 0x4000 0024
Description Internal. Only to be used through TI provided API.
Type WO
Bits Field Name Description Type Reset
31:3 RESERVED3 Internal. Only to be used through TI provided API. RO 0b0 0000 0000 0000 0000 0000 0000 0000
2 FLAG2 Internal. Only to be used through TI provided API.
Value ENUM Name Description
0x0 NOEFF Internal. Only to be used through TI provided API.
0x1 CLR Internal. Only to be used through TI provided API.
WO 0
1 FLAG1 Internal. Only to be used through TI provided API.
Value ENUM Name Description
0x0 NOEFF Internal. Only to be used through TI provided API.
0x1 CLR Internal. Only to be used through TI provided API.
WO 0
0 FLAG0 Internal. Only to be used through TI provided API.
Value ENUM Name Description
0x0 NOEFF Internal. Only to be used through TI provided API.
0x1 CLR Internal. Only to be used through TI provided API.
WO 0

TOP:PMCTL:SYSFSTA

Address Offset 0x0000 0028
Physical Address 0x4000 0028 Instance 0x4000 0028
Description Internal. Only to be used through TI provided API.
Type RO
Bits Field Name Description Type Reset
31:3 RESERVED3 Internal. Only to be used through TI provided API. RO 0b0 0000 0000 0000 0000 0000 0000 0000
2 FLAG2 Internal. Only to be used through TI provided API.
Value ENUM Name Description
0x0 VAL0 Internal. Only to be used through TI provided API.
0x1 VAL1 Internal. Only to be used through TI provided API.
RO 0
1 FLAG1 Internal. Only to be used through TI provided API.
Value ENUM Name Description
0x1 VAL1 Internal. Only to be used through TI provided API.
RO 0
0 FLAG0 Internal. Only to be used through TI provided API.
Value ENUM Name Description
0x0 VAL0 Internal. Only to be used through TI provided API.
0x1 VAL1 Internal. Only to be used through TI provided API.
RO 0

TOP:PMCTL:RSTCTL

Address Offset 0x0000 002C
Physical Address 0x4000 002C Instance 0x4000 002C
Description Reset Control Register.
This register configures and controls system reset.
Type RW
Bits Field Name Description Type Reset
31:3 RESERVED3 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000 0000 0000 0000 0000 0000 0000
2 LFLOSS LF clock loss reset enable.
Trigger system reset when LF clock loss is detected, which reset the entire device and causes a reboot of the system.
The system reset event is captured as RSTSTA.RESETSRC set to SYSRESET and RSTSTA.SYSSRC set to LFLOSSEV.
Value ENUM Name Description
0x0 DISARMED LF clock loss detection will not trigger a system reset.
0x1 ARMED LF clock loss detection will trigger a system reset.
RW 0
1 TSDEN TSD (Thermal Shutdown) enable.
TSD will trigger an immediate system reset, which reset the entire device and causes a reboot of the system.
The device will be in reset until released by the TSD IP.
The system reset event is captured as RSTSTA.TSDEV flag set.
Value ENUM Name Description
0x0 NOEFF No effect
0x1 EN Temperature shutdown comparator enable.
Note: If TSD IP not present, see DESCEX.TSD, enable will have no effect.
RW 0
0 SYSRST Trigger system reset, which will reset the entire device and causes a reboot of the system.
The system reset event is captured as RSTSTA.RESETSRC set to SYSRESET and RSTSTA.SYSSRC set to SYSRSTEV.
Value ENUM Name Description
0x0 NOEFF No effect
0x1 SET Trigger a system reset.
RW 0

TOP:PMCTL:RSTSTA

Address Offset 0x0000 0030
Physical Address 0x4000 0030 Instance 0x4000 0030
Description Reset Status.
This register contains the reset source and SHUTDOWN wakeup source for the system.
Check WUSTA.SRC first to ensure that wakeup from STANDBY is not set.
The capture feature is not rearmed until all of the possible reset sources have been released and the result has been copied to this register.
During the copy and rearm process it is one 24MHz period in which an eventual new system reset will be reported as Power on reset regardless of the root cause.
Type RO
Bits Field Name Description Type Reset
31:18 RESERVED18 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000 0000
17 SDDET Wakeup from SHUTDOWN flag.
Note: This flag will be cleared when SLPCTL.SLPN is asserted.
Value ENUM Name Description
0x0 NO_TRIG Wakeup from SHUTDOWN mode not triggered
0x1 TRIG Wakeup from SHUTDOWN mode
RO 0
16 IOWUSD Wakeup from SHUTDOWN on an I/O event flag.
Note: This flag will be cleared when SLPCTL.SLPN is asserted.
Value ENUM Name Description
0x0 NO_TRIG Wakeup from SHUTDOWN not triggered by an I/O event.
0x1 TRIG Wakeup from SHUTDOWN triggered by an I/O event.
RO 0
15:8 RESERVED8 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00
7:4 SYSSRC Shows which reset event that triggered SYSRESET in RESETSRC
Value ENUM Name Description
0x0 LFLOSSEV LF clock loss event
0x1 CPURSTEV CPU reset event
0x2 LOCKUPEV CPU LOCKUP event
0x3 WDTEV Watchdog timeout event
0x4 SYSRSTEV System reset event
0x5 SWDRSTEV Serial Wire Debug reset event
0x6 AFSMEV Analog FSM timeout event
0xE AERREV Analog Error reset event
0xF DERREV Digital Error reset event
RO 0x0
3 TSDEV System reset triggered by TSD event
Value ENUM Name Description
0x0 NO_TRIG TSD event not triggered
0x1 TRIG System reset triggered by TSD event
RO 0
2:0 RESETSRC Shows the root cause of the last system reset. More than one reported reset source can have been active during the last system reset, but only the root cause is reported.
If reset cause is SYSRESET or PINRESET, the other reset flags must be read to determine actual root cause.
Value ENUM Name Description
0x0 PWRON Power on reset
0x1 PINRESET Reset pin. TSD will also trigger a pin reset, so actual root cause is given by TSDEV reset flag status.
0x2 VDDSLOSS Brown out detect on VDDS
0x4 VDDRLOSS Brown out detect on VDDR
0x6 SYSRESET Digital system reset. Actual root cause is given by SYSSRC.
RO 0b000

TOP:PMCTL:BOOTSTA

Address Offset 0x0000 0034
Physical Address 0x4000 0034 Instance 0x4000 0034
Description Internal. Only to be used through TI provided API.
Type RW
Bits Field Name Description Type Reset
31:8 RESERVED8 Internal. Only to be used through TI provided API. RO 0x00 0000
7:0 FLAG Internal. Only to be used through TI provided API.
Value ENUM Name Description
0x0 BOOT_RESET Internal. Only to be used through TI provided API.
0x1 BOOT_COLD_BOOT Internal. Only to be used through TI provided API.
0x2 BOOT_SRAM_REP_DONE Internal. Only to be used through TI provided API.
0x3 BOOT_GENERAL_TRIMS Internal. Only to be used through TI provided API.
0x20 BOOT_ENTERED_SACI Internal. Only to be used through TI provided API.
0x36 BOOT_WAIT_SWD_DISCONNECT Internal. Only to be used through TI provided API.
0x37 BOOT_EXITED_SACI Internal. Only to be used through TI provided API.
0x38 BOOT_WAITLOOP_DBGPROBE Internal. Only to be used through TI provided API.
0x3E BOOT_FAIL_SRAM_REPAIR Internal. Only to be used through TI provided API.
0x3F BOOT_FAULT_HANDLER Internal. Only to be used through TI provided API.
0x80 MODE_BLDR Internal. Only to be used through TI provided API.
0x81 BLDR_WAITLOOP_DBGPROBE Internal. Only to be used through TI provided API.
0xBA BLDR_STARTED Internal. Only to be used through TI provided API.
0xBB BLDR_CMD_IDLE Internal. Only to be used through TI provided API.
0xBC BLDR_CMD_PROCESSING Internal. Only to be used through TI provided API.
0xBD BLDR_FAIL_EXECUTION_CONTEXT Internal. Only to be used through TI provided API.
0xBE BLDR_FAIL_APPTRANSFER Internal. Only to be used through TI provided API.
0xBF BLDR_FAULT_HANDLER Internal. Only to be used through TI provided API.
0xC0 MODE_APP Internal. Only to be used through TI provided API.
0xC1 APP_WAITLOOP_DBGPROBE Internal. Only to be used through TI provided API.
0xFD APP_FAIL_NOAPP Internal. Only to be used through TI provided API.
0xFE APP_FAIL_APPTRANSFER Internal. Only to be used through TI provided API.
0xFF APP_FAULT_HANDLER Internal. Only to be used through TI provided API.
RW 0x00

TOP:PMCTL:AONRSTA1

Address Offset 0x0000 003C
Physical Address 0x4000 003C Instance 0x4000 003C
Description AON Register Status 1.
This register contains the general purpose AON flags for SW, and is updated through AONRSET1.FLAG and AONRCLR1.FLAG.
The register is only reset on a POR event.
Type RO
Bits Field Name Description Type Reset
31:18 RESERVED18 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000 0000
17:0 FLAG State of the AON register flags RO 0b00 0000 0000 0000 0000

TOP:PMCTL:AONRSET1

Address Offset 0x0000 0040
Physical Address 0x4000 0040 Instance 0x4000 0040
Description AON Register Set 1.
This register sets the AON flags that can be read through AONRSTA1.FLAG.
Type WO
Bits Field Name Description Type Reset
31:18 RESERVED18 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RW 0b00 0000 0000 0000
17:0 FLAG Write 1 to set AONRSTA1.FLAG
Value ENUM Name Description
0x0 NOEFF No flags changed status
0x3FFFF ALL_SET Set all flags
WO 0b00 0000 0000 0000 0000

TOP:PMCTL:AONRCLR1

Address Offset 0x0000 0044
Physical Address 0x4000 0044 Instance 0x4000 0044
Description AON Register Clear 1.
This register clears the AON flags that can be read through AONRSTA1.FLAG.
Type WO
Bits Field Name Description Type Reset
31:18 RESERVED18 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RW 0b00 0000 0000 0000
17:0 FLAG Write 1 to clear AONRSTA1.FLAG
Value ENUM Name Description
0x0 NOEFF No flags changed status
0x3FFFF ALL_CLR Clear all flags
WO 0b00 0000 0000 0000 0000

TOP:PMCTL:ETPP

Address Offset 0x0000 0064
Physical Address 0x4000 0064 Instance 0x4000 0064
Description Internal. Only to be used through TI provided API.
Type RW
Bits Field Name Description Type Reset
31:0 RESERVED0 Internal. Only to be used through TI provided API. RO 0x0000 0000

TOP:PMCTL:RETCFG0

Address Offset 0x0000 007C
Physical Address 0x4000 007C Instance 0x4000 007C
Description Internal. Only to be used through TI provided API.
Type RW
Bits Field Name Description Type Reset
31:1 RESERVED1 Internal. Only to be used through TI provided API. RO 0b000 0000 0000 0000 0000 0000 0000 0000
0 VAL Internal. Only to be used through TI provided API. RW 1

TOP:PMCTL:RETCFG1

Address Offset 0x0000 0080
Physical Address 0x4000 0080 Instance 0x4000 0080
Description Internal. Only to be used through TI provided API.
Type RW
Bits Field Name Description Type Reset
31:1 RESERVED1 Internal. Only to be used through TI provided API. RO 0b000 0000 0000 0000 0000 0000 0000 0000
0 VAL Internal. Only to be used through TI provided API. RW 0

TOP:PMCTL:RETCFG2

Address Offset 0x0000 0084
Physical Address 0x4000 0084 Instance 0x4000 0084
Description Internal. Only to be used through TI provided API.
Type RW
Bits Field Name Description Type Reset
31:3 RESERVED3 Internal. Only to be used through TI provided API. RO 0b0 0000 0000 0000 0000 0000 0000 0000
2:0 VAL Internal. Only to be used through TI provided API. RW 0b010

TOP:PMCTL:RETCFG3

Address Offset 0x0000 0088
Physical Address 0x4000 0088 Instance 0x4000 0088
Description Internal. Only to be used through TI provided API.
Type RW
Bits Field Name Description Type Reset
31:0 RESERVED0 Internal. Only to be used through TI provided API. RO 0x0000 0000

TOP:PMCTL:RETCFG4

Address Offset 0x0000 008C
Physical Address 0x4000 008C Instance 0x4000 008C
Description Internal. Only to be used through TI provided API.
Type RW
Bits Field Name Description Type Reset
31:0 RESERVED0 Internal. Only to be used through TI provided API. RO 0x0000 0000

TOP:PMCTL:RETCFG5

Address Offset 0x0000 0090
Physical Address 0x4000 0090 Instance 0x4000 0090
Description Internal. Only to be used through TI provided API.
Type RW
Bits Field Name Description Type Reset
31:0 RESERVED0 Internal. Only to be used through TI provided API. RO 0x0000 0000

TOP:PMCTL:RETCFG6

Address Offset 0x0000 0094
Physical Address 0x4000 0094 Instance 0x4000 0094
Description Internal. Only to be used through TI provided API.
Type RW
Bits Field Name Description Type Reset
31:0 RESERVED0 Internal. Only to be used through TI provided API. RO 0x0000 0000

TOP:PMCTL:RETCFG7

Address Offset 0x0000 0098
Physical Address 0x4000 0098 Instance 0x4000 0098
Description Internal. Only to be used through TI provided API.
Type RW
Bits Field Name Description Type Reset
31:0 RESERVED0 Internal. Only to be used through TI provided API. RO 0x0000 0000


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