Instance: CLKCTL
Component: CLKCTL
Base address: 0x40020000
This component is the clock controller. Here SW can turn on and off IP clocks and read IP and system clock status.
Register Name |
Type |
Register Width (Bits) |
Register Reset |
Address Offset |
Physical Address |
RO |
32 |
0x2548 0000 |
0x0000 0000 |
0x4002 0000 |
|
RO |
32 |
0x7803 4447 |
0x0000 0004 |
0x4002 0004 |
|
RO |
32 |
0xF000 FF00 |
0x0000 0008 |
0x4002 0008 |
|
RO |
32 |
0x0000 0001 |
0x0000 000C |
0x4002 000C |
|
RO |
32 |
0x0000 0000 |
0x0000 0010 |
0x4002 0010 |
|
WO |
32 |
0x0000 0000 |
0x0000 0014 |
0x4002 0014 |
|
WO |
32 |
0x0000 0000 |
0x0000 0018 |
0x4002 0018 |
|
WO |
32 |
0x0000 0000 |
0x0000 0020 |
0x4002 0020 |
|
WO |
32 |
0x0000 0000 |
0x0000 0024 |
0x4002 0024 |
|
RW |
32 |
0x0000 0000 |
0x0000 003C |
0x4002 003C |
|
RW |
32 |
0x0000 0000 |
0x0000 0048 |
0x4002 0048 |
Address Offset | 0x0000 0000 | ||
Physical Address | 0x4002 0000 | Instance | 0x4002 0000 |
Description | Description Register. This register provides IP module ID, revision information, instance index and standard MMR registers offset. |
||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:16 | MODID | Module identifier used to uniquely identify this IP. | RO | 0x2548 | ||
15:12 | STDIPOFF | Standard IP MMR block offset. Standard IP MMRs are the set of from aggregated IRQ registers till DTB. 0: Standard IP MMRs do not exist 0x1-0xF: Standard IP MMRs begin at offset of (64*STDIPOFF from the base IP address) |
RO | 0x0 | ||
11:8 | INSTIDX | IP Instance ID number. If multiple instances of IP exist in the device, this field can identify the instance number (0-15). | RO | 0x0 | ||
7:4 | MAJREV | Major revision of IP 0-15 | RO | 0x0 | ||
3:0 | MINREV | Minor revision of IP 0-15. | RO | 0x0 |
Address Offset | 0x0000 0004 | ||
Physical Address | 0x4002 0004 | Instance | 0x4002 0004 |
Description | Extended Description Register 0. This register shows SVT IP availability, HW features and memory size configuration. |
||
Type | RO |
Bits | Field Name | Description | Type | Reset | |||||||||||
31 | RESERVED31 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0 | |||||||||||
30 | LGPT3 | IP status on device
|
RO | 1 | |||||||||||
29 | LGPT2 | IP status on device
|
RO | 1 | |||||||||||
28 | LGPT1 | IP status on device
|
RO | 1 | |||||||||||
27 | LGPT0 | IP status on device
|
RO | 1 | |||||||||||
26:18 | RESERVED18 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 | |||||||||||
17 | DMA | IP status on device
|
RO | 1 | |||||||||||
16 | LAES | IP status on device
|
RO | 1 | |||||||||||
15 | RESERVED15 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0 | |||||||||||
14 | ADC0 | IP status on device
|
RO | 1 | |||||||||||
13:11 | RESERVED11 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 | |||||||||||
10 | SPI0 | IP status on device
|
RO | 1 | |||||||||||
9:7 | RESERVED7 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 | |||||||||||
6 | I2C0 | IP status on device
|
RO | 1 | |||||||||||
5:3 | RESERVED3 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 | |||||||||||
2 | UART0 | IP status on device
|
RO | 1 | |||||||||||
1 | LRFD | IP status on device
|
RO | 1 | |||||||||||
0 | GPIO | IP status on device
|
RO | 1 |
Address Offset | 0x0000 0008 | ||
Physical Address | 0x4002 0008 | Instance | 0x4002 0008 |
Description | Extended Description Register 1. This register shows SVT IP availability, HW features and memory size configuration. |
||
Type | RO |
Bits | Field Name | Description | Type | Reset | |||||||||||||||||
31:30 | FLASHSZ | System flash availability
|
RO | 0b11 | |||||||||||||||||
29:28 | SRAMSZ | System SRAM availability
|
RO | 0b11 | |||||||||||||||||
27:16 | RESERVED16 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x000 | |||||||||||||||||
15:8 | ROPT | System radio feature availability
|
RO | 0xFF | |||||||||||||||||
7:0 | RESERVED0 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 |
Address Offset | 0x0000 000C | ||
Physical Address | 0x4002 000C | Instance | 0x4002 000C |
Description | Clock Configuration Register 0. This register shows the IP clock configuration for the system. The configuration is updated through CLKENSET0 and CLKENCLR0. |
||
Type | RO |
Bits | Field Name | Description | Type | Reset | |||||||||||
31 | RESERVED31 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0 | |||||||||||
30 | LGPT3 | IP clock configuration
|
RO | 0 | |||||||||||
29 | LGPT2 | IP clock configuration
|
RO | 0 | |||||||||||
28 | LGPT1 | IP clock configuration
|
RO | 0 | |||||||||||
27 | LGPT0 | IP clock configuration
|
RO | 0 | |||||||||||
26:18 | RESERVED18 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 | |||||||||||
17 | DMA | IP clock configuration
|
RO | 0 | |||||||||||
16 | LAES | IP clock configuration
|
RO | 0 | |||||||||||
15 | RESERVED15 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0 | |||||||||||
14 | ADC0 | IP clock configuration
|
RO | 0 | |||||||||||
13:11 | RESERVED11 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 | |||||||||||
10 | SPI0 | IP clock configuration
|
RO | 0 | |||||||||||
9:7 | RESERVED7 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 | |||||||||||
6 | I2C0 | IP clock configuration
|
RO | 0 | |||||||||||
5:3 | RESERVED3 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 | |||||||||||
2 | UART0 | IP clock configuration
|
RO | 0 | |||||||||||
1 | LRFD | IP clock configuration
|
RO | 0 | |||||||||||
0 | GPIO | IP clock configuration
|
RO | 1 |
Address Offset | 0x0000 0010 | ||
Physical Address | 0x4002 0010 | Instance | 0x4002 0010 |
Description | Clock Configuration Register 1. This register shows the IP clock configuration for the system. The configuration is updated through CLKENSET1 and CLKENCLR1. |
||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:0 | RESERVED0 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0000 0000 |
Address Offset | 0x0000 0014 | ||
Physical Address | 0x4002 0014 | Instance | 0x4002 0014 |
Description | Clock Enable Set Register 0. This register enables IP clocks in the system. Used to set the corresponding fields in CLKCFG0 to 1. |
||
Type | WO |
Bits | Field Name | Description | Type | Reset | |||||||||||
31 | RESERVED31 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0 | |||||||||||
30 | LGPT3 | Configure IP clock enable
|
WO | 0 | |||||||||||
29 | LGPT2 | Configure IP clock enable
|
WO | 0 | |||||||||||
28 | LGPT1 | Configure IP clock enable
|
WO | 0 | |||||||||||
27 | LGPT0 | Configure IP clock enable
|
WO | 0 | |||||||||||
26:18 | RESERVED18 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 | |||||||||||
17 | DMA | Configure IP clock enable
|
WO | 0 | |||||||||||
16 | LAES | Configure IP clock enable
|
WO | 0 | |||||||||||
15 | RESERVED15 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0 | |||||||||||
14 | ADC0 | Configure IP clock enable
|
WO | 0 | |||||||||||
13:11 | RESERVED11 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 | |||||||||||
10 | SPI0 | Configure IP clock enable
|
WO | 0 | |||||||||||
9:7 | RESERVED7 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 | |||||||||||
6 | I2C0 | Configure IP clock enable
|
WO | 0 | |||||||||||
5:3 | RESERVED3 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 | |||||||||||
2 | UART0 | Configure IP clock enable
|
WO | 0 | |||||||||||
1 | LRFD | Configure IP clock enable
|
WO | 0 | |||||||||||
0 | GPIO | Configure IP clock enable
|
WO | 0 |
Address Offset | 0x0000 0018 | ||
Physical Address | 0x4002 0018 | Instance | 0x4002 0018 |
Description | Clock Enable Set Register 1. This register enables IP clocks in the system. Used to set the corresponding fields in CLKCFG1 to 1. |
||
Type | WO |
Bits | Field Name | Description | Type | Reset | ||
31:0 | RESERVED0 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0000 0000 |
Address Offset | 0x0000 0020 | ||
Physical Address | 0x4002 0020 | Instance | 0x4002 0020 |
Description | Clock Enable Clear Register 0. This register disables IP clocks in the system. Used to clear the corresponding fields in CLKCFG0 to 0. |
||
Type | WO |
Bits | Field Name | Description | Type | Reset | |||||||||||
31 | RESERVED31 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0 | |||||||||||
30 | LGPT3 | Configure IP clock enable
|
WO | 0 | |||||||||||
29 | LGPT2 | Configure IP clock enable
|
WO | 0 | |||||||||||
28 | LGPT1 | Configure IP clock enable
|
WO | 0 | |||||||||||
27 | LGPT0 | Configure IP clock enable
|
WO | 0 | |||||||||||
26:18 | RESERVED18 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 | |||||||||||
17 | DMA | Configure IP clock enable
|
WO | 0 | |||||||||||
16 | LAES | Configure IP clock enable
|
WO | 0 | |||||||||||
15 | RESERVED15 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0 | |||||||||||
14 | ADC0 | Configure IP clock enable
|
WO | 0 | |||||||||||
13:11 | RESERVED11 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 | |||||||||||
10 | SPI0 | Configure IP clock enable
|
WO | 0 | |||||||||||
9:7 | RESERVED7 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 | |||||||||||
6 | I2C0 | Configure IP clock enable
|
WO | 0 | |||||||||||
5:3 | RESERVED3 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 | |||||||||||
2 | UART0 | Configure IP clock enable
|
WO | 0 | |||||||||||
1 | LRFD | Configure IP clock enable
|
WO | 0 | |||||||||||
0 | GPIO | Configure IP clock enable
|
WO | 0 |
Address Offset | 0x0000 0024 | ||
Physical Address | 0x4002 0024 | Instance | 0x4002 0024 |
Description | Clock Enable Clear Register 1. This register disables IP clocks in the system. Used to clear the corresponding fields in CLKCFG1 to 0. |
||
Type | WO |
Bits | Field Name | Description | Type | Reset | ||
31:0 | RESERVED0 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0000 0000 |
Address Offset | 0x0000 003C | ||
Physical Address | 0x4002 003C | Instance | 0x4002 003C |
Description | Internal. Only to be used through TI provided API. | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||||||||
31:0 | VAL | Internal. Only to be used through TI provided API.
|
RW | 0x0000 0000 |
Address Offset | 0x0000 0048 | ||
Physical Address | 0x4002 0048 | Instance | 0x4002 0048 |
Description | IDLE Configuration Register. This register contains flash LDO configuration for IDLE mode. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:1 | RESERVED1 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 0000 0000 | |||||||||||
0 | MODE | Flash LDO configuration in SLEEP/IDLE mode.
|
RW | 0 |
© 2015 - 2016. Texas Instruments | All Rights Reserved |