BPU

Instance: BPU
Component: BPU
Base address: 0xE0002000


TOP:BPU Register Summary

Register Name

Type

Register Width (Bits)

Register Reset

Address Offset

Physical Address

BP_CTRL

32

0x0000 0040

0x0000 0000

0xE000 2000

BP_COMP0

32

0x0000 0000

0x0000 0008

0xE000 2008

BP_COMP1

32

0x0000 0000

0x0000 000C

0xE000 200C

BP_COMP2

32

0x0000 0000

0x0000 0010

0xE000 2010

BP_COMP3

32

0x0000 0000

0x0000 0014

0xE000 2014

PIDR4

32

0x0000 0004

0x0000 0FD0

0xE000 2FD0

PIDR5

32

0x0000 0000

0x0000 0FD4

0xE000 2FD4

PIDR6

32

0x0000 0000

0x0000 0FD8

0xE000 2FD8

PIDR7

32

0x0000 0000

0x0000 0FDC

0xE000 2FDC

PIDR0

32

0x0000 000B

0x0000 0FE0

0xE000 2FE0

PIDR1

32

0x0000 00B0

0x0000 0FE4

0xE000 2FE4

PIDR2

32

0x0000 000B

0x0000 0FE8

0xE000 2FE8

PIDR3

32

0x0000 0000

0x0000 0FEC

0xE000 2FEC

CIDR0

32

0x0000 000D

0x0000 0FF0

0xE000 2FF0

CIDR1

32

0x0000 00E0

0x0000 0FF4

0xE000 2FF4

CIDR2

32

0x0000 0005

0x0000 0FF8

0xE000 2FF8

CIDR3

32

0x0000 00B1

0x0000 0FFC

0xE000 2FFC

TOP:BPU Register Descriptions

TOP:BPU:BP_CTRL

Address Offset 0x0000 0000
Physical Address 0xE000 2000 Instance 0xE000 2000
Description Breakpoint Control Register

Use the Breakpoint Control Register to enable the Breakpoint block
Type
Bits Field Name Description Type Reset
31:8 RESERVED8 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00 0000
7:4 NUM_CODE Number of comparators. RO 0x4
3:2 RESERVED2 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00
1 KEY Key field. To write to the Breakpoint Control Register, you must write a 1 to this write-only bit. This bit reads as zero. WO 0
0 ENABLE Breakpoint unit enable bit. DBGRESETn clears the ENABLE bit.
Value ENUM Name Description
0x0 BKPT_DIS Breakpoint unit disabled
0x1 BKPT_EN Breakpoint unit enabled
RW 0

TOP:BPU:BP_COMP0

Address Offset 0x0000 0008
Physical Address 0xE000 2008 Instance 0xE000 2008
Description Breakpoint Comparator Register 0

Use the Breakpoint Comparator Registers to store the values to compare with the instruction address.
Type
Bits Field Name Description Type Reset
31:30 BP_MATCH This selects what happens when the COMP address is matched
Value ENUM Name Description
0x0 BKPT_COMP_NONE no breakpoint generated
0x1 BKPT_COMP_LOW set breakpoint on lower halfword, upper is unaffected
0x2 BKPT_COMP_HI set breakpoint on upper halfword, lower is unaffected
0x3 BKPT_COMP_BOTH set breakpoint on both lower and upper halfwords
RW 0b00
29 RESERVED29 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0
28:2 COMP Comparison address, UNKNOWN on reset. RW 0b000 0000 0000 0000 0000 0000 0000
1 RESERVED1 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0
0 ENABLE Compare enable for Breakpoint Comparator Register 0. The ENABLE bit of BP_CTRL must also be set to enable comparisons. DBGRESETn clears the ENABLE bit.
Value ENUM Name Description
0x0 BKPT_COMP_EN Breakpoint Comparator Register 0 compare disabled
0x1 BKPT_COMP_DIS Breakpoint Comparator Register 0 compare enabled
RW 0

TOP:BPU:BP_COMP1

Address Offset 0x0000 000C
Physical Address 0xE000 200C Instance 0xE000 200C
Description Breakpoint Comparator Register 1

Use the Breakpoint Comparator Registers to store the values to compare with the instruction address.
Type
Bits Field Name Description Type Reset
31:30 BP_MATCH This selects what happens when the COMP address is matched
Value ENUM Name Description
0x0 BKPT_COMP_NONE No breakpoint generated
0x1 BKPT_COMP_LOW Set breakpoint on lower halfword, upper is unaffected
0x2 BKPT_COMP_HI Set breakpoint on upper halfword, lower is unaffected
0x3 BKPT_COMP_BOTH Set breakpoint on both lower and upper halfwords
RW 0b00
29 RESERVED29 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0
28:2 COMP Comparison address. Although it is architecturally Unpredictable whether breakpoint matches on the address of the second halfword of a 32-bit instruction to generates a debug event, in this processor it is predictable and a debug event is generated. RW 0b000 0000 0000 0000 0000 0000 0000
1 RESERVED1 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0
0 ENABLE Comparison address, UNKNOWN on reset.
Value ENUM Name Description
0x0 BKPT_COMP_EN Breakpoint Comparator Register 1 compare disabled
0x1 BKPT_COMP_DIS Breakpoint Comparator Register 1 compare enabled
RW 0

TOP:BPU:BP_COMP2

Address Offset 0x0000 0010
Physical Address 0xE000 2010 Instance 0xE000 2010
Description Breakpoint Comparator Register 2

Use the Breakpoint Comparator Registers to store the values to compare with the PC address.
Type
Bits Field Name Description Type Reset
31:30 BP_MATCH This selects what happens when the COMP address is matched
Value ENUM Name Description
0x0 BKPT_COMP_NONE No breakpoint matching
0x1 BKPT_COMP_LOW Set breakpoint on lower halfword, upper is unaffected
0x2 BKPT_COMP_HI Set breakpoint on upper halfword, lower is unaffected
0x3 BKPT_COMP_BOTH Set breakpoint on both lower and upper halfwords
RW 0b00
29 RESERVED29 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0
28:2 COMP Comparison address, UNKNOWN on reset. RW 0b000 0000 0000 0000 0000 0000 0000
1 RESERVED1 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0
0 ENABLE Compare enable for Breakpoint Comparator Register 2. The ENABLE bit of BP_CTRL must also be set to enable comparisons. DBGRESETn clears the ENABLE bit.
Value ENUM Name Description
0x0 BKPT_COMP_EN Breakpoint Comparator Register 2 compare disabled
0x1 BKPT_COMP_DIS Breakpoint Comparator Register 2 compare enabled
RW 0

TOP:BPU:BP_COMP3

Address Offset 0x0000 0014
Physical Address 0xE000 2014 Instance 0xE000 2014
Description Breakpoint Comparator Register 3

Use the Breakpoint Comparator Registers to store the values to compare with the instruction address.
Type
Bits Field Name Description Type Reset
31:30 BP_MATCH This selects what happens when the COMP address is matched
Value ENUM Name Description
0x0 BKPT_COMP_NONE No breakpoint generated
0x1 BKPT_COMP_LOW Set breakpoint on lower halfword, upper is unaffected
0x2 BKPT_COMP_HI Set breakpoint on upper halfword, lower is unaffected
0x3 BKPT_COMP_BOTH Set breakpoint on both lower and upper halfwords
RW 0b00
29 RESERVED29 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0
28:2 COMP Comparison address, UNKNOWN on reset. RW 0b000 0000 0000 0000 0000 0000 0000
1 RESERVED1 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0
0 ENABLE Compare enable for Breakpoint Comparator Register 3. The ENABLE bit of BP_CTRL must also be set to enable comparisons. DBGRESETn clears the ENABLE bit.
Value ENUM Name Description
0x0 BKPT_COMP_EN Breakpoint Comparator Register 3 compare disabled
0x1 BKPT_COMP_DIS Breakpoint Comparator Register 3 compare enabled
RW 0

TOP:BPU:PIDR4

Address Offset 0x0000 0FD0
Physical Address 0xE000 2FD0 Instance 0xE000 2FD0
Description Peripheral ID Register 4

Part of the set of Peripheral Identification registers. Contains part of the designer identity and the memory footprint indicator.
Type
Bits Field Name Description Type Reset
31:8 RESERVED8 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00 0000
7:4 SIZE This is a 4-bit value that indicates the total contiguous size of the memory window used by this component in powers of 2 from the standard 4KB. If a component only requires the standard 4KB then this should read as 0x0, 4KB only, for 8KB set to 0x1, 16KB == 0x2, 32KB == 0x3, and so on. RO 0x0
3:0 DES_2 Number of JEDEC continuation codes. Indicates the designer of the component (along with the identity code) RO 0x4

TOP:BPU:PIDR5

Address Offset 0x0000 0FD4
Physical Address 0xE000 2FD4 Instance 0xE000 2FD4
Description Peripheral ID Register 5

Reserved
Type
Bits Field Name Description Type Reset
31:0 RESERVED0 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000 0000

TOP:BPU:PIDR6

Address Offset 0x0000 0FD8
Physical Address 0xE000 2FD8 Instance 0xE000 2FD8
Description Peripheral ID Register 6

Reserved
Type
Bits Field Name Description Type Reset
31:0 RESERVED0 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000 0000

TOP:BPU:PIDR7

Address Offset 0x0000 0FDC
Physical Address 0xE000 2FDC Instance 0xE000 2FDC
Description Peripheral ID Register 7

Reserved
Type
Bits Field Name Description Type Reset
31:0 RESERVED0 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000 0000

TOP:BPU:PIDR0

Address Offset 0x0000 0FE0
Physical Address 0xE000 2FE0 Instance 0xE000 2FE0
Description Peripheral ID Register 0

Part of the set of Peripheral Identification registers. Contains part of the designer specific part number.
Type
Bits Field Name Description Type Reset
31:8 RESERVED8 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00 0000
7:0 PART_0 Bits [7:0] of the component's part number. This is selected by the designer of the component. RO 0x0B

TOP:BPU:PIDR1

Address Offset 0x0000 0FE4
Physical Address 0xE000 2FE4 Instance 0xE000 2FE4
Description Peripheral ID Register 1

Part of the set of Peripheral Identification registers. Contains part of the designer specific part number and part of the designer identity.
Type
Bits Field Name Description Type Reset
31:8 RESERVED8 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00 0000
7:4 DES_0 Bits [3:0] of the JEDEC identity code indicating the designer of the component (along with the continuation code) RO 0xB
3:0 PART_1 Bits [11:8] of the component's part number. This is selected by the designer of the component. RO 0x0

TOP:BPU:PIDR2

Address Offset 0x0000 0FE8
Physical Address 0xE000 2FE8 Instance 0xE000 2FE8
Description Peripheral ID Register 2

Part of the set of Peripheral Identification registers. Contains part of the designer identity and the product revision.
Type
Bits Field Name Description Type Reset
31:8 RESERVED8 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00 0000
7:4 REVISION The Revision field is an incremental value starting at 0x0 for the first design of this component. This only increases by 1 for both major and minor revisions and is simply used as a look-up to establish the exact major/minor revision. RO 0x0
3 JEDEC Always set. Indicates that a JEDEC assigned value is used RO 1
2:0 DES_1 Bits [6:4] of the JEDEC identity code indicating the designer of the component (along with the continuation code) RO 0b011

TOP:BPU:PIDR3

Address Offset 0x0000 0FEC
Physical Address 0xE000 2FEC Instance 0xE000 2FEC
Description Peripheral ID Register 3

Part of the set of Peripheral Identification registers. Contains the RevAnd and Customer Modified fields.
Type
Bits Field Name Description Type Reset
31:8 RESERVED8 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00 0000
7:4 REVAND This field indicates minor errata fixes specific to this design, for example metal fixes after implementation. In most cases this field is zero. It is recommended that component designers ensure this field can be changed by a metal fix if required, for example by driving it from registers that reset to zero. RO 0x0
3:0 CMOD Where the component is reusable IP, this value indicates if the customer has modified the behavior of the component. In most cases this field is zero. RO 0x0

TOP:BPU:CIDR0

Address Offset 0x0000 0FF0
Physical Address 0xE000 2FF0 Instance 0xE000 2FF0
Description Component ID Register 0

A component identification register, that indicates that the identification registers are present.
Type
Bits Field Name Description Type Reset
31:8 RESERVED8 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00 0000
7:0 PRMBL_0 Contains bits [7:0] of the component identification RO 0x0D

TOP:BPU:CIDR1

Address Offset 0x0000 0FF4
Physical Address 0xE000 2FF4 Instance 0xE000 2FF4
Description Component ID Register 1

A component identification register, that indicates that the identification registers are present. This register also indicates the component class.
Type
Bits Field Name Description Type Reset
31:8 RESERVED8 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00 0000
7:4 CLASS Class of the component. E.g. ROM table, CoreSight component etc. Constitutes bits [15:12] of the component identification. RO 0xE
3:0 PRMBL_1 Contains bits [11:8] of the component identification RO 0x0

TOP:BPU:CIDR2

Address Offset 0x0000 0FF8
Physical Address 0xE000 2FF8 Instance 0xE000 2FF8
Description Component ID Register 2

A component identification register, that indicates that the identification registers are present.
Type
Bits Field Name Description Type Reset
31:8 RESERVED8 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00 0000
7:0 PRMBL_2 Contains bits [23:16] of the component identification RO 0x05

TOP:BPU:CIDR3

Address Offset 0x0000 0FFC
Physical Address 0xE000 2FFC Instance 0xE000 2FFC
Description Component ID Register 3

A component identification register, that indicates that the identification registers are present.
Type
Bits Field Name Description Type Reset
31:8 RESERVED8 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00 0000
7:0 PRMBL_3 Contains bits [31:24] of the component identification RO 0xB1


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