LRFDTRC

Instance: LRFDTRC
Component: LRFDTRC
Base address: 0x40084000


TOP:LRFDTRC Register Summary

Register Name

Type

Register Width (Bits)

Register Reset

Address Offset

Physical Address

CFG

RW

32

0x0000 0000

0x0000 0000

0x4008 4000

CH1CMD

RW

32

0x0000 0000

0x0000 0004

0x4008 4004

CH2CMD

RW

32

0x0000 0000

0x0000 0008

0x4008 4008

CH3CMD

RW

32

0x0000 0000

0x0000 000C

0x4008 400C

CH1PAR01

RW

32

0x0000 0000

0x0000 0014

0x4008 4014

CH2PAR01

RW

32

0x0000 0000

0x0000 0018

0x4008 4018

CH3PAR01

RW

32

0x0000 0000

0x0000 001C

0x4008 401C

CH1PAR23

RW

32

0x0000 0000

0x0000 0024

0x4008 4024

CH2PAR23

RW

32

0x0000 0000

0x0000 0028

0x4008 4028

CH3PAR23

RW

32

0x0000 0000

0x0000 002C

0x4008 402C

TOP:LRFDTRC Register Descriptions

TOP:LRFDTRC:CFG

Address Offset 0x0000 0000
Physical Address 0x4008 4000 Instance 0x4008 4000
Description Tracer Configuration
Type RW
Bits Field Name Description Type Reset
31:9 RESERVED9 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000 0000
8:7 PRESCAL Data rate prescaler for bit clock of the serialized data
Value ENUM Name Description
0x0 DIV1 Divide clock by 1
0x1 DIV2 Divide clock by 2
0x2 DIV3 Divide clock by 3
0x3 DIV4 Divide clock by 4
RW 0b00
6 TSCLR Writing 1 to this bit clears the TX timer
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
WO 0
5 TSEN Enables the Timestamp
Value ENUM Name Description
0x0 OFF The bit is 0
0x1 ON The bit is 1
RW 0
4:3 CH3EN Enables CH3 traces
Value ENUM Name Description
0x0 OFF Disabled. No tracer transfer due to CH3 events
0x1 NORM Enabled in normal mode. Data from bus slave interface.
0x2 TOPSM Enabled with MCE, MCO and CCE backdoor access access
RW 0b00
2:1 CH2EN Enables CH2 traces
Value ENUM Name Description
0x0 OFF Disabled. No tracer transfer due to CH2 events
0x1 NORM Enabled in normal mode. Data from bus slave interface.
0x2 TOPSM Enabled with PBE and RFE backdoor access access
RW 0b00
0 CH1EN Enables CH1 traces
Value ENUM Name Description
0x0 OFF Disabled. No tracer transfer due to CH1 events
0x1 NORM Enabled in normal mode. Data from bus slave interface.
RW 0

TOP:LRFDTRC:CH1CMD

Address Offset 0x0000 0004
Physical Address 0x4008 4004 Instance 0x4008 4004
Description Channel 1 Command Register. Note only writeable when TRC.CFG.CH1EN = 1
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:8 PKTHDR Header Byte. Reverts back to 0 when ready to transmit. A Write starts a transmission sequence.
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFF ALLONES All the bits are 1
RW 0x00
7:3 RESERVED3 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000
2:0 PARCNT Number of parameters to transmit. Reverts back to 0 when ready to transmit. A Write starts a transmission sequence.
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0x7 ALLONES All the bits are 1
RW 0b000

TOP:LRFDTRC:CH2CMD

Address Offset 0x0000 0008
Physical Address 0x4008 4008 Instance 0x4008 4008
Description Channel 2 Command Register. Note only writeable when TRC.CFG.CH2EN = 1
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:8 PKTHDR Header Byte. Reverts back to 0 when ready to transmit. A Write starts a transmission sequence.
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFF ALLONES All the bits are 1
RW 0x00
7:3 RESERVED3 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000
2:0 PARCNT Number of parameters to transmit. Reverts back to 0 when ready to transmit. A Write starts a transmission sequence.
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0x7 ALLONES All the bits are 1
RW 0b000

TOP:LRFDTRC:CH3CMD

Address Offset 0x0000 000C
Physical Address 0x4008 400C Instance 0x4008 400C
Description Channel 3 Command Register. Note only writeable when TRC.CFG.CH3EN = 1
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:8 PKTHDR Header Byte. Reverts back to 0 when ready to transmit. A Write starts a transmission sequence.
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFF ALLONES All the bits are 1
RW 0x00
7:3 RESERVED3 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000
2:0 PARCNT Number of parameters to transmit. Reverts back to 0 when ready to transmit. A Write starts a transmission sequence.
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0x7 ALLONES All the bits are 1
RW 0b000

TOP:LRFDTRC:CH1PAR01

Address Offset 0x0000 0014
Physical Address 0x4008 4014 Instance 0x4008 4014
Description Channel 1 Parameter 0/1 Register
Type RW
Bits Field Name Description Type Reset
31:16 PAR1 Parameter 1 for Channel 1
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RW 0x0000
15:0 PAR0 Parameter 0 for Channel 1
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RW 0x0000

TOP:LRFDTRC:CH2PAR01

Address Offset 0x0000 0018
Physical Address 0x4008 4018 Instance 0x4008 4018
Description Channel 2 Parameter 0/1 Register
Type RW
Bits Field Name Description Type Reset
31:16 PAR1 Parameter 1 for Channel 2
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RW 0x0000
15:0 PAR0 Parameter 0 for Channel 2
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RW 0x0000

TOP:LRFDTRC:CH3PAR01

Address Offset 0x0000 001C
Physical Address 0x4008 401C Instance 0x4008 401C
Description Channel 3 Parameter 0/1 Register
Type RW
Bits Field Name Description Type Reset
31:16 PAR1 Parameter 1 for Channel 3
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RW 0x0000
15:0 PAR0 Parameter 0 for Channel 3
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RW 0x0000

TOP:LRFDTRC:CH1PAR23

Address Offset 0x0000 0024
Physical Address 0x4008 4024 Instance 0x4008 4024
Description Channel 1 Parameter 2/3 Register
Type RW
Bits Field Name Description Type Reset
31:16 PAR3 Parameter 3 for Channel 1
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RW 0x0000
15:0 PAR2 Parameter 2 for Channel 1
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RW 0x0000

TOP:LRFDTRC:CH2PAR23

Address Offset 0x0000 0028
Physical Address 0x4008 4028 Instance 0x4008 4028
Description Channel 2 Parameter 2/3 Register
Type RW
Bits Field Name Description Type Reset
31:16 PAR3 Parameter 3 for Channel 2
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RW 0x0000
15:0 PAR2 Parameter 2 for Channel 2
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RW 0x0000

TOP:LRFDTRC:CH3PAR23

Address Offset 0x0000 002C
Physical Address 0x4008 402C Instance 0x4008 402C
Description Channel 3 Parameter 2/3 Register
Type RW
Bits Field Name Description Type Reset
31:16 PAR3 Parameter 3 for Channel 3
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RW 0x0000
15:0 PAR2 Parameter 2 for Channel 3
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RW 0x0000


© 2015 - 2016. Texas Instruments | All Rights Reserved