LRFDRFE32

Instance: LRFDRFE32
Component: LRFDRFE32
Base address: 0x40083400


TOP:LRFDRFE32 Register Summary

Register Name

Type

Register Width (Bits)

Register Reset

Address Offset

Physical Address

FWSRC_ENABLE

RW

32

0x0000 0000

0x0000 0000

0x4008 3400

PDREQ_INIT

WO

32

0x0000 0000

0x0000 0004

0x4008 3404

EVT1_EVT0

RO

32

0x0000 0000

0x0000 0008

0x4008 3408

EVTMSK1_EVTMSK0

RW

32

0x0000 0000

0x0000 000C

0x4008 340C

EVTCLR1_EVTCLR0

WO

32

0x0000 0000

0x0000 0010

0x4008 3410

HFXTSTAT

RO

32

0x0000 0000

0x0000 0014

0x4008 3414

RFSTATE

RW

32

0x0000 0000

0x0000 0018

0x4008 3418

CMDPAR0_API

RO

32

0x0000 0000

0x0000 0024

0x4008 3424

MSGBOX_CMDPAR1

RO

32

0x0000 0000

0x0000 0028

0x4008 3428

MCEDATIN0_MCEDATOUT0

RW

32

0x0000 0000

0x0000 002C

0x4008 342C

MCECMDIN_MCECMDOUT

RW

32

0x0000 0000

0x0000 0030

0x4008 3430

PBEDATIN0_PBEDATOUT0

RW

32

0x0000 0000

0x0000 0034

0x4008 3434

PBECMDIN_PBECMDOUT

RW

32

0x0000 0000

0x0000 0038

0x4008 3438

STRB

WO

32

0x0000 0000

0x0000 003C

0x4008 343C

MAGNTHR_MAGNTHRCFG

RW

32

0x0000 0000

0x0000 0040

0x4008 3440

GAINCTL_RSSIOFFSET

RW

32

0x0000 0000

0x0000 0044

0x4008 3444

MAGNCTL1_MAGNCTL0

RW

32

0x0000 0000

0x0000 0048

0x4008 3448

SPARE1_SPARE0

RW

32

0x0000 0000

0x0000 004C

0x4008 344C

SPARE3_SPARE2

RW

32

0x0000 0000

0x0000 0050

0x4008 3450

SPARE5_SPARE4

RW

32

0x0000 0000

0x0000 0054

0x4008 3454

IFAMPRFLDO_LNA

RW

32

0x0000 0000

0x0000 0058

0x4008 3458

PA1_PA0

RW

32

0x0000 0000

0x0000 005C

0x4008 345C

IFADC0_ULNA

RW

32

0x0000 0000

0x0000 0060

0x4008 3460

IFADCLF_IFADC1

RW

32

0x0000 0000

0x0000 0064

0x4008 3464

IFADCALDO_IFADCQUANT

RW

32

0x0000 0000

0x0000 0068

0x4008 3468

IFADCTST_IFADCDLDO

RW

32

0x0000 0000

0x0000 006C

0x4008 346C

ATSTREF

RW

32

0x0000 0000

0x0000 0070

0x4008 3470

DIV_DCO

RW

32

0x0000 0000

0x0000 0074

0x4008 3474

TDCLDO_DIVLDO

RW

32

0x0000 0000

0x0000 0078

0x4008 3478

DCOLDO1_DCOLDO0

RW

32

0x0000 0000

0x0000 007C

0x4008 347C

PRE1_PRE0

RW

32

0x0000 0000

0x0000 0080

0x4008 3480

PRE3_PRE2

RW

32

0x0000 0000

0x0000 0084

0x4008 3484

CAL1_CAL0

RW

32

0x0000 0000

0x0000 0088

0x4008 3488

CAL3_CAL2

RW

32

0x0000 0000

0x0000 008C

0x4008 348C

MISC1_MISC0

RW

32

0x0000 0000

0x0000 0090

0x4008 3490

LF1_LF0

RW

32

0x0000 0000

0x0000 0094

0x4008 3494

PHINIT_PHEDISC

RW

32

0x0000 0000

0x0000 0098

0x4008 3498

PLLMON1_PLLMON0

RW

32

0x0000 0000

0x0000 009C

0x4008 349C

MOD1_MOD0

RW

32

0x0000 0000

0x0000 00A0

0x4008 34A0

DTX1_DTX0

RW

32

0x0000 0000

0x0000 00A4

0x4008 34A4

DTX3_DTX2

RW

32

0x0000 0000

0x0000 00A8

0x4008 34A8

DTX5_DTX4

RW

32

0x0000 0000

0x0000 00AC

0x4008 34AC

DTX7_DTX6

RW

32

0x0000 0000

0x0000 00B0

0x4008 34B0

DTX9_DTX8

RW

32

0x0000 0000

0x0000 00B4

0x4008 34B4

DTX11_DTX10

RW

32

0x0000 0000

0x0000 00B8

0x4008 34B8

PLLM0

RW

32

0x0000 0000

0x0000 00BC

0x4008 34BC

PLLM1

RW

32

0x0000 0000

0x0000 00C0

0x4008 34C0

CALMMID_CALMCRS

RW

32

0x0000 0000

0x0000 00C4

0x4008 34C4

REFDIV

RW

32

0x0000 0000

0x0000 00C8

0x4008 34C8

DLOCTL0

RW

32

0x0000 0000

0x0000 00CC

0x4008 34CC

DLOCTL1

RW

32

0x0000 0000

0x0000 00D0

0x4008 34D0

DCOOVR1_DCOOVR0

RW

32

0x0000 0000

0x0000 00D4

0x4008 34D4

DLOEV_DTST

RW

32

0x0000 0000

0x0000 00D8

0x4008 34D8

FDCOSPANLSB_DTSTRD

RO

32

0x0000 0000

0x0000 00DC

0x4008 34DC

TDCCAL_FDCOSPANMSB

RO

32

0x0000 0000

0x0000 00E0

0x4008 34E0

GPI_CALRES

RO

32

0x0000 0000

0x0000 00E4

0x4008 34E4

LIN2LOGOUT_MATHACCELIN

RW

32

0x0000 0000

0x0000 00E8

0x4008 34E8

TIMCTL_DIVBY3OUT

RO

32

0x0000 0000

0x0000 00EC

0x4008 34EC

TIMPER_TIMINC

RW

32

0x0000 0000

0x0000 00F0

0x4008 34F0

TIMCAPT_TIMCNT

RO

32

0x0000 0000

0x0000 00F4

0x4008 34F4

TRCSTAT_TRCCTRL

WO

32

0x0000 0000

0x0000 00F8

0x4008 34F8

TRCPAR0_TRCCMD

RW

32

0x0000 0000

0x0000 00FC

0x4008 34FC

GPOCTL_TRCPAR1

RW

32

0x0000 0000

0x0000 0100

0x4008 3500

DIVCTL_ANAISOCTL

RW

32

0x0000 000F

0x0000 0104

0x4008 3504

MAGNACC0_RXCTRL

RW

32

0x0000 0000

0x0000 0108

0x4008 3508

RSSI_MAGNACC1

RO

32

0x0000 0000

0x0000 010C

0x4008 350C

RFGAIN_RSSIMAX

RW

32

0x0000 0000

0x0000 0110

0x4008 3510

DIVSTA_IFADCSTAT

RO

32

0x0000 0000

0x0000 0114

0x4008 3514

DIVIDEND

WO

32

0x0000 0000

0x0000 0118

0x4008 3518

DIVISOR

RW

32

0x0000 0000

0x0000 011C

0x4008 351C

QUOTIENT

RO

32

0x0000 0000

0x0000 0120

0x4008 3520

PRODUCT

RO

32

0x0000 0000

0x0000 0124

0x4008 3524

MULTSTA

RO

32

0x0000 0000

0x0000 0128

0x4008 3528

MULTCFG

RW

32

0x0000 0000

0x0000 012C

0x4008 352C

TOP:LRFDRFE32 Register Descriptions

TOP:LRFDRFE32:FWSRC_ENABLE

Address Offset 0x0000 0000
Physical Address 0x4008 3400 Instance 0x4008 3400
Description Alias register for RFE_FWSRC_RFE_ENABLE
Type RW
Bits Field Name Description Type Reset
31:19 RESERVED19 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000 0000 0000
18 DATARAM
Value ENUM Name Description
0x0 RFERAM Use RFERAM for data
0x1 S2RRAM Use S2RRAM for data
RW 0
17 FWRAM
Value ENUM Name Description
0x0 RFERAM Run code from RFERAM
0x1 S2RRAM Run code from S2RRAM
RW 0
16 BANK
Value ENUM Name Description
0x0 ZERO Run code from bank 0
0x1 ONE Run code from bank 1
RW 0
15:4 RESERVED4 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x000
3 ACC1
Value ENUM Name Description
0x0 DIS Disable
0x1 EN Enable
RW 0
2 ACC0
Value ENUM Name Description
0x0 DIS Disable
0x1 EN Enable
RW 0
1 LOCTIM
Value ENUM Name Description
0x0 DIS Disable
0x1 EN Enable
RW 0
0 TOPSM
Value ENUM Name Description
0x0 DIS Disable
0x1 EN Enable
RW 0

TOP:LRFDRFE32:PDREQ_INIT

Address Offset 0x0000 0004
Physical Address 0x4008 3404 Instance 0x4008 3404
Description Alias register for RFE_PDREQ_RFE_INIT
Type WO
Bits Field Name Description Type Reset
31:17 RESERVED17 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000
16 TOPSMPDREQ
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RW 0
15:4 RESERVED4 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x000
3 ACC1
Value ENUM Name Description
0x0 NO_EFFECT No effect
0x1 RESET Reset module
WO 0
2 ACC0
Value ENUM Name Description
0x0 NO_EFFECT No effect
0x1 RESET Reset module
WO 0
1 LOCTIM
Value ENUM Name Description
0x0 NO_EFFECT No effect
0x1 RESET Reset module
WO 0
0 TOPSM
Value ENUM Name Description
0x0 NO_EFFECT No effect
0x1 RESET Reset module
WO 0

TOP:LRFDRFE32:EVT1_EVT0

Address Offset 0x0000 0008
Physical Address 0x4008 3408 Instance 0x4008 3408
Description Alias register for RFE_EVT1_RFE_EVT0
Type RO
Bits Field Name Description Type Reset
31:30 RESERVED30 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00
29 PREREFCLK
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
28 REFCLK
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
27 FBLWTHR
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
26 FABVTHR
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
25 LOCK
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
24 LOL
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
23 GPI7
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
22 GPI6
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
21 GPI5
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
20 GPI4
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
19 GPI3
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
18 GPI2
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
17 GPI1
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
16 GPI0
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
15 RESERVED15 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0
14 MAGNTHR
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
13 S2RSTOP
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
12 SYSTCMP2
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
11 SYSTCMP1
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
10 SYSTCMP0
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
9 PBERFEDAT
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
8 MDMRFEDAT
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
7 DLO
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
6 PBECMD
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
5 COUNTER
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
4 MDMCMD
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
3 ACC1
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
2 ACC0
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
1 TIMER
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
0 RFEAPI
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0

TOP:LRFDRFE32:EVTMSK1_EVTMSK0

Address Offset 0x0000 000C
Physical Address 0x4008 340C Instance 0x4008 340C
Description Alias register for RFE_EVTMSK1_RFE_EVTMSK0
Type RW
Bits Field Name Description Type Reset
31:30 RESERVED30 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00
29 PREREFCLK
Value ENUM Name Description
0x0 DIS The bit is 0
0x1 EN The bit is 1
RW 0
28 REFCLK
Value ENUM Name Description
0x0 DIS The bit is 0
0x1 EN The bit is 1
RW 0
27 FBLWTHR
Value ENUM Name Description
0x0 DIS The bit is 0
0x1 EN The bit is 1
RW 0
26 FABVTHR
Value ENUM Name Description
0x0 DIS The bit is 0
0x1 EN The bit is 1
RW 0
25 LOCK
Value ENUM Name Description
0x0 DIS The bit is 0
0x1 EN The bit is 1
RW 0
24 LOL
Value ENUM Name Description
0x0 DIS The bit is 0
0x1 EN The bit is 1
RW 0
23 GPI7
Value ENUM Name Description
0x0 DIS The bit is 0
0x1 EN The bit is 1
RW 0
22 GPI6
Value ENUM Name Description
0x0 DIS The bit is 0
0x1 EN The bit is 1
RW 0
21 GPI5
Value ENUM Name Description
0x0 DIS The bit is 0
0x1 EN The bit is 1
RW 0
20 GPI4
Value ENUM Name Description
0x0 DIS The bit is 0
0x1 EN The bit is 1
RW 0
19 GPI3
Value ENUM Name Description
0x0 DIS The bit is 0
0x1 EN The bit is 1
RW 0
18 GPI2
Value ENUM Name Description
0x0 DIS The bit is 0
0x1 EN The bit is 1
RW 0
17 GPI1
Value ENUM Name Description
0x0 DIS The bit is 0
0x1 EN The bit is 1
RW 0
16 GPI0
Value ENUM Name Description
0x0 DIS The bit is 0
0x1 EN The bit is 1
RW 0
15 RESERVED15 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0
14 MAGNTHR
Value ENUM Name Description
0x0 DIS The bit is 0
0x1 EN The bit is 1
RW 0
13 S2RSTOP
Value ENUM Name Description
0x0 DIS The bit is 0
0x1 EN The bit is 1
RW 0
12 SYSTCMP2
Value ENUM Name Description
0x0 DIS The bit is 0
0x1 EN The bit is 1
RW 0
11 SYSTCMP1
Value ENUM Name Description
0x0 DIS The bit is 0
0x1 EN The bit is 1
RW 0
10 SYSTCMP0
Value ENUM Name Description
0x0 DIS The bit is 0
0x1 EN The bit is 1
RW 0
9 PBERFEDAT
Value ENUM Name Description
0x0 DIS The bit is 0
0x1 EN The bit is 1
RW 0
8 MDMRFEDAT
Value ENUM Name Description
0x0 DIS The bit is 0
0x1 EN The bit is 1
RW 0
7 DLO
Value ENUM Name Description
0x0 DIS The bit is 0
0x1 EN The bit is 1
RW 0
6 PBECMD
Value ENUM Name Description
0x0 DIS The bit is 0
0x1 EN The bit is 1
RW 0
5 COUNTER
Value ENUM Name Description
0x0 DIS The bit is 0
0x1 EN The bit is 1
RW 0
4 MDMCMD
Value ENUM Name Description
0x0 DIS The bit is 0
0x1 EN The bit is 1
RW 0
3 ACC1
Value ENUM Name Description
0x0 DIS The bit is 0
0x1 EN The bit is 1
RW 0
2 ACC0
Value ENUM Name Description
0x0 DIS The bit is 0
0x1 EN The bit is 1
RW 0
1 TIMER
Value ENUM Name Description
0x0 DIS The bit is 0
0x1 EN The bit is 1
RW 0
0 RFEAPI
Value ENUM Name Description
0x0 DIS The bit is 0
0x1 EN The bit is 1
RW 0

TOP:LRFDRFE32:EVTCLR1_EVTCLR0

Address Offset 0x0000 0010
Physical Address 0x4008 3410 Instance 0x4008 3410
Description Alias register for RFE_EVTCLR1_RFE_EVTCLR0
Type WO
Bits Field Name Description Type Reset
31:30 RESERVED30 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00
29 PREREFCLK
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
WO 0
28 REFCLK
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
WO 0
27 FBLWTHR
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
WO 0
26 FABVTHR
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
WO 0
25 LOCK
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
WO 0
24 LOL
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
WO 0
23 GPI7
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
WO 0
22 GPI6
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
WO 0
21 GPI5
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
WO 0
20 GPI4
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
WO 0
19 GPI3
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
WO 0
18 GPI2
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
WO 0
17 GPI1
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
WO 0
16 GPI0
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
WO 0
15 RESERVED15 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0
14 MAGNTHR
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
WO 0
13 S2RSTOP
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
WO 0
12 SYSTCMP2
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
WO 0
11 SYSTCMP1
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
WO 0
10 SYSTCMP0
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
WO 0
9 PBERFEDAT
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
WO 0
8 MDMRFEDAT
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
WO 0
7 DLO
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
WO 0
6 PBECMD
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
WO 0
5 COUNTER
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
WO 0
4 MDMCMD
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
WO 0
3 ACC1
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
WO 0
2 ACC0
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
WO 0
1 TIMER
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
WO 0
0 RFEAPI
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
WO 0

TOP:LRFDRFE32:HFXTSTAT

Address Offset 0x0000 0014
Physical Address 0x4008 3414 Instance 0x4008 3414
Description Alias register for RFE_HFXTSTAT
Type RO
Bits Field Name Description Type Reset
31:1 RESERVED1 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000 0000 0000 0000
0 STAT
Value ENUM Name Description
0x0 NONQUAL Clock signal is not qualified
0x1 QUAL Clock signal is qualified
RO 0

TOP:LRFDRFE32:RFSTATE

Address Offset 0x0000 0018
Physical Address 0x4008 3418 Instance 0x4008 3418
Description Alias register for RFE_RFSTATE
Type RW
Bits Field Name Description Type Reset
31:4 RESERVED4 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x000 0000
3:0 VAL
Value ENUM Name Description
0x0 IDLE Radio is idle
0x1 SYNTH Synth is running
0x2 TX TX is active
0x3 RX RX is active
RW 0x0

TOP:LRFDRFE32:CMDPAR0_API

Address Offset 0x0000 0024
Physical Address 0x4008 3424 Instance 0x4008 3424
Description Alias register for RFE_CMDPAR0_RFE_API
Type RO
Bits Field Name Description Type Reset
31:16 VAL
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RO 0x0000
15:8 RESERVED8 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00
7:4 PROTOCOLID
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xF ALLONES All the bits are 1
RO 0x0
3:0 RFECMD
Value ENUM Name Description
0x0 ALLZEROS All bits are 0
0xF ALLONES All the bits are 1
RO 0x0

TOP:LRFDRFE32:MSGBOX_CMDPAR1

Address Offset 0x0000 0028
Physical Address 0x4008 3428 Instance 0x4008 3428
Description Alias register for RFE_MSGBOX_RFE_CMDPAR1
Type RO
Bits Field Name Description Type Reset
31:24 RESERVED24 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00
23:16 MSGBOX_VAL
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFF ALLONES All the bits are 1
RW 0x00
15:0 CMDPAR1_VAL
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RO 0x0000

TOP:LRFDRFE32:MCEDATIN0_MCEDATOUT0

Address Offset 0x0000 002C
Physical Address 0x4008 342C Instance 0x4008 342C
Description Alias register for RFE_MCEDATIN0_RFE_MCEDATOUT0
Type RW
Bits Field Name Description Type Reset
31:16 MCEDATIN0_VAL
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RO 0x0000
15:0 MCEDATOUT0_VAL
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RW 0x0000

TOP:LRFDRFE32:MCECMDIN_MCECMDOUT

Address Offset 0x0000 0030
Physical Address 0x4008 3430 Instance 0x4008 3430
Description Alias register for RFE_MCECMDIN_RFE_MCECMDOUT
Type RW
Bits Field Name Description Type Reset
31:20 RESERVED20 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x000
19:16 MCECMDIN_VAL
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xF ALLONES All the bits are 1
RO 0x0
15:4 RESERVED4 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x000
3:0 MCECMDOUT_VAL
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xF ALLONES All the bits are 1
RW 0x0

TOP:LRFDRFE32:PBEDATIN0_PBEDATOUT0

Address Offset 0x0000 0034
Physical Address 0x4008 3434 Instance 0x4008 3434
Description Alias register for RFE_PBEDATIN0_RFE_PBEDATOUT0
Type RW
Bits Field Name Description Type Reset
31:16 PBEDATIN0_VAL
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RO 0x0000
15:0 PBEDATOUT0_VAL
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RW 0x0000

TOP:LRFDRFE32:PBECMDIN_PBECMDOUT

Address Offset 0x0000 0038
Physical Address 0x4008 3438 Instance 0x4008 3438
Description Alias register for RFE_PBECMDIN_RFE_PBECMDOUT
Type RW
Bits Field Name Description Type Reset
31:20 RESERVED20 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x000
19:16 PBECMDIN_VAL
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xF ALLONES All the bits are 1
RO 0x0
15:4 RESERVED4 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x000
3:0 PBECMDOUT_VAL
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xF ALLONES All the bits are 1
RW 0x0

TOP:LRFDRFE32:STRB

Address Offset 0x0000 003C
Physical Address 0x4008 343C Instance 0x4008 343C
Description Alias register for RFE_STRB
Type WO
Bits Field Name Description Type Reset
31:8 RESERVED8 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00 0000
7 S2RTRG
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
WO 0
6 DMATRG
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
WO 0
5 SYSTCPT2
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
WO 0
4 SYSTCPT1
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
WO 0
3 SYSTCPT0
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
WO 0
2 EVT1
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
WO 0
1 EVT0
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
WO 0
0 CMDDONE
Value ENUM Name Description
0x0 NO The bit is 0
0x1 YES The bit is 1
WO 0

TOP:LRFDRFE32:MAGNTHR_MAGNTHRCFG

Address Offset 0x0000 0040
Physical Address 0x4008 3440 Instance 0x4008 3440
Description Alias register for RFE_MAGNTHR_RFE_MAGNTHRCFG
Type RW
Bits Field Name Description Type Reset
31:24 RESERVED24 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00
23:16 VAL
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFF ALLONES All the bits are 1
RW 0x00
15:2 RESERVED2 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000 0000
1 SEL
Value ENUM Name Description
0x0 MAGNACC0 Use MAGNACC0 in the compare against the theshold in MANGTHR
0x1 MAGNACC1 Use MAGNACC1 in the compare against the theshold in MANGTHR
RW 0
0 CTL
Value ENUM Name Description
0x0 DIS Disable automatic comparison with threshold (input of lin2log is driven by FW)
0x1 EN Enable automatic comparison of magntude with threshold (input of lin2log is driven by HW)
RW 0

TOP:LRFDRFE32:GAINCTL_RSSIOFFSET

Address Offset 0x0000 0044
Physical Address 0x4008 3444 Instance 0x4008 3444
Description Alias register for RFE_GAINCTL_RFE_RSSIOFFSET
Type RW
Bits Field Name Description Type Reset
31:20 RESERVED20 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x000
19:18 BDE2DVGA
Value ENUM Name Description
0x0 GAIN1 Gain 1
0x1 GAIN2 Gain 2
0x2 GAIN4 Gain 4
0x3 GAIN8 Gain 8
RW 0b00
17:16 BDE1DVGA
Value ENUM Name Description
0x0 GAIN1 Gain 1
0x1 GAIN2 Gain 2
0x2 GAIN4 Gain 4
0x3 GAIN8 Gain 8
RW 0b00
15:8 RESERVED8 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00
7:0 VAL
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFF ALLONES All the bits are 1
RW 0x00

TOP:LRFDRFE32:MAGNCTL1_MAGNCTL0

Address Offset 0x0000 0048
Physical Address 0x4008 3448 Instance 0x4008 3448
Description Alias register for RFE_MAGNCTL1_RFE_MAGNCTL0
Type RW
Bits Field Name Description Type Reset
31:29 RESERVED29 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000
28 MAGNCTL1_PERMODE
Value ENUM Name Description
0x0 ONESHOT One-shot mode
0x1 PERIODIC Periodic mode
RW 0
27:24 MAGNCTL1_SCL
Value ENUM Name Description
0x0 DIV1 1/1 (no scaling)
0x1 DIV2 1/2
0x2 DIV4 1/4
0x3 DIV8 1/8
0x4 DIV16 1/16
0x5 DIV32 1/32
0x6 DIV64 1/64
0x7 DIV128 1/128
0x8 DIV256 1/256
RW 0x0
23:16 MAGNCTL1_PER
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFF ALLONES All the bits are 1
RW 0x00
15:13 RESERVED13 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000
12 MAGNCTL0_PERMODE
Value ENUM Name Description
0x0 ONESHOT One-shot mode
0x1 PERIODIC Periodic mode
RW 0
11:8 MAGNCTL0_SCL
Value ENUM Name Description
0x0 DIV1 1/1 (no scaling)
0x1 DIV2 1/2
0x2 DIV4 1/4
0x3 DIV8 1/8
0x4 DIV16 1/16
0x5 DIV32 1/32
0x6 DIV64 1/64
0x7 DIV128 1/128
0x8 DIV256 1/256
RW 0x0
7:0 MAGNCTL0_PER
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFF ALLONES All the bits are 1
RW 0x00

TOP:LRFDRFE32:SPARE1_SPARE0

Address Offset 0x0000 004C
Physical Address 0x4008 344C Instance 0x4008 344C
Description Alias register for RFE_SPARE1_RFE_SPARE0
Type RW
Bits Field Name Description Type Reset
31:16 SPARE1_VAL
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RW 0x0000
15:0 SPARE0_VAL
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RW 0x0000

TOP:LRFDRFE32:SPARE3_SPARE2

Address Offset 0x0000 0050
Physical Address 0x4008 3450 Instance 0x4008 3450
Description Alias register for RFE_SPARE3_RFE_SPARE2
Type RW
Bits Field Name Description Type Reset
31:16 SPARE3_VAL
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RW 0x0000
15:0 SPARE2_VAL
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RW 0x0000

TOP:LRFDRFE32:SPARE5_SPARE4

Address Offset 0x0000 0054
Physical Address 0x4008 3454 Instance 0x4008 3454
Description Alias register for RFE_SPARE5_RFE_SPARE4
Type RW
Bits Field Name Description Type Reset
31:16 SPARE5_VAL
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RW 0x0000
15:0 SPARE4_VAL
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RW 0x0000

TOP:LRFDRFE32:IFAMPRFLDO_LNA

Address Offset 0x0000 0058
Physical Address 0x4008 3458 Instance 0x4008 3458
Description Alias register for RFE_IFAMPRFLDO_RFE_LNA
Type RW
Bits Field Name Description Type Reset
31:25 IFAMPRFLDO_TRIM
Value ENUM Name Description
0x0 MIN Minimum output voltage
0x7E MAX Maximum output voltage
0x7F BYPASS Regulator is in bypass mode
RW 0b000 0000
24 IFAMPRFLDO_EN
Value ENUM Name Description
0x0 DIS Disable regulator
0x1 EN Enable regulator
RW 0
23:20 IFAMPRFLDO_AAFCAP
Value ENUM Name Description
0x0 MIN Smallest capacitance on IFAMP output. High BW.
0xF MAX Largest capacitance on IFAMP output. Low BW
RW 0x0
19:17 IFAMPRFLDO_IFAMPIB
Value ENUM Name Description
0x0 MIN Minimum IB
0x7 MAX Max IB
RW 0b000
16 IFAMPRFLDO_IFAMP
Value ENUM Name Description
0x0 DIS Disable IFAMP
0x1 EN Enable IFAMP
RW 0
15:8 LNA_SPARE
Value ENUM Name Description
0x0 DIS Disable IFAMP
0x1 EN Enable IFAMP
RW 0x00
7:4 LNA_TRIM
Value ENUM Name Description
0x0 ZEROS All bits are zero
0xF ONES All bits are one
RW 0x0
3 LNA_BIAS
Value ENUM Name Description
0x0 BGAP IPTAT bias currents are from bandgap
0x1 INT IPTAT bias currents are from bias circuit inside LRF_FRONTEND
RW 0
2:1 LNA_IB
Value ENUM Name Description
0x0 MIN Minimum IB
0x3 MAX Maximum IB
RW 0b00
0 LNA_EN
Value ENUM Name Description
0x0 OFF Disable LNA
0x1 ON Enable LNA
RW 0

TOP:LRFDRFE32:PA1_PA0

Address Offset 0x0000 005C
Physical Address 0x4008 345C Instance 0x4008 345C
Description Alias register for RFE_PA1_RFE_PA0
Type RW
Bits Field Name Description Type Reset
31:23 SPARE
Value ENUM Name Description
0x0 MIN Shortest ramp time
0x3 MAX Longest ramp time
RW 0b0 0000 0000
22 MIXATST
Value ENUM Name Description
0x0 DIS Mixers are not available on ATEST
0x1 EN Mixers are available on ATEST
RW 0
21 LDOITST
Value ENUM Name Description
0x0 DIS Current test signal not available through ITEST
0x1 EN Current test signal is available through ITEST
RW 0
20 LDOATST
Value ENUM Name Description
0x0 DIS LDO output voltage not available through ATEST
0x1 EN LDO output voltage is available through ATEST
RW 0
19:18 RC
Value ENUM Name Description
0x0 MIN Shortest ramp time
0x3 MAX Longest ramp time
RW 0b00
17 RAMP
Value ENUM Name Description
0x0 DOWN Ramp down
0x1 UP Ramp up
RW 0
16 EN
Value ENUM Name Description
0x0 DIS Disable PA
0x1 EN Enable PA
RW 0
15 SPARE15
Value ENUM Name Description
0x0 ZERO Bit is 0
0x1 ONE Bit is one
RW 0
14 MODE
Value ENUM Name Description
0x0 LOW Low power mode, max 3 dBm
0x1 HIGH High power mode, max 8 dBm
RW 0
13:11 GAIN
Value ENUM Name Description
0x0 MIN Minimum gain
0x7 MAX Maximum gain
RW 0b000
10:5 IB
Value ENUM Name Description
0x0 MIN Minimum output power
0x3F MAX Maximum output power
RW 0b00 0000
4:0 TRIM
Value ENUM Name Description
0x0 MIN Minimum bias current
0x1F MAX Maximum bias current
RW 0b0 0000

TOP:LRFDRFE32:IFADC0_ULNA

Address Offset 0x0000 0060
Physical Address 0x4008 3460 Instance 0x4008 3460
Description Alias register for RFE_IFADC0_RFE_ULNA
Type RW
Bits Field Name Description Type Reset
31 EXTCLK
Value ENUM Name Description
0x0 DIS The bit is 0
0x1 EN The bit is 1
RW 0
30:28 DITHERTRIM
Value ENUM Name Description
0x0 ZEROS All the bits are 0
0x7 ONES All the bits are 1
RW 0b000
27:26 DITHEREN
Value ENUM Name Description
0x0 DIS All the bits are 0
0x1 ENS All the bits are 1
0x2 ENSD All the bits are 1
0x3 ENG All the bits are 1
RW 0b00
25 ADCIEN
Value ENUM Name Description
0x0 DIS The bit is 0
0x1 EN The bit is 1
RW 0
24 ADCQEN
Value ENUM Name Description
0x0 DIS The bit is 0
0x1 EN The bit is 1
RW 0
23:20 INT2ADJ
Value ENUM Name Description
0x0 ZEROS All the bits are 0
0xF ONES All the bits are 1
RW 0x0
19:18 AAFCAP
Value ENUM Name Description
0x0 DIS All the bits are 0
0x1 ENS All the bits are 1
0x2 ENSD All the bits are 1
0x3 ENG All the bits are 1
RW 0b00
17:16 RESERVED
Value ENUM Name Description
0x0 ZEROS All the bits are 0
0x3 ONES All the bits are 1
RW 0b00
15:0 SPARE
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RW 0x0000

TOP:LRFDRFE32:IFADCLF_IFADC1

Address Offset 0x0000 0064
Physical Address 0x4008 3464 Instance 0x4008 3464
Description Alias register for RFE_IFADCLF_RFE_IFADC1
Type RW
Bits Field Name Description Type Reset
31:28 FF3
Value ENUM Name Description
0x0 ZEROS All the bits are 0
0xF ONES All the bits are 1
RW 0x0
27:24 FF2
Value ENUM Name Description
0x0 ZEROS All the bits are 0
0xF ONES All the bits are 1
RW 0x0
23:20 FF1
Value ENUM Name Description
0x0 ZEROS All the bits are 0
0xF ONES All the bits are 1
RW 0x0
19:16 INT3
Value ENUM Name Description
0x0 ZEROS All the bits are 0
0xF ONES All the bits are 1
RW 0x0
15 NRZ
Value ENUM Name Description
0x0 DIS The feedback DAC uses RZ mode
0x1 EN The feedback DAC uses NRZ mode. (Default)
RW 0
14:9 TRIM
Value ENUM Name Description
0x0 ZEROS All the bits are 0
0x3F ONES All the bits are 1
RW 0b00 0000
8 RESERVED8
Value ENUM Name Description
0x0 DIS The bit is 0
0x1 EN The bit is 1
RW 0
7 RSTN
Value ENUM Name Description
0x0 EN DTCs are reset
0x1 DIS DTCs are not reset
RW 0
6 CLKGEN
Value ENUM Name Description
0x0 DIS Internal clock generator module is disabled
0x1 EN Internal clock generator module is enabled
RW 0
5 ADCDIGCLK
Value ENUM Name Description
0x0 DIS Clock to decimator disabled
0x1 EN Clock to decimator enabled
RW 0
4 ADCLFSROUT
Value ENUM Name Description
0x0 DIS The quantizer output is connected to the ADC output
0x1 EN The LFSR test output is connected to the ADC output
RW 0
3:1 LPFTSTMODE
Value ENUM Name Description
0x0 DIS All the bits are 0
0x1 EN All the bits are 1
RW 0b000
0 INVCLKOUT
Value ENUM Name Description
0x0 DIS Keep default IFADC output clock phase
0x1 EN Invert IFADC output clock phase (default)
RW 0

TOP:LRFDRFE32:IFADCALDO_IFADCQUANT

Address Offset 0x0000 0068
Physical Address 0x4008 3468 Instance 0x4008 3468
Description Alias register for RFE_IFADCALDO_RFE_IFADCQUANT
Type RW
Bits Field Name Description Type Reset
31 ATESTVSSANA
Value ENUM Name Description
0x0 DIS Not connected
0x1 EN Connected
RW 0
30 RESERVED
Value ENUM Name Description
0x0 ZEROS All the bits are 0
0x1 ONES All the bits are ONES
RW 0
29:24 TRIMOUT
Value ENUM Name Description
0x0 ZEROS All the bits are zero
0x3F ONES All the bits are one
RW 0b00 0000
23 DUMMY
Value ENUM Name Description
0x0 DIS Disabled
0x1 EN Enabled
RW 0
22 ATESTOUT
Value ENUM Name Description
0x0 DIS Disabled
0x1 EN Enabled
RW 0
21 ATSTLDOFB
Value ENUM Name Description
0x0 DIS Disabled
0x1 EN Enabled
RW 0
20 ATESTERRAMP
Value ENUM Name Description
0x0 DIS Disabled
0x1 EN Enabled
RW 0
19 ITEST
Value ENUM Name Description
0x0 DIS Disabled
0x1 EN Enabled
RW 0
18 BYPASS
Value ENUM Name Description
0x0 DIS Disabled
0x1 EN Enabled
RW 0
17 CLAMP
Value ENUM Name Description
0x0 DIS Disabled. The LDO output is shorted to ground when disabled.
0x1 EN Enabled
RW 0
16 CTL
Value ENUM Name Description
0x0 DIS Disabled
0x1 EN Enabled
RW 0
15:14 CLKDLYTRIM
Value ENUM Name Description
0x0 ZEROS All the bits are zero
0x3 ONES All the bits are one
RW 0b00
13:9 DBGCALVALIN
Value ENUM Name Description
0x0 ZEROS All the bits are 0
0x1F ONES All the bits are ONES
RW 0b0 0000
8 DBGCALLEG
Value ENUM Name Description
0x0 POS Positive leg
0x1 NEG Negative leg
RW 0
7:6 DBGCALMQ
Value ENUM Name Description
0x0 DBGCAL_QMODZ Disable quantizer calibration mode.(Default)
0x1 DBGCAL_QMODN Enable quantizer calibration mode for Negative comparator in Q modulator.
0x2 DBGCAL_QMODP Enable quantizer calibration mode for Positive comparator in Q modulator.
0x3 DBGCAL_QMODB UNCLEAR_Enable quantizer calibration mode.
RW 0b00
5:4 DBGCALMI
Value ENUM Name Description
0x0 DBGCAL_IMODZ Disable quantizer calibration mode.(Default)
0x1 DBGCAL_IMODN Enable quantizer calibration mode for Negative comparator in I modulator.
0x2 DBGCAL_IMODP Enable quantizer calibration mode for Positive comparator in I modulator.
0x3 DBGCAL_IMODB UNCLEAR_Enable quantizer calibration mode.
RW 0b00
3 AUTOCAL
Value ENUM Name Description
0x0 DIS Disable the auto calibration logic
0x1 EN Enable the auto calibration logic (Default)
RW 0
2:0 QUANTTHR
Value ENUM Name Description
0x0 ZEROS All the bits are 0
0x7 ONES All the bits are 1
RW 0b000

TOP:LRFDRFE32:IFADCTST_IFADCDLDO

Address Offset 0x0000 006C
Physical Address 0x4008 346C Instance 0x4008 346C
Description Alias register for RFE_IFADCTST_RFE_IFADCDLDO
Type RW
Bits Field Name Description Type Reset
31:24 RESERVED24 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00
23 EXTCURR
Value ENUM Name Description
0x0 DIS Disabled
0x1 EN Enabled
RW 0
22 QCALDBIQ
Value ENUM Name Description
0x0 COMP0 Q Comparator
0x1 COMP1 I comparator
RW 0
21 QCALDBC
Value ENUM Name Description
0x0 COMP0 Q Comparator
0x1 COMP1 I comparator
RW 0
20:16 SEL
Value ENUM Name Description
0x0 NONE ADC_TEST_P and ADC_TEST_N tristated (Default)
0x1F EXTCLKN1 External ADC clock through ADC_TEST_N (N1 internally). The the clock should be a 200MHz sine wave (it is divided internally to 100MHz).
RW 0b0 0000
15:14 RESERVED
Value ENUM Name Description
0x0 ZEROS All the bits are 0
0x3 ONES All the bits are ONES
RW 0b00
13:8 TRIMOUT
Value ENUM Name Description
0x0 ZEROS All the bits are zero
0x3F ONES All the bits are one
RW 0b00 0000
7 DUMMY
Value ENUM Name Description
0x0 DIS Disabled
0x1 EN Enabled
RW 0
6 ATESTOUT
Value ENUM Name Description
0x0 DIS Disabled
0x1 EN Enabled
RW 0
5 ATSTBGP
Value ENUM Name Description
0x0 DIS Disabled
0x1 EN Enabled
RW 0
4 ATESTERRAMP
Value ENUM Name Description
0x0 DIS Disabled
0x1 EN Enabled
RW 0
3 ITEST
Value ENUM Name Description
0x0 DIS Disabled
0x1 EN Enabled
RW 0
2 BYPASS
Value ENUM Name Description
0x0 DIS Disabled
0x1 EN Enabled
RW 0
1 CLAMP
Value ENUM Name Description
0x0 DIS Disabled. The LDO output is shorted to ground when disabled.
0x1 EN Enabled
RW 0
0 CTL
Value ENUM Name Description
0x0 DIS Disabled
0x1 EN Enabled
RW 0

TOP:LRFDRFE32:ATSTREF

Address Offset 0x0000 0070
Physical Address 0x4008 3470 Instance 0x4008 3470
Description Alias register for RFE_ATSTREFH_RFE_ATSTREFL
Type RW
Bits Field Name Description Type Reset
31 VREFBPDIS
Value ENUM Name Description
0x0 BPEN Bandgap reference bypass enabled.
0x1 BPDIS Bandgap reference bypass disabled
RW 0
30:26 IREFTRIM
Value ENUM Name Description
0x0 ZEROS All bits are zero
0x1F ONES All bits are ones
RW 0b0 0000
25 BIAS
Value ENUM Name Description
0x0 DIS Disabled
0x1 EN Enabled
RW 0
24 OUTPUT2
Value ENUM Name Description
0x0 DIS Output is disabled
0x1 EN The output is enabled
RW 0
23 OUTPUT1
Value ENUM Name Description
0x0 DIS Output is disabled
0x1 EN The output is enabled
RW 0
22:0 MUX
Value ENUM Name Description
0x0 DIS No atest selected
0x1 FE_OUTIP Frontend IF outip, voltage
0x2 FE_OUTIN Frontend IF outin, voltage
0x4 FE_OUTQP Frontend IF outqp, voltage
0x8 FE_OUTQN Frontend IF outqn, voltage
0x10 FE_OUTIP_2 Frontend IF outip, voltage
0x20 FE_OUTIN_2 Frontend IF outin, voltage
0x40 MIX_OUTIP MIX outip, voltage
0x80 MIX_OUTIN MIX outin, voltage
0x100 MIX_OUTQP MIX outqp, voltage
0x200 MIX_OUTQN MIX outqn, voltage
0x400 PA_PEAK_OUTP PA peak detector output p
0x800 PA_PEAK_OUTN PA peak detector output n
0x2000 LDO_ITEST LDO_ITEST itest out, current
0x4000 LDO_VTEST LDO_VTEST vtest out, current
0x8000 IFADC_ATB IFADC ATB
RW 0b000 0000 0000 0000 0000 0000

TOP:LRFDRFE32:DIV_DCO

Address Offset 0x0000 0074
Physical Address 0x4008 3474 Instance 0x4008 3474
Description Alias register for RFE_DIV_RFE_DCO
Type RW
Bits Field Name Description Type Reset
31 PDET
Value ENUM Name Description
0x0 DIS Peak detector mode disabled, normal functional mode
0x1 EN Peak detektor mode enabled, used in production test
RW 0
30:28 NMIREFTRIM
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0x7 ALLONES All the bits are 1
RW 0b000
27:25 PMIREFTRIM
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0x7 ALLONES All the bits are 1
RW 0b000
24 TXBBOOST
Value ENUM Name Description
0x0 DEFAULT Default drive strength
0x1 INCREASED High drive strength
RW 0
23 S1GFRC
Value ENUM Name Description
0x0 DIS Disable force S1G power switch
0x1 EN Enable force S1G power switch
RW 0
22:21 BUFGAIN
Value ENUM Name Description
0x0 MAX Maximum gain (default)
0x1 _80_PST 80% of maximum gain
0x2 DONT_USE Same as _80_PST
0x3 _60_PST 60% of maximum gain
RW 0b00
20 BIAS
Value ENUM Name Description
0x0 ALTERNATIVE Alternative bias (for test purposes)
0x1 DEFAULT Default bias
RW 0
19 OUT
Value ENUM Name Description
0x0 FE_S1G Enable outputs going to sub-1GHz front-end
0x1 FE_2G4 Enable outputs going to 2.4GHz front-end
RW 0
18:16 RATIO
Value ENUM Name Description
0x0 DIV2 DIVIDER = 2
0x1 DIV4 DIVIDER = 4 (for test purposes only)
0x2 DIV6 DIVIDER = 6
0x3 DIV12 DIVIDER = 12
0x4 DIV5 DIVIDER = 5
0x5 DIV10 DIVIDER = 10
0x6 DIV15 DIVIDER = 15
0x7 DIV30 DIVIDER = 30
RW 0b000
15:11 RESERVED11 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000
10:9 MTDCSPARE
Value ENUM Name Description
0x0 EN DIVIDER = 2
0x1 DIS DIVIDER = 4 (for test purposes only)
RW 0b00
8:7 SPARE7
Value ENUM Name Description
0x0 ZERO Bit is zero
0x1 ONE Bit is one
RW 0b00
6:3 TAILRESTRIM
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xF ALLONES All the bits are 1
RW 0x0
2 RTRIMCAP
Value ENUM Name Description
0x0 DIS Disable(default)
0x1 EN Enable
RW 0
1 CNRCAP
Value ENUM Name Description
0x0 DEFAULT Default
0x1 _50MHZ 50 MHz
RW 0
0 CRSCAPCM
Value ENUM Name Description
0x0 DEFAULT Default
0x1 REDUCED Reduced common mode for greater reliability
RW 0

TOP:LRFDRFE32:TDCLDO_DIVLDO

Address Offset 0x0000 0078
Physical Address 0x4008 3478 Instance 0x4008 3478
Description Alias register for RFE_TDCLDO_RFE_DIVLDO
Type RW
Bits Field Name Description Type Reset
31 TDCLDO_ITESTCTL
Value ENUM Name Description
0x0 DIS ITEST Disabled
0x1 EN ITEST enabled
RW 0
30:24 TDCLDO_VOUTTRIM
Value ENUM Name Description
0x0 ZEROS All bits are zero
0x7F ONES All bits are one
RW 0b000 0000
23 TDCLDO_ITESTBUFCTL
Value ENUM Name Description
0x0 DIS ITEST mode in buffer is disabled
0x1 EN ITEST mode in buffer is enabled
RW 0
22:20 TDCLDO_TMUX
Value ENUM Name Description
0x0 OFF Normal mode
0x1 VDDA ATEST output is VDDA
0x2 LDO_OUT ATEST output is LDO output
0x4 VSSA ATEST output is VSSA
RW 0b000
19 TDCLDO_PDSEL
Value ENUM Name Description
0x0 R R (default)
0x1 DIODE Diode stack
RW 0
18 TDCLDO_MODE
Value ENUM Name Description
0x0 NORM Regular low bandwidth of LDO
0x1 FAST Regulator in high bandwidth mode
RW 0
17 TDCLDO_BYPASS
Value ENUM Name Description
0x0 DIS No bypass
0x1 EN Regulator is bypassed
RW 0
16 TDCLDO_CTL
Value ENUM Name Description
0x0 DIS Regulator is disabled
0x1 EN Regulator is enabled
RW 0
15 DIVLDO_SPARE15
Value ENUM Name Description
0x0 ZEROS All bits are zero
0x1 ONES All bits are one
RW 0
14:8 DIVLDO_VOUTTRIM
Value ENUM Name Description
0x0 ZEROS All bits are zero
0x7F ONES All bits are one
RW 0b000 0000
7 DIVLDO_ITST
Value ENUM Name Description
0x0 DIS Regulator is disabled
0x1 EN Regulator is enabled
RW 0
6:4 DIVLDO_TMUX
Value ENUM Name Description
0x0 OFF Normal mode
0x1 GND ATEST output is grounded
0x2 LDO_OUT ATEST output is LDO output
0x4 VDDR ATEST output is VDDR
RW 0b000
3 DIVLDO_SPARE3
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RW 0
2 DIVLDO_MODE
Value ENUM Name Description
0x0 NORM Regular low bandwidth of LDO
0x1 FAST Regulator in high bandwidth mode
RW 0
1 DIVLDO_BYPASS
Value ENUM Name Description
0x0 DIS No bypass
0x1 EN Regulator is bypassed
RW 0
0 DIVLDO_CTL
Value ENUM Name Description
0x0 DIS Regulator is disabled
0x1 EN Regulator is enabled
RW 0

TOP:LRFDRFE32:DCOLDO1_DCOLDO0

Address Offset 0x0000 007C
Physical Address 0x4008 347C Instance 0x4008 347C
Description Alias register for RFE_DCOLDO1_RFE_DCOLDO0
Type RW
Bits Field Name Description Type Reset
31:27 RESERVED27 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000
26 REFSRC
Value ENUM Name Description
0x0 XTAL PLL clock source is XTAL
0x1 BAW PLL clock source is BAW
RW 0
25:24 DIVATST
Value ENUM Name Description
0x0 ZEROS All bits are zero
0x3 ONES All bits are one
RW 0b00
23 PERFM
Value ENUM Name Description
0x0 DIS Disabled (normal)
0x1 EN Enabled (performance)
RW 0
22 CHRGFILT
Value ENUM Name Description
0x0 DIS Charging disabled, normal operation
0x1 EN Charging enabled
RW 0
21:16 ATST
Value ENUM Name Description
0x0 LDO_OUT LDO output
0x1 FIRST_OUT First LDO output
0x20 VSSANA VSSANA
RW 0b00 0000
15:14 ITST
Value ENUM Name Description
0x0 DIS Regulator is disabled
0x1 FIRST Enable first pass transistor
0x2 SECOND Enable second pass transistor
0x3 BOTH Enable both pass transistors
RW 0b00
13:8 SECONDTRIM
Value ENUM Name Description
0x0 ZEROS All bits are zero
0x3F ONES All bits are one
RW 0b00 0000
7:4 FIRSTTRIM
Value ENUM Name Description
0x0 ZEROS All bits are zero
0xF ONES All bits are one
RW 0x0
3 PDN
Value ENUM Name Description
0x0 DIS No Pulldown
0x1 EN Pulldown
RW 0
2 BYPFIRST
Value ENUM Name Description
0x0 DIS No bypass
0x1 EN Regulator is bypassed
RW 0
1 BYPBOTH
Value ENUM Name Description
0x0 DIS No bypass
0x1 EN Regulator is bypassed
RW 0
0 CTL
Value ENUM Name Description
0x0 DIS Regulator is disabled
0x1 EN Regulator is enabled
RW 0

TOP:LRFDRFE32:PRE1_PRE0

Address Offset 0x0000 0080
Physical Address 0x4008 3480 Instance 0x4008 3480
Description Alias register for RFE_PRE1_RFE_PRE0
Type RW
Bits Field Name Description Type Reset
31:30 IIRBW
Value ENUM Name Description
0x0 K2 K=2
0x1 K4 K=4
0x2 K8 K=8
0x3 K16 K=16
RW 0b00
29 IIRORD
Value ENUM Name Description
0x0 FIRST Select first order IIR filter
0x1 SECOND Select second order IIR filter
RW 0
28:24 IIRDIV
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0x1F ALLONES All the bits are 1
RW 0b0 0000
23 RESERVED23 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0
22 CALHSDDC
Value ENUM Name Description
0x0 NOGATE No duty-cycling
0x1 GATE Duty-cycling given by HSDDC
RW 0
21:16 HSDDC
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0x3F ALLONES All the bits are 1
RW 0b00 0000
15:14 SPARE14
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0x3 ALLONES All the bits are 1
RW 0b00
13:8 PLLDIV1
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0x3F ALLONES All the bits are 1
RW 0b00 0000
7:6 SPARE6
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0x3 ALLONES All the bits are 1
RW 0b00
5:0 PLLDIV0
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0x3F ALLONES All the bits are 1
RW 0b00 0000

TOP:LRFDRFE32:PRE3_PRE2

Address Offset 0x0000 0084
Physical Address 0x4008 3484 Instance 0x4008 3484
Description Alias register for RFE_PRE3_RFE_PRE2
Type RW
Bits Field Name Description Type Reset
31:21 FINECALDIV
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0x7FF ALLONES All the bits are 1
RW 0b000 0000 0000
20:16 MIDCALDIVMSB
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0x1F ALLONES All the bits are 1
RW 0b0 0000
15:12 MIDCALDIVLSB
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xF ALLONES All the bits are 1
RW 0x0
11:6 CRSCALDIV
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0x3F ALLONES All the bits are 1
RW 0b00 0000
5:0 FSMDIV
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0x3F ALLONES All the bits are 1
RW 0b00 0000

TOP:LRFDRFE32:CAL1_CAL0

Address Offset 0x0000 0088
Physical Address 0x4008 3488 Instance 0x4008 3488
Description Alias register for RFE_CAL1_RFE_CAL0
Type RW
Bits Field Name Description Type Reset
31 CAL1_SPARE15
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RW 0
30:24 CAL1_FCTOP
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0x7F ALLONES All the bits are 1
RW 0b000 0000
23 CAL1_SPARE7
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RW 0
22:16 CAL1_FCBOT
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0x7F ALLONES All the bits are 1
RW 0b000 0000
15 CAL0_SPARE15
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RW 0
14:8 CAL0_FCSTART
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0x7F ALLONES All the bits are 1
RW 0b000 0000
7 CAL0_CRS
Value ENUM Name Description
0x0 DIS Disable coarse calibration
0x1 EN Enable coarse calibration
RW 0
6 CAL0_MID
Value ENUM Name Description
0x0 DIS Disable mid calibration
0x1 EN Enable mid calibration
RW 0
5 CAL0_KTDC
Value ENUM Name Description
0x0 DIS Disable TDC estimation
0x1 EN Enable TDC estimation
RW 0
4 CAL0_KDCO
Value ENUM Name Description
0x0 DIS Disable KDCO estimation
0x1 EN Enable KDCO estimation
RW 0
3:2 CAL0_TDCAVG
Value ENUM Name Description
0x0 REPEAT_1_TIME Repeat measurement 1 time
0x1 REPEAT_2_TIMES Repeat measurement 2 times
0x2 REPEAT_4_TIMES Repeat measurement 4 times
0x3 REPEAT_8_TIMES Repeat measurement 8 times
RW 0b00
1:0 CAL0_TDC_SPARE
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0x3 ALLONES All the bits are 1
RW 0b00

TOP:LRFDRFE32:CAL3_CAL2

Address Offset 0x0000 008C
Physical Address 0x4008 348C Instance 0x4008 348C
Description Alias register for RFE_CAL3_RFE_CAL2
Type RW
Bits Field Name Description Type Reset
31:16 DTXGAIN
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RW 0x0000
15:0 KTDCINV
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RW 0x0000

TOP:LRFDRFE32:MISC1_MISC0

Address Offset 0x0000 0090
Physical Address 0x4008 3490 Instance 0x4008 3490
Description Alias register for RFE_MISC1_RFE_MISC0
Type RW
Bits Field Name Description Type Reset
31 RESERVED31 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0
30 FCDEMCLK
Value ENUM Name Description
0x0 CKCD16 ckvd16 clock used for update upper and lower DWA DEM
0x1 CKVD64 ckvd64 clock used for update upper and lower DWA DEM
RW 0
29:28 FCDEMUPD
Value ENUM Name Description
0x0 DEFAULT Default: Update both DWAs always at rising edge of selected clock
0x1 PH_ERR phase_error[0]. (Phase error is 6.11s )
0x2 SDM SDM[1] (this value depends on DEM for SDM)
0x3 SDM_XOR_PH_ERR phase_error[0] xor SDM[1]
RW 0b00
27:22 TDCINL
Value ENUM Name Description
0x0 ZEROS All bits are zero
0x3F ONES All bits are one
RW 0b00 0000
21 TDCINLCTL
Value ENUM Name Description
0x0 DIS Disabled INL correction
0x1 EN Enables INL correction of TDC
RW 0
20 PHINIT
Value ENUM Name Description
0x0 KNOWN Known phase
0x1 UNKNOWN Unknown phase
RW 0
19 SDMOOVRCTL
Value ENUM Name Description
0x0 DIS Disable SDM output override
0x1 EN Enable SDM output override
RW 0
18:16 SDMOOVR
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0x7 ALLONES All the bits are 1
RW 0b000
15:14 RESERVED14 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00
13 PHCPT
Value ENUM Name Description
0x0 SYNC Phase capture mode is synchronous
0x1 ASYNC Phase capture mode is asyncrhonous
RW 0
12 TDCCALCORR
Value ENUM Name Description
0x0 DIS Disable TDC error correction inside DLO.
0x1 EN Enable TDC error correction inside DLO.
RW 0
11 TDCMSBCORR
Value ENUM Name Description
0x0 DIS Disable TDC error correction inside DLO.
0x1 EN Enable TDC error correction inside DLO.
RW 0
10 SDMDEM
Value ENUM Name Description
0x0 DIS Disable dynamic element matching
0x1 EN Enable dynamic element matching (recommended)
RW 0
9:8 DLYSDM
Value ENUM Name Description
0x0 CKVD16_0_PER Delay integer fine code by 0 CKVD16 clock periods
0x1 CKVD16_1_PER Delay integer fine code by 1 CKVD16 clock period
0x2 CKVD16_2_PER Delay integer fine code by 2 CKVD16 clock periods
0x3 CKVD16_3_PER Delay integer fine code by 3 CKVD16 clock periods
RW 0b00
7 RESERVED7 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0
6 DLYPHVALID
Value ENUM Name Description
0x0 CKVD16_0_PER No additional delay on variable phase capture.
0x1 CKVD16_1_PER Delays the variable phase capture and hence the phase error calculation with 1 CKVD16 clock period.
RW 0
5:4 DLYCANCRS
Value ENUM Name Description
0x0 CKVD64_0_PER Delay by 0 CKVD64 clock periods
0x1 CKVD64_1_PER Delay by 1 CKVD64 clock period
0x2 CKVD64_2_PER Delay by 2 CKVD64 clock periods
0x3 CKVD64_3_PER Delay by 3 CKVD64 clock periods
RW 0b00
3:2 DLYCANFINE
Value ENUM Name Description
0x0 CKVD16_1_PER Delay by 1 CKVD16 clock periods
0x1 CKVD16_2_PER Delay by 2 CKVD16 clock period
0x2 CKVD16_3_PER Delay by 3 CKVD16 clock periods
0x3 CKVD16_4_PER Delay by 4 CKVD16 clock periods
RW 0b00
1:0 DLYADD
Value ENUM Name Description
0x0 CKVD64_0_PER Delay by 0 CKVD64 clock periods
0x1 CKVD64_1_PER Delay by 1 CKVD64 clock period
0x2 CKVD64_2_PER Delay by 2 CKVD64 clock periods
0x3 CKVD64_3_PER Delay by 3 CKVD64 clock periods
RW 0b00

TOP:LRFDRFE32:LF1_LF0

Address Offset 0x0000 0094
Physical Address 0x4008 3494 Instance 0x4008 3494
Description Alias register for RFE_LF1_RFE_LF0
Type RW
Bits Field Name Description Type Reset
31:30 RESERVED30 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00
29:16 KP
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0x3FFF ALLONES All the bits are 1
RW 0b00 0000 0000 0000
15:13 RESERVED13 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000
12 KIPREC
Value ENUM Name Description
0x0 LOW KI encoding is <12.0u>
0x1 HIGH KI encoding is <4.08>
RW 0
11:0 KI
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFF ALLONES All the bits are 1
RW 0x000

TOP:LRFDRFE32:PHINIT_PHEDISC

Address Offset 0x0000 0098
Physical Address 0x4008 3498 Instance 0x4008 3498
Description Alias register for RFE_PHINIT_RFE_PHEDISC
Type RW
Bits Field Name Description Type Reset
31:24 RESERVED24 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00
23:16 OFF
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFF ALLONES All the bits are 1
RW 0x00
15:14 RESERVED14 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00
13:10 CNT
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xF ALLONES All the bits are 1
RW 0x0
9:0 THR
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0x3FF ALLONES All the bits are 1
RW 0b00 0000 0000

TOP:LRFDRFE32:PLLMON1_PLLMON0

Address Offset 0x0000 009C
Physical Address 0x4008 349C Instance 0x4008 349C
Description Alias register for RFE_PLLMON1_RFE_PLLMON0
Type RW
Bits Field Name Description Type Reset
31:29 RESERVED29 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000
28:24 PHELOCKCNT
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0x1F ALLONES All the bits are 1
RW 0b0 0000
23:16 PHELOCKTHR
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFF ALLONES All the bits are 1
RW 0x00
15:14 PHELOLCNT
Value ENUM Name Description
0x0 REFCLK_16_PER Threshold count is 16 REFCLK periods
0x1 REFCLK_32_PER Threshold count is 32 REFCLK periods
0x2 REFCLK_64_PER Threshold count is 64 REFCLK periods
0x3 REFCLK_128_PER Threshold count is 128 REFCLK periods
RW 0b00
13:8 PHELOLTHR
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0x3F ALLONES All the bits are 1
RW 0b00 0000
7 RESERVED7 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0
6:0 FCTHR
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0x7F ALLONES All the bits are 1
RW 0b000 0000

TOP:LRFDRFE32:MOD1_MOD0

Address Offset 0x0000 00A0
Physical Address 0x4008 34A0 Instance 0x4008 34A0
Description Alias register for RFE_MOD1_RFE_MOD0
Type RW
Bits Field Name Description Type Reset
31:28 RESERVED28 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0
27:16 FOFF
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFF ALLONES All the bits are 1
RW 0x000
15:13 RESERVED13 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000
12:11 SCHEME
Value ENUM Name Description
0x0 NC No connect Modulator output does not add to frequencey control word from PLL.
0x1 INLOOP_MOD_FREF In-loop modulation with FREF resolution MOD_RES = FREF / (DIVIDER/2) / 2^(15+CANPTHGAIN) DIV.RATIO determines DIVIDER configuration. Scheme only supports closed-loop operation.
0x2 INLOOP_MOD_FRF In-loop modulation with FRF resolution MOD_RES = FRF / 2^(21+CANPTHGAIN)
0x3 TWO_POINT_MOD_FRF 2-point modulation with FRF resolution MOD_RES = FRF / 2^(21+CANPTHGAIN) Scheme supports both open -and closed-loop operation. Scheme allows wider modulation bandwiths than INLOOP_MOD_FRF.
RW 0b00
10:8 SYMSHP
Value ENUM Name Description
0x0 SHAPEDFSK Use generic 3 symbol shaper defined by SHAPECFG* registers.
0x1 ZIGBEE Use unshaped zigbee
0x2 PCWSPSK Use piecewise linear PSK shaper defined by SHAPECFG* registers.
0x3 SHAPEDZIGBEE Use Shaped 802.15.4 modulation
0x4 CHIRP Chirp modulation
RW 0b000
7:6 CANPTHGAIN
Value ENUM Name Description
0x0 TWO_POW_M_15 POW(2,-15)
0x1 TWO_POW_M_16 POW(2,-16)
0x2 TWO_POW_M_17 POW(2,-17)
0x3 TWO_POW_M_18 POW(2,-18)
RW 0b00
5:4 SHPGAIN
Value ENUM Name Description
0x0 X1 Shape gain = 1
0x1 X2 Shape gain = 2
0x2 X4 Shape gain = 4
0x3 X8 Shape gain = 8
RW 0b00
3:2 INTPFACT
Value ENUM Name Description
0x0 ILLEGAL0 Illegal, unsupported setting
0x1 INTP_BY_16 Interpolate by 16
0x2 INTP_BY_32 Interpolate by 32
0x3 ILLEGAL1 Illegal, unsupported setting
RW 0b00
1:0 RESERVED0 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00

TOP:LRFDRFE32:DTX1_DTX0

Address Offset 0x0000 00A4
Physical Address 0x4008 34A4 Instance 0x4008 34A4
Description Alias register for RFE_DTX1_RFE_DTX0
Type RW
Bits Field Name Description Type Reset
31:24 SHP3
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFF ALLONES All the bits are 1
RW 0x00
23:16 SHP2
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFF ALLONES All the bits are 1
RW 0x00
15:8 SHP1
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFF ALLONES All the bits are 1
RW 0x00
7:0 SHP0
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFF ALLONES All the bits are 1
RW 0x00

TOP:LRFDRFE32:DTX3_DTX2

Address Offset 0x0000 00A8
Physical Address 0x4008 34A8 Instance 0x4008 34A8
Description Alias register for RFE_DTX3_RFE_DTX2
Type RW
Bits Field Name Description Type Reset
31:24 SHP7
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFF ALLONES All the bits are 1
RW 0x00
23:16 SHP6
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFF ALLONES All the bits are 1
RW 0x00
15:8 SHP5
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFF ALLONES All the bits are 1
RW 0x00
7:0 SHP4
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFF ALLONES All the bits are 1
RW 0x00

TOP:LRFDRFE32:DTX5_DTX4

Address Offset 0x0000 00AC
Physical Address 0x4008 34AC Instance 0x4008 34AC
Description Alias register for RFE_DTX5_RFE_DTX4
Type RW
Bits Field Name Description Type Reset
31:24 SHP11
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFF ALLONES All the bits are 1
RW 0x00
23:16 SHP10
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFF ALLONES All the bits are 1
RW 0x00
15:8 SHP9
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFF ALLONES All the bits are 1
RW 0x00
7:0 SHP8
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFF ALLONES All the bits are 1
RW 0x00

TOP:LRFDRFE32:DTX7_DTX6

Address Offset 0x0000 00B0
Physical Address 0x4008 34B0 Instance 0x4008 34B0
Description Alias register for RFE_DTX7_RFE_DTX6
Type RW
Bits Field Name Description Type Reset
31:24 SHP15
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFF ALLONES All the bits are 1
RW 0x00
23:16 SHP14
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFF ALLONES All the bits are 1
RW 0x00
15:8 SHP13
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFF ALLONES All the bits are 1
RW 0x00
7:0 SHP12
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFF ALLONES All the bits are 1
RW 0x00

TOP:LRFDRFE32:DTX9_DTX8

Address Offset 0x0000 00B4
Physical Address 0x4008 34B4 Instance 0x4008 34B4
Description Alias register for RFE_DTX9_RFE_DTX8
Type RW
Bits Field Name Description Type Reset
31:24 SHP19
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFF ALLONES All the bits are 1
RW 0x00
23:16 SHP18
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFF ALLONES All the bits are 1
RW 0x00
15:8 SHP17
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFF ALLONES All the bits are 1
RW 0x00
7:0 SHP16
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFF ALLONES All the bits are 1
RW 0x00

TOP:LRFDRFE32:DTX11_DTX10

Address Offset 0x0000 00B8
Physical Address 0x4008 34B8 Instance 0x4008 34B8
Description Alias register for RFE_DTX11_RFE_DTX10
Type RW
Bits Field Name Description Type Reset
31:24 SHP23
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFF ALLONES All the bits are 1
RW 0x00
23:16 SHP22
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFF ALLONES All the bits are 1
RW 0x00
15:8 SHP21
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFF ALLONES All the bits are 1
RW 0x00
7:0 SHP20
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFF ALLONES All the bits are 1
RW 0x00

TOP:LRFDRFE32:PLLM0

Address Offset 0x0000 00BC
Physical Address 0x4008 34BC Instance 0x4008 34BC
Description Alias register for RFE_PLLM0H_RFE_PLLM0L
Type RW
Bits Field Name Description Type Reset
31:2 VAL
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0x3FFF ALLONES All the bits are 1
RW 0b00 0000 0000 0000 0000 0000 0000 0000
1:0 SPARE0
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0x3 ALLONES All the bits are 1
RW 0b00

TOP:LRFDRFE32:PLLM1

Address Offset 0x0000 00C0
Physical Address 0x4008 34C0 Instance 0x4008 34C0
Description Alias register for RFE_PLLM1H_RFE_PLLM1L
Type RW
Bits Field Name Description Type Reset
31:2 VAL
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0x3FFF ALLONES All the bits are 1
RW 0b00 0000 0000 0000 0000 0000 0000 0000
1:0 SPARE0
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0x3 ALLONES All the bits are 1
RW 0b00

TOP:LRFDRFE32:CALMMID_CALMCRS

Address Offset 0x0000 00C4
Physical Address 0x4008 34C4 Instance 0x4008 34C4
Description Alias register for RFE_CALMMID_RFE_CALMCRS
Type RW
Bits Field Name Description Type Reset
31:16 CALMMID_VAL
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RW 0x0000
15:0 CALMCRS_VAL
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RW 0x0000

TOP:LRFDRFE32:REFDIV

Address Offset 0x0000 00C8
Physical Address 0x4008 34C8 Instance 0x4008 34C8
Description Alias register for RFE_REFDIV
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 LOAD
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RW 0x0000

TOP:LRFDRFE32:DLOCTL0

Address Offset 0x0000 00CC
Physical Address 0x4008 34CC Instance 0x4008 34CC
Description Alias register for RFE_DLOCTL0
Type RW
Bits Field Name Description Type Reset
31:11 RESERVED11 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000 0000 0000 0000 0000
10:8 TDCSTOP
Value ENUM Name Description
0x0 CLOSED Closed-loop operation
0x1 OPEN Open-loop operation
RW 0b000
7 DTSTXTAL
Value ENUM Name Description
0x0 ZERO Disable XTALBAW DTST interface
0x1 ONE Enable XTALBAW DTST interface
RW 0
6:4 LOOPUPD
Value ENUM Name Description
0x0 DEF Use default FREF (PLLM0)
0x1 ALT Use alternate REF (PLLM1)
RW 0b000
3 PH3
Value ENUM Name Description
0x0 HALT Halt DLO FSM after DCO frequency span measurement When DLO and RFE runs KDCO estimation, RFE must compute KDCO from the frequency span, and calculate loop filter settings to use before lock aquisition.
0x1 START Close the loop to aquire phase lock, i.e. phase 3 of calibration routine.
RW 0
2 PH2
Value ENUM Name Description
0x0 HALT Halt DLO FSM after TDC calibration measurement When DLO and RFE runs TDC calibration, RFE must use calibration measurement to calculcate CAL2.KTDCINV.
0x1 START Start KDCO estimation, i.e. phase 2 of calibration routine.
RW 0
1 LOOPMODE
Value ENUM Name Description
0x0 CLOSED Closed-loop operation
0x1 OPEN Open-loop operation
RW 0
0 RSTN
Value ENUM Name Description
0x0 RESET DLO is reset
0x1 ACTIVE DLO is not held in reset
RW 0

TOP:LRFDRFE32:DLOCTL1

Address Offset 0x0000 00D0
Physical Address 0x4008 34D0 Instance 0x4008 34D0
Description Alias register for RFE_DLOCTL1
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15 DCO
Value ENUM Name Description
0x0 DIS Disable DCO
0x1 EN Enable DCO
RW 0
14:8 RESERVED8 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000
7 FCDEM
Value ENUM Name Description
0x0 DIS Disable DEM
0x1 EN Enable DEM
RW 0
6 DTSTCKVD
Value ENUM Name Description
0x0 ZERO Disable CKVD DTST interface
0x1 ONE Enable CKVD DTST interface
RW 0
5 PHEDISC
Value ENUM Name Description
0x0 DIS Disable phase error discard function
0x1 EN Enable phase error discard function
RW 0
4 PLLMON
Value ENUM Name Description
0x0 DIS Disable and reset PLL monitor
0x1 EN Enable PLL monitor
RW 0
3 IIR
Value ENUM Name Description
0x0 DIS Disable IIR filter
0x1 EN Enable IIR filter
RW 0
2 MOD
Value ENUM Name Description
0x0 DIS Disable MODISF
0x1 EN Enable MODISF
RW 0
1 MODINIT
Value ENUM Name Description
0x0 DEACTIVATE Deactivate MODISF initialization
0x1 ACTIVATE Activate MODISF initialization
RW 0
0 MTDCRSTN
Value ENUM Name Description
0x0 RESET Reset MTDC
0x1 ACTIVE Release MTDC reset
RW 0

TOP:LRFDRFE32:DCOOVR1_DCOOVR0

Address Offset 0x0000 00D4
Physical Address 0x4008 34D4 Instance 0x4008 34D4
Description Alias register for RFE_DCOOVR1_RFE_DCOOVR0
Type RW
Bits Field Name Description Type Reset
31 RESERVED31 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0
30:24 FINECODE
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0x7F ALLONES All the bits are 1
RW 0b000 0000
23:16 SDMICODE
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFF ALLONES All the bits are 1
RW 0x00
15:14 RESERVED14 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00
13:8 MIDCODE
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0x3F ALLONES All the bits are 1
RW 0b00 0000
7:4 CRSCODE
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xF ALLONES All the bits are 1
RW 0x0
3 FINECTL
Value ENUM Name Description
0x0 DIS Disable fine code override
0x1 EN Enable fine code override
RW 0
2 SDMICTL
Value ENUM Name Description
0x0 DIS Disable SDM input code override
0x1 EN Enable SDM input code override
RW 0
1 MIDCTL
Value ENUM Name Description
0x0 DIS Disable mid code override
0x1 EN Enable mid code override
RW 0
0 CRSCTL
Value ENUM Name Description
0x0 DIS Disable coarse code override
0x1 EN Enable coarse code override
RW 0

TOP:LRFDRFE32:DLOEV_DTST

Address Offset 0x0000 00D8
Physical Address 0x4008 34D8 Instance 0x4008 34D8
Description Alias register for RFE_DLOEV_RFE_DTST
Type RW
Bits Field Name Description Type Reset
31:24 RESERVED24 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00
23 LOCK
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
22 LOL
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
21 FCABVTHR
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
20 FCBLWTHR
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
19:16 STATE
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xF ALLONES All the bits are 1
RO 0x0
15 RESERVED15 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0
14:11 SPARE11
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xF ALLONES All the bits are 1
RW 0x0
10:8 VARTGLDLY
Value ENUM Name Description
0x0 CLK_0_PER Toggle lags data by 0 CKVD16 periods.
0x1 CLK_1_PER Toggle lags data by 1 CKVD16 periods.
0x2 CLK_2_PER Toggle lags data by 2 CKVD16 periods.
0x3 CLK_3_PER Toggle lags data by 3 CKVD16 periods.
0x4 CLK_4_PER Toggle lags data by 4 CKVD16 periods.
0x5 CLK_5_PER Toggle lags data by 5 CKVD16 periods.
0x6 CLK_6_PER Toggle lags data by 6 CKVD16 periods.
0x7 CLK_7_PER Toggle lags data by 7 CKVD16 periods.
RW 0b000
7 REFTGLDLY
Value ENUM Name Description
0x0 CLK_0_PER Toggle lags data by 0 HFXT/BAW periods.
0x1 CLK_1_PER Toggle lags data by 1 HFXT/BAW periods.
RW 0
6 TRNSEQ
Value ENUM Name Description
0x0 DIS Disable trainer sequence
0x1 EN Enable trainer sequence
RW 0
5 SPARE5
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RW 0
4:0 SIG
Value ENUM Name Description
0x0 REF_NC_0 dtst_data = 0x0000
0x1 REF_FSMCAL dtst_data : [15] : '0' [14] : u_fsm/pi_pll_lock_ind [13:10] : u_fsm/po_dsts_fsm_state [9:6] : u_fsm/po_dtst_fsm_coarse [5:0] : u_fsm/po_dtst_fsm_mid
0x2 REF_FERR_MAG dtst_data = u_fsm/po_dtst_fsm_ferr_mag Format is14.2u. The signal is only updated for frequency measurements that affect the calibration result.
0x3 REF_NC_3 dtst_data = 0x0000
0x4 REF_NC_4 dtst_data = 0x0000
0x5 REF_NC_5 dtst_data = 0x0000
0x6 REF_NC_6 dtst_data = 0x0000
0x7 REF_NC_7 dtst_data = 0x0000
0x8 REF_NC_8 dtst_data = 0x0000
0x9 REF_NC_9 dtst_data = 0x0000
0xA REF_NC_10 dtst_data = 0x0000
0xB REF_NC_11 dtst_data = 0x0000
0xC REF_NC_12 dtst_data = 0x0000
0xD REF_NC_13 dtst_data = 0x0000
0xE REF_NC_14 dtst_data = 0x0000
0xF REF_NC_15 dtst_data = 0x0000
0x10 VAR_NC_0 dtst_data = 0x0000
0x11 VAR_PHERR_UPPER dtst_data = u_pll/phase_error[16:1] Format is 6.10s.
0x12 VAR_PHERR_LOWER dtst_data : [15] : u_pll/phase_error[16] [14:0] : u_pll/phase_error[14:0] Format is 5.11s. Phase error wraps if if too large.
0x13 VAR_PH_RAW dtst_data : [15] ; u_pll/pi_tdc_msb_error [14:11] : u_pll/pi_pi_cnt_lsb [10:0] : u_pll/pi_tdc_data
0x14 VAR_PH_TDCCORR dtst_data : [15] ; u_pll/pi_tdc_msb_error [14:11] : u_pll/pi_pi_cnt_lsb [10:0] : u_pll/tdc_data_corr
0x15 VAR_PH_COMP_PHERR_TDCSTOP dtst_data : [15:14] : po_tdc_stop_dly_sel [13] : u_pll/phase_error[16] [12:9]: u_pll/phase_error[11:8] [8:0] : u_pll/var_phase[14: 6] [13:9] : phase error. Format is 2.3s. [8:0] : variable phase. Format is 4.5u.
0x16 VAR_TDCSTOP_PHERR dtst_data : [15:14] : po_tdc_stop_dly_sel [13] u_pll/phase_error[16] [12:0]: u_pll/phase_error[12:0] [13:0] : phase_error. Format is 3.11s.
0x17 VAR_TDCSTOP_STATUS_TDC dtst_data : [15:14] : po_tdc_stop_dly_sel [13] : u_pll/pi_tdc_msb_error [12] : u_pll/pll_loop_update [11] : (u_pll/po_ckvd48_pllmon_lock XOR u_pll/po_ckvd48_pllmon_lol) [10:0]: u_pll/pi_tdc_data Note that [12:11] are samples from previous reference clock edge.
0x18 VAR_MPX_CAN dtst_data : [15] : u_mpx/freq_can[16] [14:0] : u_mpx/freq_can[14:0] Format is 1.15s. This field holds how much phase DTX adds to DCO per reference frequency. This is a slice of the signals that goes to u_pll which is 3.18s. Hence, wrapping can occur.
0x19 VAR_LOCK_FINECODE dtst_data : [15] : (u_pll/po_ckvd48_pllmon_lock XOR u_pll/po_ckvd48_pllmon_lol) [14:0] : u_pll/po_ckvd16_finecode_pll
0x1A VAR_LOOP_UPD_FINECODE dtst_data : [15] : (u_pll/pll_loop_update) [14:0] : u_pll/po_ckvd16_finecode_pll
0x1B VAR_NC_11 dtst_data = 0x0000
0x1C VAR_NC_12 dtst_data = 0x0000
0x1D VAR_NC_13 dtst_data = 0x0000
0x1E VAR_NC_14 dtst_data = 0x0000
0x1F VAR_NC_15 dtst_data = 0x0000
RW 0b0 0000

TOP:LRFDRFE32:FDCOSPANLSB_DTSTRD

Address Offset 0x0000 00DC
Physical Address 0x4008 34DC Instance 0x4008 34DC
Description Alias register for RFE_FDCOSPANLSB_RFE_DTSTRD
Type RO
Bits Field Name Description Type Reset
31:16 VAL
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RO 0x0000
15:0 DATA
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RO 0x0000

TOP:LRFDRFE32:TDCCAL_FDCOSPANMSB

Address Offset 0x0000 00E0
Physical Address 0x4008 34E0 Instance 0x4008 34E0
Description Alias register for RFE_TDCCAL_RFE_FDCOSPANMSB
Type RO
Bits Field Name Description Type Reset
31:16 TDCCAL_VAL
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RO 0x0000
15:3 RESERVED3 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000 0000 0000
2:0 FDCOSPANMSB_VAL
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0x7 ALLONES All the bits are 1
RO 0b000

TOP:LRFDRFE32:GPI_CALRES

Address Offset 0x0000 00E4
Physical Address 0x4008 34E4 Instance 0x4008 34E4
Description Alias register for RFE_GPI_RFE_CALRES
Type RO
Bits Field Name Description Type Reset
31:24 RESERVED24 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00
23 GPI7
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
22 GPI6
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
21 GPI5
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
20 GPI4
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
19 GPI3
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
18 GPI2
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
17 GPI1
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
16 GPI0
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
15:10 RESERVED10 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000
9:4 MIDCODE
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0x3F ALLONES All the bits are 1
RO 0b00 0000
3:0 CRSCODE
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xF ALLONES All the bits are 1
RO 0x0

TOP:LRFDRFE32:LIN2LOGOUT_MATHACCELIN

Address Offset 0x0000 00E8
Physical Address 0x4008 34E8 Instance 0x4008 34E8
Description Alias register for RFE_LIN2LOGOUT_RFE_MATHACCELIN
Type RW
Bits Field Name Description Type Reset
31:23 RESERVED23 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000 0000
22:16 LOGVAL
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0x7F ALLONES All the bits are 1
RO 0b000 0000
15:0 VAL
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RW 0x0000

TOP:LRFDRFE32:TIMCTL_DIVBY3OUT

Address Offset 0x0000 00EC
Physical Address 0x4008 34EC Instance 0x4008 34EC
Description Alias register for RFE_TIMCTL_RFE_DIVBY3OUT
Type RO
Bits Field Name Description Type Reset
31:30 RESERVED30 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00
29:24 CPTSRC
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0x3F ALLONES All the bits are 1
RW 0b00 0000
23 CPTCTL
Value ENUM Name Description
0x0 DIS Disable counter capture mode
0x1 EN Enable counter capture mode
RW 0
22:21 CNTRSRC
Value ENUM Name Description
0x0 CLK Use clock
0x1 MAGN0 Use magnitude estimator 0 data enable
0x2 MAGN1 Use magnitude estimator 1 data enable
0x3 FREF Count FREF ticks
RW 0b00
20 CNTRCLR
Value ENUM Name Description
0x0 ZERO No action
0x1 ONE Clear counter value
RW 0
19 CNTRCTL
Value ENUM Name Description
0x0 DIS Disable counter
0x1 EN Enable counter
RW 0
18:17 TIMSRC
Value ENUM Name Description
0x0 CLK Use clock
0x1 MAGN0 Use magnitude estimator 0 data enable
0x2 MAGN1 Use magnitude estimator 1 data enable
0x3 FREF Count FREF ticks
RW 0b00
16 TIMCTL
Value ENUM Name Description
0x0 DIS Disable timer and clear internal timer value
0x1 EN Enable timer
RW 0
15:4 RESERVED4 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x000
3:0 DIV3
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xF ALLONES All the bits are 1
RO 0x0

TOP:LRFDRFE32:TIMPER_TIMINC

Address Offset 0x0000 00F0
Physical Address 0x4008 34F0 Instance 0x4008 34F0
Description Alias register for RFE_TIMPER_RFE_TIMINC
Type RW
Bits Field Name Description Type Reset
31:16 TIMPER_VAL
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RW 0x0000
15:0 TIMINC_VAL
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RW 0x0000

TOP:LRFDRFE32:TIMCAPT_TIMCNT

Address Offset 0x0000 00F4
Physical Address 0x4008 34F4 Instance 0x4008 34F4
Description Alias register for RFE_TIMCAPT_RFE_TIMCNT
Type RO
Bits Field Name Description Type Reset
31:16 VALUE
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RO 0x0000
15:0 VAL
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RO 0x0000

TOP:LRFDRFE32:TRCSTAT_TRCCTRL

Address Offset 0x0000 00F8
Physical Address 0x4008 34F8 Instance 0x4008 34F8
Description Alias register for RFE_TRCSTAT_RFE_TRCCTRL
Type WO
Bits Field Name Description Type Reset
31:17 RESERVED17 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000
16 BUSY
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
15:1 RESERVED1 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000
0 SEND
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
WO 0

TOP:LRFDRFE32:TRCPAR0_TRCCMD

Address Offset 0x0000 00FC
Physical Address 0x4008 34FC Instance 0x4008 34FC
Description Alias register for RFE_TRCPAR0_RFE_TRCCMD
Type RW
Bits Field Name Description Type Reset
31:16 VAL
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RW 0x0000
15:10 RESERVED10 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000
9:8 PARCNT
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0x3 ALLONES All the bits are 1
RW 0b00
7:0 PKTHDR
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFF ALLONES All the bits are 1
RW 0x00

TOP:LRFDRFE32:GPOCTL_TRCPAR1

Address Offset 0x0000 0100
Physical Address 0x4008 3500 Instance 0x4008 3500
Description Alias register for RFE_GPOCTL_RFE_TRCPAR1
Type RW
Bits Field Name Description Type Reset
31 SEL7
Value ENUM Name Description
0x0 SW The pin is controlled by GPOCTRL.GPO7
0x1 HW The pin is controlled by its HW source
RW 0
30 SEL6
Value ENUM Name Description
0x0 SW The pin is controlled by GPOCTRL.GPO6
0x1 HW The pin is controlled by its HW source
RW 0
29 SEL5
Value ENUM Name Description
0x0 SW The pin is controlled by GPOCTRL.GPO5
0x1 HW The pin is controlled by its HW source
RW 0
28 SEL4
Value ENUM Name Description
0x0 SW The pin is controlled by GPOCTRL.GPO4
0x1 HW The pin is controlled by its HW source
RW 0
27 SEL3
Value ENUM Name Description
0x0 SW The pin is controlled by GPOCTRL.GPO3
0x1 HW The pin is controlled by its HW source
RW 0
26 SEL2
Value ENUM Name Description
0x0 SW The pin is controlled by GPOCTRL.GPO2
0x1 HW The pin is controlled by its HW source
RW 0
25 SEL1
Value ENUM Name Description
0x0 SW The pin is controlled by GPOCTRL.GPO1
0x1 HW The pin is controlled by its HW source
RW 0
24 SEL0
Value ENUM Name Description
0x0 SW The pin is controlled by GPOCTRL.GPO0
0x1 HW The pin is controlled by its HW source
RW 0
23 GPO7
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RW 0
22 GPO6
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RW 0
21 GPO5
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RW 0
20 GPO4
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RW 0
19 GPO3
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RW 0
18 GPO2
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RW 0
17 GPO1
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RW 0
16 GPO0
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RW 0
15:0 VAL
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RW 0x0000

TOP:LRFDRFE32:DIVCTL_ANAISOCTL

Address Offset 0x0000 0104
Physical Address 0x4008 3504 Instance 0x4008 3504
Description Alias register for RFE_DIVCTL_RFE_ANAISOCTL
Type RW
Bits Field Name Description Type Reset
31 DIV2PH180
Value ENUM Name Description
0x0 DIS Disable path
0x1 EN Enable path
RW 0
30 DIV2PH0
Value ENUM Name Description
0x0 DIS Disable path
0x1 EN Enable path
RW 0
29 DIV2PH270
Value ENUM Name Description
0x0 DIS Disable path
0x1 EN Enable path
RW 0
28 DIV2PH90
Value ENUM Name Description
0x0 DIS Disable path
0x1 EN Enable path
RW 0
27 SPARE11
Value ENUM Name Description
0x0 ZERO Bit is 0
0x1 ONE Bit is one
RW 0
26 S1G20DBMMUX
Value ENUM Name Description
0x0 ENABLEN Enable mux
0x1 DISABLE Disable mux
RW 0
25 ADCDIV
Value ENUM Name Description
0x0 DIS Disable divider
0x1 EN Enable divider
RW 0
24 ENSYNTH
Value ENUM Name Description
0x0 DIS Clock is disabled
0x1 EN Clock is enabled
RW 0
23 TXPH18020DBMDIV
Value ENUM Name Description
0x0 DIS Disable divider
0x1 EN Enable divider
RW 0
22 TXPH020DBMDIV
Value ENUM Name Description
0x0 DIS Disable divider
0x1 EN Enable divider
RW 0
21 TXPH180DIV
Value ENUM Name Description
0x0 DIS Disable divider
0x1 EN Enable divider
RW 0
20 TXPH0DIV
Value ENUM Name Description
0x0 DIS Disable divider
0x1 EN Enable divider
RW 0
19 RXPH90DIV
Value ENUM Name Description
0x0 DIS Disable divider
0x1 EN Enable divider
RW 0
18 RXPH0DIV
Value ENUM Name Description
0x0 DIS Disable divider
0x1 EN Enable divider
RW 0
17 Spare1
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RW 0
16 EN
Value ENUM Name Description
0x0 OFF Disable divider
0x1 ON Enable divider
RW 0
15:5 RESERVED5 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000
4 ADCDIGRSTN
Value ENUM Name Description
0x0 RESET Reset
0x1 ACTIVE Don't reset
RW 0
3 IFADC2SVTISO
Value ENUM Name Description
0x0 CONNECT Don't isolate
0x1 ISOLATE Isolate
RW 1
2 DIV2IFADCISO
Value ENUM Name Description
0x0 CONNECT Don't isolate
0x1 ISOLATE Isolate
RW 1
1 MTDC2SVTISO
Value ENUM Name Description
0x0 CONNECT Don't isolate
0x1 ISOLATE Isolate
RW 1
0 DIV2MTDCISO
Value ENUM Name Description
0x0 CONNECT Don't isolate
0x1 ISOLATE Isolate
RW 1

TOP:LRFDRFE32:MAGNACC0_RXCTRL

Address Offset 0x0000 0108
Physical Address 0x4008 3508 Instance 0x4008 3508
Description Alias register for RFE_MAGNACC0_RFE_RXCTRL
Type RW
Bits Field Name Description Type Reset
31:16 VAL
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RO 0x0000
15:13 RESERVED13 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000
12 SPARE
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RW 0
11:9 ATTN
Value ENUM Name Description
0x0 NOATT No attenuation
0x1 _3DB 3dB attenuation
0x2 _6DB 6dB attenuation
0x3 _9DB 9dB attenuation
0x4 _12DB 12dB attenuation
0x5 _15DB 15dB attenuation
0x6 _18DB 18dB attenuation
0x7 _21DB 21dB attenuation
RW 0b000
8:4 IFAMPGC
Value ENUM Name Description
0x0 MIN15DB Set gain to MAX - 15 dB
0x1 MIN12DB Set gain to MAX - 12 dB
0x3 MIN9DB Set gain to MAX - 9 dB
0x7 MIN6DB Set gain to MAX - 6 dB
0xF MIN3DB Set gain to MAX - 3 dB
0x1F MAX Set IFAMP gain to MAX
RW 0b0 0000
3:0 LNAGAIN
Value ENUM Name Description
0x0 MIN12DB Set gain to MAX - 12 dB
0x1 MIN9DB Set gain to MAX - 9 dB
0x3 MIN6DB Set gain to MAX - 6 dB
0x7 MIN3DB Set gain to MAX - 3 dB
0xF MAX Set gain to MAX
RW 0x0

TOP:LRFDRFE32:RSSI_MAGNACC1

Address Offset 0x0000 010C
Physical Address 0x4008 350C Instance 0x4008 350C
Description Alias register for RFE_RSSI_RFE_MAGNACC1
Type RO
Bits Field Name Description Type Reset
31:24 RESERVED24 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00
23:16 RSSI_VAL
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFF ALLONES All the bits are 1
RW 0x00
15:0 MAGNACC1_VAL
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RO 0x0000

TOP:LRFDRFE32:RFGAIN_RSSIMAX

Address Offset 0x0000 0110
Physical Address 0x4008 3510 Instance 0x4008 3510
Description Alias register for RFE_RFGAIN_RFE_RSSIMAX
Type RW
Bits Field Name Description Type Reset
31:24 RESERVED24 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00
23:16 DBGAIN
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFF ALLONES All the bits are 1
RW 0x00
15:8 RESERVED8 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00
7:0 VAL
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFF ALLONES All the bits are 1
RW 0x00

TOP:LRFDRFE32:DIVSTA_IFADCSTAT

Address Offset 0x0000 0114
Physical Address 0x4008 3514 Instance 0x4008 3514
Description Alias register for RFE_DIVSTA_RFE_IFADCSTAT
Type RO
Bits Field Name Description Type Reset
31:17 RESERVED17 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000
16 STAT
Value ENUM Name Description
0x0 IDLE Serial divider is idle
0x1 BUSY Serial divider is busy and result is not available yet
RO 0
15:8 RESERVED8 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00
7 RESERVED7
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
6:2 QUANTCALVAL
Value ENUM Name Description
0x0 COMP0 Q Comparator
0x1 COMP1 I comparator
RO 0b0 0000
1 QUANTCALDONE
Value ENUM Name Description
0x0 NOT_READY Calibration is not finished
0x1 READY Calibration is complete
RO 0
0 RESERVED0
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0

TOP:LRFDRFE32:DIVIDEND

Address Offset 0x0000 0118
Physical Address 0x4008 3518 Instance 0x4008 3518
Description Alias register for RFE_DIVIDENDH_RFE_DIVIDENDL
Type WO
Bits Field Name Description Type Reset
31:0 VAL
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
WO 0x0000 0000

TOP:LRFDRFE32:DIVISOR

Address Offset 0x0000 011C
Physical Address 0x4008 351C Instance 0x4008 351C
Description Alias register for RFE_DIVISORH_RFE_DIVISORL
Type RW
Bits Field Name Description Type Reset
31:0 VAL
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RW 0x0000 0000

TOP:LRFDRFE32:QUOTIENT

Address Offset 0x0000 0120
Physical Address 0x4008 3520 Instance 0x4008 3520
Description Alias register for RFE_QUOTIENTH_RFE_QUOTIENTL
Type RO
Bits Field Name Description Type Reset
31:0 VAL
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RO 0x0000 0000

TOP:LRFDRFE32:PRODUCT

Address Offset 0x0000 0124
Physical Address 0x4008 3524 Instance 0x4008 3524
Description Alias register for RFE_PRODUCTH_RFE_PRODUCTL
Type RO
Bits Field Name Description Type Reset
31:0 VAL
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RO 0x0000 0000

TOP:LRFDRFE32:MULTSTA

Address Offset 0x0000 0128
Physical Address 0x4008 3528 Instance 0x4008 3528
Description Alias register for RFE_MULTSTA
Type RO
Bits Field Name Description Type Reset
31:1 RESERVED1 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000 0000 0000 0000
0 STAT
Value ENUM Name Description
0x0 IDLE Multiplier is idle
0x1 BUSY Multiplier is busy, result is not ready yet
RO 0

TOP:LRFDRFE32:MULTCFG

Address Offset 0x0000 012C
Physical Address 0x4008 352C Instance 0x4008 352C
Description Alias register for RFE_MULTCFG
Type RW
Bits Field Name Description Type Reset
31:1 RESERVED1 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000 0000 0000 0000
0 MODE
Value ENUM Name Description
0x0 UNSIGNED Multiplier assumes inputs are unsigned numbers
0x1 SIGNED Multiplier assumes inputs are signed numbers
RW 0


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