VIMS

Instance: VIMS
Component: VIMS
Base address: 0x40024000


Versatile Instruction Memory System
Controls memory access to the Flash and encapsulates the following instruction memories:
- Boot ROM
- Caches

TOP:VIMS Register Summary

Register Name

Type

Register Width (Bits)

Register Reset

Address Offset

Physical Address

DESC

RO

32

0xD140 0010

0x0000 0000

0x4002 4000

DESCEX

RO

32

0x11FF 801F

0x0000 0004

0x4002 4004

FLWS1T

RW

32

0x0000 000F

0x0000 0008

0x4002 4008

FLWS2T

RW

32

0x0000 000F

0x0000 000C

0x4002 400C

PTRMC0

RW

32

0x131A 0000

0x0000 0018

0x4002 4018

B0TRMC1

RW

32

0x0000 0000

0x0000 001C

0x4002 401C

B0TRMC0

RW

32

0x0000 0000

0x0000 0020

0x4002 4020

B1TRMC1

RW

32

0x0000 0000

0x0000 0024

0x4002 4024

B1TRMC0

RW

32

0x0000 0000

0x0000 0028

0x4002 4028

FLBLCK

RW

32

0x0000 0000

0x0000 0100

0x4002 4100

CFG

RW

32

0x0000 0309

0x0000 03FC

0x4002 43FC

RDPRMN

RW

32

0x0000 000F

0x0000 0400

0x4002 4400

RDPRNMN

RW

32

0x0000 00BF

0x0000 0404

0x4002 4404

RDPRTRM

RW

32

0x0000 00BF

0x0000 0408

0x4002 4408

RDPREGR

RW

32

0x0000 0001

0x0000 040C

0x4002 440C

WEPRA

RW

32

0xFFFF FFFF

0x0000 0410

0x4002 4410

WEPRB0

RW

32

0xFFFF FFFF

0x0000 0414

0x4002 4414

WEPRB1

RW

32

0xFFFF FFFF

0x0000 0418

0x4002 4418

WEPRAUX

RW

32

0x0000 001F

0x0000 041C

0x4002 441C

FLBSTA

RO

32

0x0000 0000

0x0000 0420

0x4002 4420

CCHCTL

RW

32

0x0000 0091

0x0000 0424

0x4002 4424

CCHSTA

RO

32

0x0000 0003

0x0000 0428

0x4002 4428

CNTHIT

RO

32

0x0000 0000

0x0000 0430

0x4002 4430

CNTMISS

RO

32

0x0000 0000

0x0000 0434

0x4002 4434

CTL

RW

32

0x0000 0000

0x0000 04FC

0x4002 44FC

DTB

RW

32

0x0000 0000

0x0000 0800

0x4002 4800

TOP:VIMS Register Descriptions

TOP:VIMS:DESC

Address Offset 0x0000 0000
Physical Address 0x4002 4000 Instance 0x4002 4000
Description
Description Register. This register provides IP module ID, revision information, instance index and standard MMR registers offset.
Type RO
Bits Field Name Description Type Reset
31:16 MODID Module identification contains a unique peripheral identification number. RO 0xD140
15:12 STDIPOFF Standard IP MMR block offset. Standard IP MMRs are the set of from aggregated IRQ registers till DTB.
0: Standard IP MMRs do not exist
0x1-0xF: Standard IP MMRs begin at offset of (64*STDIPOFF from the base IP address)		 RO 0x0
11:8 INSTIDX IP Instance ID number. If multiple instances of IP exist in the device, this field can identify the instance number (0-15). RO 0x0
7:4 MAJREV Major revision of IP RO 0x1
3:0 MINREV Minor revision of IP RO 0x0

TOP:VIMS:DESCEX

Address Offset 0x0000 0004
Physical Address 0x4002 4004 Instance 0x4002 4004
Description
Extended Description Register.This register describes the configuration of VIMS.
Type RO
Bits Field Name Description Type Reset
31:29 RESERVED29 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000
28:27 NBANK Number of Flash banks RO 0b10
26:15 FLSZ FLASH size in Kilo Bytes. The total FLASH size is (FLSZ + 1) KB RO 0x3FF
14:0 ROMSZ ROM size in Kilo Bytes. The total ROM size is (ROMSZ + 1) KB RO 0b000 0000 0001 1111

TOP:VIMS:FLWS1T

Address Offset 0x0000 0008
Physical Address 0x4002 4008 Instance 0x4002 4008
Description
Flash Wait State 1T. This register is used to specify the number of waitstates necessary for accessing the flash in 1T mode.
Type RW
Bits Field Name Description Type Reset
31:4 RESERVED4 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x000 0000
3:0 VAL Flash read wait states for 1T accesses
Value ENUM Name Description
0x0 WS0 Wait state value 0
0x1 WS1 Wait state value 1
0x2 WS2 Wait state value 2
0x3 WS3 Wait state value 3
0x4 WS4 Wait state value 4
0x5 WS5 Wait state value 5
0x6 WS6 Wait state value 6
0x7 WS7 Wait state value 7
0x8 WS8 Wait state value 8
0x9 WS9 Wait state value 9
0xA WS10 Wait state value 10
0xB WS11 Wait state value 11
0xC WS12 Wait state value 12
0xD WS13 Wait state value 13
0xE WS14 Wait state value 14
0xF WS15 Wait state value 15
RW 0xF

TOP:VIMS:FLWS2T

Address Offset 0x0000 000C
Physical Address 0x4002 400C Instance 0x4002 400C
Description
Flash Wait State 1T. This register is used to specify the number of waitstates necessary for accessing the flash in 2T mode. This register is writable only when CFG.LOCK is 1
Type RW
Bits Field Name Description Type Reset
31:4 RESERVED4 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x000 0000
3:0 VAL Flash read wait states for 2T accesses
Value ENUM Name Description
0x0 WS0 Wait state value 0
0x1 WS1 Wait state value 1
0x2 WS2 Wait state value 2
0x3 WS3 Wait state value 3
0x4 WS4 Wait state value 4
0x5 WS5 Wait state value 5
0x6 WS6 Wait state value 6
0x7 WS7 Wait state value 7
0x8 WS8 Wait state value 8
0x9 WS9 Wait state value 9
0xA WS10 Wait state value 10
0xB WS11 Wait state value 11
0xC WS12 Wait state value 12
0xD WS13 Wait state value 13
0xE WS14 Wait state value 14
0xF WS15 Wait state value 15
RW 0xF

TOP:VIMS:PTRMC0

Address Offset 0x0000 0018
Physical Address 0x4002 4018 Instance 0x4002 4018
Description
FLASH Pump trim Bank 0. This register stores various PUMP trims. This register is writable only when CFG.LOCK is 1
Type RW
Bits Field Name Description Type Reset
31:0 VAL Flash charge pump trim value. RW 0x131A 0000

TOP:VIMS:B0TRMC1

Address Offset 0x0000 001C
Physical Address 0x4002 401C Instance 0x4002 401C
Description
FLASH Bank 0 Trim [59:32]. This register stores various bank trims. This register is writable only when CFG.LOCK is 1
Type RW
Bits Field Name Description Type Reset
31:28 RESERVED28 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0
27:0 VAL Flash bank trim value. RW 0x000 0000

TOP:VIMS:B0TRMC0

Address Offset 0x0000 0020
Physical Address 0x4002 4020 Instance 0x4002 4020
Description
FLASH Bank 0 Trim [31:0]. This register stores various bank trims. This register is writable only when CFG.LOCK is 1
Type RW
Bits Field Name Description Type Reset
31:0 VAL Flash bank trim value. RW 0x0000 0000

TOP:VIMS:B1TRMC1

Address Offset 0x0000 0024
Physical Address 0x4002 4024 Instance 0x4002 4024
Description
FLASH Bank 1 Trim [59:32]. This register stores various bank trims. This register is writable only when CFG.LOCK is 1
Type RW
Bits Field Name Description Type Reset
31:28 RESERVED28 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0
27:0 VAL Flash bank trim value. RW 0x000 0000

TOP:VIMS:B1TRMC0

Address Offset 0x0000 0028
Physical Address 0x4002 4028 Instance 0x4002 4028
Description
FLASH Bank 1 Trim [31:0]. This register stores various bank trims. This register is writable only when CFG.LOCK is 1
Type RW
Bits Field Name Description Type Reset
31:0 VAL Flash bank trim value. RW 0x0000 0000

TOP:VIMS:FLBLCK

Address Offset 0x0000 0100
Physical Address 0x4002 4100 Instance 0x4002 4100
Description
Flash Block. This register is used to block user read, write and erase operation to flash. This register is sticky 1 and writable only when CFG.LOCK is 1
Type RW
Bits Field Name Description Type Reset
31:1 RESERVED1 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000 0000 0000 0000
0 ACCESS Flash Access
Value ENUM Name Description
0x0 ALLOW Allow
0x1 BLOCK Block
RW 0

TOP:VIMS:CFG

Address Offset 0x0000 03FC
Physical Address 0x4002 43FC Instance 0x4002 43FC
Description
Configuration Register. This register is used for VIMS configuration. This register is writable only when CFG.LOCK is 1
Type RW
Bits Field Name Description Type Reset
31:11 RESERVED11 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000 0000 0000 0000 0000
10:8 HSMSZ HSM Size. Number of 32KB blocks allocated to HSM
Value ENUM Name Description
0x0 SIZE_0 No space allocated to HSM
0x1 SIZE_32 32KB
0x2 SIZE_64 64KB
0x3 SIZE_96 96KB
0x4 SIZE_128 128KB
0x5 SIZE_160 160KB
0x6 SIZE_192 192KB
0x7 SIZE_224 224KB
RW 0b011
7:5 RESERVED5 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000
4 SPLMODE Split Mode. The logical address space is split into two equal regions
Value ENUM Name Description
0x0 DIS Disable
0x1 EN Enable
RW 0
3 RDPRROM ROM Read Protection Disable
Value ENUM Name Description
0x0 EN Enable
0x1 DIS Disable
RW 1
2 ATTEST This bit is used to enable flash test mode.
Value ENUM Name Description
0x0 DIS Disable
0x1 EN Enable
RW 0
1 TRMVLID TRIM Valid. This bit indicates if flash charge pump and bank trim values are valid. RW 0
0 LOCK Lock. Lock VIMS configuration. This bit is sticky '0' and when 0 write protects following registers
FLWS1T
FLWS2T
PTRMC0
B0TRMC1
B0TRMC0
B1TRMC1
B1TRMC0
FLBLCK
CFG
Value ENUM Name Description
0x0 EN Configuration registers are locked for writing
0x1 DIS Configuration registers are open for writing
RW 1

TOP:VIMS:RDPRMN

Address Offset 0x0000 0400
Physical Address 0x4002 4400 Instance 0x4002 4400
Description
Read Protect Main. First 16KB of flash main region can be protected with granularity of 2KB. This register is sticky 0
Type RW
Bits Field Name Description Type Reset
31:4 RESERVED4 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x000 0000
3:0 VAL Protection configuration value.
Undefined values will read protect whole protectable region
Value ENUM Name Description
0x7 PROT_16KB Protect First 16KB
0x8 PROT_14KB Protect First 14KB
0x9 PROT_12KB Protect First 12KB
0xA PROT_10KB Protect First 10KB
0xB PROT_8KB Protect First 8KB
0xC PROT_6KB Protect First 6KB
0xD PROT_4KB Protect First 4KB
0xE PROT_2KB Protect First 2KB
0xF PROT_0KB Protection is Disabled
RW 0xF

TOP:VIMS:RDPRNMN

Address Offset 0x0000 0404
Physical Address 0x4002 4404 Instance 0x4002 4404
Description
Read Protect Non-Main regions.
Type RW
Bits Field Name Description Type Reset
31:8 RESERVED8 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00 0000
7 VLOG VLOG read protection configuration. This field is sticky 0 RW 1
6 RESERVED6 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0
5:0 CCFG CCFG read protection configuration. Last 512 bytes of CCFG can be protected with granularity of 16Bytes. This field is sticky 0 RW 0b11 1111

TOP:VIMS:RDPRTRM

Address Offset 0x0000 0408
Physical Address 0x4002 4408 Instance 0x4002 4408
Description
Read Protect Trim
Type RW
Bits Field Name Description Type Reset
31:8 RESERVED8 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00 0000
7 SCFG SCFG read protection configuration. This field is sticky 0 RW 1
6 RESERVED6 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0
5:0 FCFG FCFG read protection configuration. Last 512 bytes of CCFG can be protected with granularity of 16Bytes. This register is sticky 0 RW 0b11 1111

TOP:VIMS:RDPREGR

Address Offset 0x0000 040C
Physical Address 0x4002 440C Instance 0x4002 440C
Description
Read Protect ENGR. This register is sticky 0
Type RW
Bits Field Name Description Type Reset
31:1 RESERVED1 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000 0000 0000 0000
0 ENGR ENGR read protection configuration. RW 1

TOP:VIMS:WEPRA

Address Offset 0x0000 0410
Physical Address 0x4002 4410 Instance 0x4002 4410
Description
Write Erase Protect Main A. This register allows the first 32 sectors of the logical bank 0 main region to be protected from program or erase, with 1 bit protecting each sector (sector 0 to sector 31). This register is sticky 0
Type RW
Bits Field Name Description Type Reset
31:0 VAL Flash write/erase protection configuration value. RW 0xFFFF FFFF

TOP:VIMS:WEPRB0

Address Offset 0x0000 0414
Physical Address 0x4002 4414 Instance 0x4002 4414
Description
Write Erase Protect Main Bank 0. This register allows physical bank 0 main region sectors to be protected from program and erase. Each bit corresponds to a group of 8 sectors. First 4-bit are reserved if physical Bank 0 is logical bank 0 i.e. CTL.SWAP = 0. This register is sticky 0
Type RW
Bits Field Name Description Type Reset
31:0 VAL Flash write/erase protection configuration value. RW 0xFFFF FFFF

TOP:VIMS:WEPRB1

Address Offset 0x0000 0418
Physical Address 0x4002 4418 Instance 0x4002 4418
Description
Write Erase Protect Main Bank 1. This register allows physical bank 1 main region sectors to be protected from program and erase. Each bit corresponds to a group of 8 sectors. First 4-bit are reserved if physical Bank 1 is logical bank 0 i.e. CTL.SWAP = 1. This register is sticky 0
Type RW
Bits Field Name Description Type Reset
31:0 VAL Flash write/erase protection configuration value. RW 0xFFFF FFFF

TOP:VIMS:WEPRAUX

Address Offset 0x0000 041C
Physical Address 0x4002 441C Instance 0x4002 441C
Description
Write Erase Protect Auxillary. Flash Write/Erase protection for Non-Main, TRIM and ENGR Regions. This register is sticky 0
Type RW
Bits Field Name Description Type Reset
31:5 RESERVED5 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000 0000 0000
4 VLOG Write/Erase Protection for VLOG RW 1
3 SCFG Write/Erase Protection for SCFG RW 1
2 ENGR Write/Erase Protection for ENGR RW 1
1 FCFG Write/Erase Protection for FCFG RW 1
0 CCFG Write/Erase Protection for CCFG RW 1

TOP:VIMS:FLBSTA

Address Offset 0x0000 0420
Physical Address 0x4002 4420 Instance 0x4002 4420
Description
Flash Status. This register is used to indicate status of flash.
Type RO
Bits Field Name Description Type Reset
31:6 RESERVED6 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000 0000 0000 0000 0000
5 B1BSY Bank 1 Busy. This bit indicates if flash Bank 1 is busy.
Value ENUM Name Description
0x0 IDLE Idle
0x1 BUSY Busy
RO 0
4 B0BSY Bank 0 Busy. This bit indicates if flash Bank 0 is busy.
Value ENUM Name Description
0x0 IDLE Idle
0x1 BUSY Busy
RO 0
3 PARERR Parity Error. This bit indicates parity error on write/erase & read protection MMRs. This bit is sticky when set to 1 by hardware.
Value ENUM Name Description
0x0 NOERR No Error
0x1 ERR Error
RO 0
2 BUSY This bit indicates if flash is busy.
Value ENUM Name Description
0x0 IDLE Idle
0x1 BUSY Busy
RO 0
1 FL2TRDY Flash 2T Ready. This bit indicates if flash is ready in 2T mode.
Value ENUM Name Description
0x0 NOTREADY Not Ready
0x1 READY Ready
RO 0
0 FL1TRDY Flash 1T Ready. This bit indicates if flash is ready in 1T mode.
Value ENUM Name Description
0x0 NOTREADY Not Ready
0x1 READY Ready
RO 0

TOP:VIMS:CCHCTL

Address Offset 0x0000 0424
Physical Address 0x4002 4424 Instance 0x4002 4424
Description
Cache Control Register. This register is used for cache control on code bus Interface. This register can only be written when CCHSTA.BUSY is 0
Type RW
Bits Field Name Description Type Reset
31:17 RESERVED17 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000
16 HCHFLUSH Cache Flush for HSM Cache. This bit is used to flush the cache on HSM bus Interface. This bit is self clearing
Value ENUM Name Description
0x1 TRIG Trigger Flush
WO 0
15:9 RESERVED9 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000
8 CNTCLR Cache Hit/Miss Count Clear. Writing 0 to this bit has no affect
Value ENUM Name Description
0x1 CLR Clear Hit/Miss Counter
WO 0
7 CNTEN Cache Hit/Miss Count Enable.
Value ENUM Name Description
0x0 DIS Disable
0x1 EN Enable
RW 1
6 RPOLICY Replacement policy for Cache.
Value ENUM Name Description
0x0 RND Random Replacement Policy
0x1 SEQ Sequencial Replacement Policy
RW 0
5 LINFLUSH Line Buffer Flush. This bit is used to flush the Line buffer on system bus Interface. This bit is self clearing. Writing 0 to this bit has no affect
Value ENUM Name Description
0x1 TRIG Trigger Flush
WO 0
4 LINEN Line Buffer Enable. This bit is used to enable the Line buffer on system bus Interface. Disabling the Line buffer will flush it
Value ENUM Name Description
0x0 DIS Disable
0x1 EN Enable
RW 1
3 CCHFLUSH Cache Flush. This bit is used to flush the cache on code bus Interface. This bit is self clearing. Writing 0 to this bit has no affect
Value ENUM Name Description
0x1 TRIG Trigger Flush
WO 0
2:1 RESERVED1 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00
0 CCHEN Cache Enable. This bit is used to enable the cache. Disabling the cache will flush it
Value ENUM Name Description
0x0 DIS Disable
0x1 EN Enable
RW 1

TOP:VIMS:CCHSTA

Address Offset 0x0000 0428
Physical Address 0x4002 4428 Instance 0x4002 4428
Description
Cache Status. This register gives cache status
Type RO
Bits Field Name Description Type Reset
31:2 RESERVED2 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000 0000 0000 0000 0000 0000
1 BUSY Busy. This bit indicate Cache is changing state RO 1
0 EN Enabled. This bit indicate whether cache is enabled or disabled RO 1

TOP:VIMS:CNTHIT

Address Offset 0x0000 0430
Physical Address 0x4002 4430 Instance 0x4002 4430
Description
Cache Hit Counter
Type RO
Bits Field Name Description Type Reset
31:0 VAL Hit Counter Value. This counter is cleared by writing CCHCTL.CNTCLR RO 0x0000 0000

TOP:VIMS:CNTMISS

Address Offset 0x0000 0434
Physical Address 0x4002 4434 Instance 0x4002 4434
Description
Cache Miss Counter
Type RO
Bits Field Name Description Type Reset
31:0 VAL Miss Counter Value. This counter is cleared by writing CCHCTL.CNTCLR RO 0x0000 0000

TOP:VIMS:CTL

Address Offset 0x0000 04FC
Physical Address 0x4002 44FC Instance 0x4002 44FC
Description
Control Register.
Type RW
Bits Field Name Description Type Reset
31 SWAPLOCK Swap Lock. If set, CTL.SWAP bit is blocked for writing. This bit is sticky 1
Value ENUM Name Description
0x0 UNLOCK Unlocked
0x1 LOCK Locked
RW 0
30:1 RESERVED1 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000 0000 0000 0000 0000 0000
0 SWAP Swaps the logical to physical bank mapping. This bit has no effect if CTL.SPLMODE is 0 and is writable ony when CTL.SWAPLOCK is 0
Value ENUM Name Description
0x0 NOSWAP Bank is not swapped
0x1 SWAPED Bank is swapped
RW 0

TOP:VIMS:DTB

Address Offset 0x0000 0800
Physical Address 0x4002 4800 Instance 0x4002 4800
Description
Digital test bus control register. This register can be used to bring out IP internal signals to the pads for observation. 16 signals can be observed per select value.
Type RW
Bits Field Name Description Type Reset
31:4 RESERVED4 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x000 0000
3:0 SEL Digital test bus selection mux control.
Non-zero select values output a 16 bit selected group of signals per value.
Value ENUM Name Description
0x0 DIS DTB output from peripheral is 0x0
RW 0x0


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