TCM

Instance: TCM
Component: TCM
Base address: 0x40007000


IO Controller

TOP:TCM Register Summary

Register Name

Type

Register Width (Bits)

Register Reset

Address Offset

Physical Address

DESC

RO

32

0x6F44 0010

0x0000 0000

0x4000 7000

DESCEX

RO

32

0x0000 0029

0x0000 0004

0x4000 7004

REGWEN

RW

32

0x2000 0000

0x0000 0008

0x4000 7008

WMCFG

RW

32

0xE03F F01F

0x0000 000C

0x4000 700C

GSKEN0

RW

32

0xE000 03FF

0x0000 0010

0x4000 7010

GSKEN1

RW

32

0x6001 FFFF

0x0000 0014

0x4000 7014

TOP:TCM Register Descriptions

TOP:TCM:DESC

Address Offset 0x0000 0000
Physical Address 0x4000 7000 Instance 0x4000 7000
Description This register identifies the peripheral and its exact version.
This register is strictly read-only. Any write to this register will trigger chip reset.
Type RO
Bits Field Name Description Type Reset
31:16 MODID Module identification contains a unique peripheral identification number.
Value ENUM Name Description
0x0 MINIMUM Smallest value
0xFFFF MAXIMUM Highest possible value
RW 0x6F44
15:12 STDIPOFF Standard IP registers offset. Value 0 indicates Standard IP registers are not present. Any other value between 1 to 15 indicates standard IP registers start from address offset 64 * STDIPOFF from base address.
Value ENUM Name Description
0x0 MINIMUM Smallest value
0xF MAXIMUM Highest possible value
RW 0x0
11:8 INSTIDX Instance Index within the device. This will be a parameter to the RTL for modules that can have multiple instances.
Value ENUM Name Description
0x0 MINIMUM Smallest value
0xF MAXIMUM Highest possible value
RW 0x0
7:4 MAJREV Major rev of the IP
Value ENUM Name Description
0x0 MINIMUM Smallest value
0xF MAXIMUM Highest possible value
RW 0x1
3:0 MINREV Minor rev of the IP
Value ENUM Name Description
0x0 MINIMUM Smallest value
0xF MAXIMUM Highest possible value
RW 0x0

TOP:TCM:DESCEX

Address Offset 0x0000 0004
Physical Address 0x4000 7004 Instance 0x4000 7004
Description This register identifies the peripheral and its exact version.
This register is strictly read-only. Any write to this register will trigger chip reset.
Type RO
Bits Field Name Description Type Reset
31:9 RESERVED9 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000 0000
8:0 GSKCNT Number of gaskets
Value ENUM Name Description
0x1 MINIMUM Smallest value
0x200 MAXIMUM Highest possible value
RW 0b0 0010 1001

TOP:TCM:REGWEN

Address Offset 0x0000 0008
Physical Address 0x4000 7008 Instance 0x4000 7008
Description This register blocks writes to all the MMR of TCM once set. This register is protected by odd parity bit. It is sticky 1.
Type RW
Bits Field Name Description Type Reset
31:30 RESERVED30 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00
29 PAR Parity bit
Value ENUM Name Description
0x0 SET Set
0x1 RESET Reset
RW 1
28:1 RESERVED1 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x000 0000
0 WEN Write enable
Value ENUM Name Description
0x0 ENABLE Smallest value
0x1 DISABLE Highest possible value
RW 0

TOP:TCM:WMCFG

Address Offset 0x0000 000C
Physical Address 0x4000 700C Instance 0x4000 700C
Description This register is used to configure SRAM and VIMS watermark. This register is protected by odd parity bits.
Type RW
Bits Field Name Description Type Reset
31:29 PAR Parity bits. Bit 28 stores the odd parity for bits 0 to 7. Bit 29 stores the odd parity of bits 8 to 15. Bit 30 stores the odd parity of bits 23 to 16.
Value ENUM Name Description
0x0 VAL0 Value 0
0x1 VAL1 Value 1
0x2 VAL2 Value 2
0x3 VAL3 Value 3
0x4 VAL4 Value 4
0x5 VAL5 Value 5
0x6 VAL6 Value 6
0x7 VAL7 Value 7
RW 0b111
28:23 RESERVED23 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000
22:12 SRAMWM SRAM Watermark
Value ENUM Name Description
0x0 MINIMUM Smallest value
0x1FF MAXIMUM Highest possible value
RW 0b011 1111 1111
11:5 RESERVED5 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000
4:0 VIMSWM VIMS Watermark
Value ENUM Name Description
0x0 MINIMUM Smallest value
0x1FF MAXIMUM Highest possible value
RW 0b1 1111

TOP:TCM:GSKEN0

Address Offset 0x0000 0010
Physical Address 0x4000 7010 Instance 0x4000 7010
Description This register is used to store gasket configuration. This register is protected by odd parity bits.
Type RW
Bits Field Name Description Type Reset
31:29 PAR Parity bits. Bit 29 stores the odd parity for bits 0 to 7. Bit 30 stores the odd parity of bits 8 to 15. Bit 31 stores the odd parity of bits 23 to 16.
Value ENUM Name Description
0x0 VAL0 Value 0
0x1 VAL1 Value 1
0x2 VAL2 Value 2
0x3 VAL3 Value 3
0x4 VAL4 Value 4
0x5 VAL5 Value 5
0x6 VAL6 Value 6
0x7 VAL7 Value 7
RW 0b111
28:10 RESERVED10 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000
9:0 EN Gasket enable. The gasket bit to IP mapping is given as follows :-
[0] = DMA initiator AHB gasket enable
[1] = I2S initiator AHB gasket enable
[2] = HSM initiator AHB gasket enable
[3] = Radio target AHB gasket enable
[4] = AES target AHB gasket enable
[5] = I2S target AHB gasket enable
[6] = PDM target AHB gasket enable
[7] = AFA target AHB gasket enable
[8] = DMA target AHB gasket enable
[9] = CANFD target AHB gasket enable
[10] = VCE target AHB gasket enable
[11] = VCERAM target AHB gasket enable
[12] = GPIO target APB gasket enable
[13] = SYSTIMER target APB gasket enable
[14] = UART0 target APB gasket enable
[15] = UART1 target APB gasket enable
[16] = SPI0 target APB gasket enable
[17] = SPI1 target APB gasket enable
[18] = I2C0 target APB gasket enable
[19] = EVTSVT target APB gasket enable
[20] = ADC target APB gasket enable
[21] = MICADC target APB gasket enable
[22] = MICPGA target APB gasket enable
[23] = CLKCTRL target APB gasket enable
Value ENUM Name Description
0x0 MINIMUM Smallest value
0xFFFFFF MAXIMUM Highest possible value
RW 0b11 1111 1111

TOP:TCM:GSKEN1

Address Offset 0x0000 0014
Physical Address 0x4000 7014 Instance 0x4000 7014
Description This register is used to store gasket configuration. This register is protected by odd parity bits.
Type RW
Bits Field Name Description Type Reset
31:29 PAR Parity bits. Bit 29 stores the odd parity for bits 0 to 7. Bit 30 stores the odd parity of bits 8 to 15. Bit 31 stores the odd parity of bits 23 to 16.
Value ENUM Name Description
0x0 VAL0 Value 0
0x1 VAL1 Value 1
0x2 VAL2 Value 2
0x3 VAL3 Value 3
0x4 VAL4 Value 4
0x5 VAL5 Value 5
0x6 VAL6 Value 6
0x7 VAL7 Value 7
RW 0b011
28:24 RESERVED24 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000
23:0 EN Gasket enable. The gasket bit to IP mapping is given as follows :-
[0] = LGPT target APB gasket enable
[1] = NOWRAPPER target APB gasket enable
[2] = VIMS target APB gasket enable
[3] = HSM target APB gasket enable
[4] = PMC target APB gasket enable
[5] = CKMDIG target APB gasket enable
[6] = RTC target APB gasket enable
[7] = IOC target APB gasket enable
[8] = SYS0 target APB gasket enable
[9] = EVTULL target APB gasket enable
[10] = PMUDIG target APB gasket enable
[11] = DEBUGSS target APB gasket enable
[12] = HSM mailbox target APB gasket enable
[13] = HSM mailbox target APB gasket enable
[14] = HSM mailbox target APB gasket enable
[15] = HSM mailbox target APB gasket enable
[16] = HSM config target APB gasket enable
Value ENUM Name Description
0x0 MINIMUM Smallest value
0xFFFFFF MAXIMUM Highest possible value
RW 0x01 FFFF


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