Instance: SCB
Component: SCB
Base address: 0xE000ECFC
|
Register Name |
Type |
Register Width (Bits) |
Register Reset |
Address Offset |
Physical Address |
|
RO |
32 |
0x411F D210 |
0x0000 0000 |
0xE000 ECFC |
|
|
32 |
0x411F D210 |
0x0000 0004 |
0xE000 ED00 |
||
|
32 |
0x0000 0000 |
0x0000 0008 |
0xE000 ED04 |
||
|
32 |
0x411F D210 |
0x0000 000C |
0xE000 ED08 |
||
|
32 |
0xFA05 0000 |
0x0000 0010 |
0xE000 ED0C |
||
|
32 |
0x0000 0000 |
0x0000 0014 |
0xE000 ED10 |
||
|
32 |
0x0000 0201 |
0x0000 0018 |
0xE000 ED14 |
||
|
32 |
0x0000 0000 |
0x0000 001C |
0xE000 ED18 |
||
|
32 |
0x0000 0000 |
0x0000 0020 |
0xE000 ED1C |
||
|
32 |
0x0000 0000 |
0x0000 0024 |
0xE000 ED20 |
||
|
32 |
0x0000 0000 |
0x0000 0028 |
0xE000 ED24 |
||
|
32 |
0x0000 0000 |
0x0000 002C |
0xE000 ED28 |
||
|
32 |
0x0000 0000 |
0x0000 0030 |
0xE000 ED2C |
||
|
32 |
0x0000 0000 |
0x0000 0034 |
0xE000 ED30 |
||
|
32 |
0x0000 0000 |
0x0000 0038 |
0xE000 ED34 |
||
|
32 |
0x0000 0000 |
0x0000 003C |
0xE000 ED38 |
||
|
32 |
0x0000 0000 |
0x0000 0040 |
0xE000 ED3C |
||
|
32 |
0x0000 0030 |
0x0000 0044 |
0xE000 ED40 |
||
|
32 |
0x0000 0210 |
0x0000 0048 |
0xE000 ED44 |
||
|
32 |
0x0020 0000 |
0x0000 004C |
0xE000 ED48 |
||
|
32 |
0x0000 0000 |
0x0000 0050 |
0xE000 ED4C |
||
|
32 |
0x0010 1F40 |
0x0000 0054 |
0xE000 ED50 |
||
|
32 |
0x0000 0000 |
0x0000 0058 |
0xE000 ED54 |
||
|
32 |
0x0100 0000 |
0x0000 005C |
0xE000 ED58 |
||
|
32 |
0x0000 0000 |
0x0000 0060 |
0xE000 ED5C |
||
|
32 |
0x0114 1110 |
0x0000 0064 |
0xE000 ED60 |
||
|
32 |
0x0221 2000 |
0x0000 0068 |
0xE000 ED64 |
||
|
32 |
0x2023 2232 |
0x0000 006C |
0xE000 ED68 |
||
|
32 |
0x0111 1131 |
0x0000 0070 |
0xE000 ED6C |
||
|
32 |
0x0131 0132 |
0x0000 0074 |
0xE000 ED70 |
||
|
32 |
0x0000 0000 |
0x0000 0078 |
0xE000 ED74 |
||
|
32 |
0x0000 0000 |
0x0000 007C |
0xE000 ED78 |
||
|
32 |
0x8000 C000 |
0x0000 0080 |
0xE000 ED7C |
||
|
32 |
0x8000 C000 |
0x0000 0084 |
0xE000 ED80 |
||
|
32 |
0x8000 C000 |
0x0000 0088 |
0xE000 ED84 |
||
|
32 |
0x0000 0000 |
0x0000 008C |
0xE000 ED88 |
||
|
32 |
0x0000 0000 |
0x0000 0090 |
0xE000 ED8C |
| Address Offset | 0x0000 0000 | ||
| Physical Address | 0xE000 ECFC | Instance | 0xE000 ECFC |
| Description | Provides implementation-specific minor revision information | ||
| Type | RO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | IMPLEMENTAION_DEFINED | The contents of this field are IMPLEMENTATION DEFINED | RO | 0x411F D210 | ||
| Address Offset | 0x0000 0004 | ||
| Physical Address | 0xE000 ED00 | Instance | 0xE000 ED00 |
| Description | Provides identification information for the PE, including an implementer code for the device and a device ID number | ||
| Type | |||
| Bits | Field Name | Description | Type | Reset | ||
| 31:24 | Implementer | This field must hold an implementer code that has been assigned by ARM | RO | 0x41 | ||
| 23:20 | Variant | IMPLEMENTATION DEFINED variant number. Typically, this field is used to distinguish between different product variants, or major revisions of a product | RO | 0x1 | ||
| 19:16 | Architecture | Defines the Architecture implemented by the PE | RO | 0xF | ||
| 15:4 | PartNo | IMPLEMENTATION DEFINED primary part number for the device | RO | 0xD21 | ||
| 3:0 | Revision | IMPLEMENTATION DEFINED revision number for the device | RO | 0x0 | ||
| Address Offset | 0x0000 0008 | ||
| Physical Address | 0xE000 ED04 | Instance | 0xE000 ED04 |
| Description | Controls and provides status information for NMI, PendSV, SysTick and interrupts | ||
| Type | |||
| Bits | Field Name | Description | Type | Reset | ||
| 31 | PENDNMISET | Indicates whether the NMI exception is pending | RO | 0 | ||
| 30 | PENDNMICLR | Allows the NMI exception pend state to be cleared | WO | 0 | ||
| 29 | RES0 | Reserved, RES0 | RO | 0 | ||
| 28 | PENDSVSET | Indicates whether the PendSV `FTSSS exception is pending | RO | 0 | ||
| 27 | PENDSVCLR | Allows the PendSV exception pend state to be cleared `FTSSS | WO | 0 | ||
| 26 | PENDSTSET | Indicates whether the SysTick `FTSSS exception is pending | RO | 0 | ||
| 25 | PENDSTCLR | Allows the SysTick exception pend state to be cleared `FTSSS | WO | 0 | ||
| 24 | STTNS | Controls whether in a single SysTick implementation, the SysTick is Secure or Non-secure | RW | 0 | ||
| 23 | ISRPREEMPT | Indicates whether a pending exception will be serviced on exit from debug halt state | RO | 0 | ||
| 22 | ISRPENDING | Indicates whether an external interrupt, generated by the NVIC, is pending | RO | 0 | ||
| 21 | RES0_1 | Reserved, RES0 | RO | 0 | ||
| 20:12 | VECTPENDING | The exception number of the highest priority pending and enabled interrupt | RO | 0b0 0000 0000 | ||
| 11 | RETTOBASE | In Handler mode, indicates whether there is more than one active exception | RO | 0 | ||
| 10:9 | RES0_2 | Reserved, RES0 | RO | 0b00 | ||
| 8:0 | VECTACTIVE | The exception number of the current executing exception | RO | 0b0 0000 0000 | ||
| Address Offset | 0x0000 000C | ||
| Physical Address | 0xE000 ED08 | Instance | 0xE000 ED08 |
| Description | Indicates the offset of the vector table base address from memory address 0x00000000 | ||
| Type | |||
| Bits | Field Name | Description | Type | Reset | ||
| 31:7 | TBLOFF | Bits 31 down to 7 of the vector table base offset. | RO | 0b0 1000 0010 0011 1111 1010 0100 | ||
| 6:0 | RES0 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b001 0000 | ||
| Address Offset | 0x0000 0010 | ||
| Physical Address | 0xE000 ED0C | Instance | 0xE000 ED0C |
| Description | This register is used to determine data endianness, clear all active state information for debug or to recover from a hard failure, execute a system reset, alter the priority grouping position (binary point). | ||
| Type | |||
| Bits | Field Name | Description | Type | Reset | ||
| 31:16 | VECTKEY | Register key. Writing to this register (AIRCR) requires 0x05FA in VECTKEY. Otherwise the write value is ignored. Read always returns 0xFA05. | RW | 0xFA05 | ||
| 15 | ENDIANESS | Data endianness bit 0 Little-endian. 1 Big-endian. |
RO | 0 | ||
| 14 | PRIS | Prioritize Secure exceptions. The value of this bit defines whether Secure exception priority boosting is enabled. |
RO | 0 | ||
| 13 | BFHFNMINS | BusFault, HardFault, and NMI Non-secure enable. The value of this bit defines whether BusFault and NMI exceptions are Non-secure, and whether exceptions target the Non-secure HardFault exception 0x0 BusFault, HardFault, and NMI are Secure. 0x1 BusFault and NMI are Non-secure and exceptions can target Non-secure HardFault. |
RW | 0 | ||
| 12:11 | RESERVED11 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 | ||
| 10:8 | PRIGROUP | Interrupt priority grouping field. This field determines the split of group priority from subpriority |
RW | 0b000 | ||
| 7:4 | RES4 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0 | ||
| 3 | SYSRESETREQS | System reset request Secure only. The value of this bit defines whether the SYSRESETREQ bit is functional for Non-secure use |
RW | 0 | ||
| 2 | SYSRESETREQ | System reset request. This bit allows software or a debugger to request a system reset: 0 Do not request a system reset. 1 Request a system reset. This bit is not banked between Security states. |
WO | 0 | ||
| 1 | VECTCLRACTIVE | Reserved for Debug use. This bit reads as 0. When writing to the register you must write 0 to this bit, otherwise behavior is UNPREDICTABLE. |
WO | 0 | ||
| 1 | RESERVED1 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0 | ||
| 0 | RES0 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0 | ||
| Address Offset | 0x0000 0014 | ||
| Physical Address | 0xE000 ED10 | Instance | 0xE000 ED10 |
| Description | This register is used for power-management functions, i.e., signaling to the system when the processor can enter a low power state, controlling how the processor enters and exits low power states. | ||
| Type | |||
| Bits | Field Name | Description | Type | Reset | ||
| 31:5 | RESERVED5 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 0000 | ||
| 4 | SEVONPEND | Send Event on Pending bit: 0 Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded. 1 Enabled events and all interrupts, including disabled interrupts, can wakeup the processor. When an event or interrupt enters pending state, the event signal wakes up the processor from WFE. If the processor is not waiting for an event, the event is registered and affects the next WFE. The processor also wakes up on execution of an SEV instruction or an external event. This bit is banked between Security states. |
RW | 0 | ||
| 3 | SLEEPDEEPS | Controls whether the SLEEPDEEP bit is only accessible from the Secure state: 0 The SLEEPDEEP bit accessible from both Security states. 1 The SLEEPDEEP bit behaves as RAZ/WI when accessed from the Non-secure state. This bit in only accessible from the Secure state, and behaves as RAZ/WI when accessed from the Nonsecure state. This bit is not banked between Security states. |
RW | 0 | ||
| 2 | SLEEPDEEP | Controls whether the processor uses sleep or deep sleep as its low power mode. 0 Sleep. 1 Deep sleep. This bit is not banked between Security states. |
RW | 0 | ||
| 1 | SLEEPONEXIT | Indicates sleep-on-exit when returning from Handler mode to Thread mode: 0 Do not sleep when returning to Thread mode. 1 Enter sleep, or deep sleep, on return from an ISR. Setting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application. This bit is banked between Security states. |
RW | 0 | ||
| 0 | RESERVED0 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0 | ||
| Address Offset | 0x0000 0018 | ||
| Physical Address | 0xE000 ED14 | Instance | 0xE000 ED14 |
| Description | Sets or returns configuration and control data | ||
| Type | |||
| Bits | Field Name | Description | Type | Reset | ||
| 31:19 | RES0 | Reserved, RES0 | RO | 0b0 0000 0000 0000 | ||
| 18 | BP | Enables program flow prediction `FTSSS | RO | 0 | ||
| 17 | IC | This is a global enable bit for instruction caches in the selected Security state | RO | 0 | ||
| 16 | DC | Enables data caching of all data accesses to Normal memory `FTSSS | RO | 0 | ||
| 15:11 | RES0_1 | Reserved, RES0 | RO | 0b0 0000 | ||
| 10 | STKOFHFNMIGN | Controls the effect of a stack limit violation while executing at a requested priority less than 0 | RW | 0 | ||
| 9 | RES1 | Reserved, RES1 | RO | 1 | ||
| 8 | BFHFNMIGN | Determines the effect of precise BusFaults on handlers running at a requested priority less than 0 | RW | 0 | ||
| 7:5 | RES0_2 | Reserved, RES0 | RO | 0b000 | ||
| 4 | DIV_0_TRP | Controls the generation of a DIVBYZERO UsageFault when attempting to perform integer division by zero | RW | 0 | ||
| 3 | UNALIGN_TRP | Controls the trapping of unaligned word or halfword accesses | RW | 0 | ||
| 2 | RES0_3 | Reserved, RES0 | RO | 0 | ||
| 1 | USERSETMPEND | Determines whether unprivileged accesses are permitted to pend interrupts via the STIR | RW | 0 | ||
| 0 | RES1_1 | Reserved, RES1 | RO | 1 | ||
| Address Offset | 0x0000 001C | ||
| Physical Address | 0xE000 ED18 | Instance | 0xE000 ED18 |
| Description | Sets or returns priority for system handlers 4 - 7 | ||
| Type | |||
| Bits | Field Name | Description | Type | Reset | ||
| 31:24 | PRI_7 | Priority of system handler 7, SecureFault | RW | 0x00 | ||
| 23:16 | PRI_6 | Priority of system handler 6, UsageFault | RW | 0x00 | ||
| 15:8 | PRI_5 | Priority of system handler 5, BusFault | RW | 0x00 | ||
| 7:0 | PRI_4 | Priority of system handler 4, MemManage | RW | 0x00 | ||
| Address Offset | 0x0000 0020 | ||
| Physical Address | 0xE000 ED1C | Instance | 0xE000 ED1C |
| Description | Sets or returns priority for system handlers 8 - 11 | ||
| Type | |||
| Bits | Field Name | Description | Type | Reset | ||
| 31:24 | PRI_11 | Priority of system handler 11, SVCall | RW | 0x00 | ||
| 23:0 | RES0 | Reserved, RES0 | RO | 0x00 0000 | ||
| Address Offset | 0x0000 0024 | ||
| Physical Address | 0xE000 ED20 | Instance | 0xE000 ED20 |
| Description | Sets or returns priority for system handlers 12 - 15 | ||
| Type | |||
| Bits | Field Name | Description | Type | Reset | ||
| 31:24 | PRI_15 | Priority of system handler 15, SysTick | RW | 0x00 | ||
| 23:16 | PRI_14 | Priority of system handler 14, PendSV | RW | 0x00 | ||
| 15:0 | RES0_0 | Reserved, RES0 | RO | 0x0000 | ||
| Address Offset | 0x0000 0028 | ||
| Physical Address | 0xE000 ED24 | Instance | 0xE000 ED24 |
| Description | Provides access to the active and pending status of system exceptions | ||
| Type | |||
| Bits | Field Name | Description | Type | Reset | ||
| 31:22 | RES0 | Reserved, RES0 | RO | 0b00 0000 0000 | ||
| 21 | HARDFAULTPENDED | `IAAMO the pending state of the HardFault exception `CTTSSS | RW | 0 | ||
| 20 | SECUREFAULTPENDED | `IAAMO the pending state of the SecureFault exception | RW | 0 | ||
| 19 | SECUREFAULTENA | `DW the SecureFault exception is enabled | RW | 0 | ||
| 18 | USGFAULTENA | `DW the UsageFault exception is enabled `FTSSS | RW | 0 | ||
| 17 | BUSFAULTENA | `DW the BusFault exception is enabled | RW | 0 | ||
| 16 | MEMFAULTENA | `DW the MemManage exception is enabled `FTSSS | RW | 0 | ||
| 15 | SVCALLPENDED | `IAAMO the pending state of the SVCall exception `FTSSS | RW | 0 | ||
| 14 | BUSFAULTPENDED | `IAAMO the pending state of the BusFault exception | RW | 0 | ||
| 13 | MEMFAULTPENDED | `IAAMO the pending state of the MemManage exception `FTSSS | RW | 0 | ||
| 12 | USGFAULTPENDED | The UsageFault exception is banked between Security states, `IAAMO the pending state of the UsageFault exception `FTSSS | RW | 0 | ||
| 11 | SYSTICKACT | `IAAMO the active state of the SysTick exception `FTSSS | RW | 0 | ||
| 10 | PENDSVACT | `IAAMO the active state of the PendSV exception `FTSSS | RW | 0 | ||
| 9 | RES0_1 | Reserved, RES0 | RO | 0 | ||
| 8 | MONITORACT | `IAAMO the active state of the DebugMonitor exception | RW | 0 | ||
| 7 | SVCALLACT | `IAAMO the active state of the SVCall exception `FTSSS | RW | 0 | ||
| 6 | RES0_2 | Reserved, RES0 | RO | 0 | ||
| 5 | NMIACT | `IAAMO the active state of the NMI exception | RW | 0 | ||
| 4 | SECUREFAULTACT | `IAAMO the active state of the SecureFault exception | RW | 0 | ||
| 3 | USGFAULTACT | `IAAMO the active state of the UsageFault exception `FTSSS | RW | 0 | ||
| 2 | HARDFAULTACT | Indicates and allows limited modification of the active state of the HardFault exception `FTSSS | RW | 0 | ||
| 1 | BUSFAULTACT | `IAAMO the active state of the BusFault exception | RW | 0 | ||
| 0 | MEMFAULTACT | `IAAMO the active state of the MemManage exception `FTSSS | RW | 0 | ||
| Address Offset | 0x0000 002C | ||
| Physical Address | 0xE000 ED28 | Instance | 0xE000 ED28 |
| Description | Contains the three Configurable Fault Status Registers | ||
| Type | |||
| Bits | Field Name | Description | Type | Reset | ||
| 31:26 | RES0_3 | Reserved, RES0 | RO | 0b00 0000 | ||
| 25 | DIVBYZERO | Sticky flag indicating whether an integer division by zero error has occurred | RW | 0 | ||
| 24 | UNALIGNED | Sticky flag indicating whether an unaligned access error has occurred | RW | 0 | ||
| 23:21 | RES0_1_2 | Reserved, RES0 | RO | 0b000 | ||
| 20 | STKOF | Sticky flag indicating whether a stack overflow error has occurred | RW | 0 | ||
| 19 | NOCP | Sticky flag indicating whether a coprocessor disabled or not present error has occurred | RW | 0 | ||
| 18 | INVPC | Sticky flag indicating whether an integrity check error has occurred | RW | 0 | ||
| 17 | INVSTATE | Sticky flag indicating whether an EPSR.T or EPSR.IT validity error has occurred | RW | 0 | ||
| 16 | UNDEFINSTR | Sticky flag indicating whether an undefined instruction error has occurred | RW | 0 | ||
| 15 | BFARVALID | Indicates validity of the contents of the BFAR register | RW | 0 | ||
| 14 | RES0_2 | Reserved, RES0 | RO | 0 | ||
| 13 | LSPERR | Records whether a BusFault occurred during FP lazy state preservation | RW | 0 | ||
| 12 | STKERR | Records whether a derived BusFault occurred during exception entry stacking | RW | 0 | ||
| 11 | UNSTKERR | Records whether a derived BusFault occurred during exception return unstacking | RW | 0 | ||
| 10 | IMPRECISERR | Records whether an imprecise data access error has occurred | RW | 0 | ||
| 9 | PRECISERR | Records whether a precise data access error has occurred | RW | 0 | ||
| 8 | IBUSERR | Records whether a BusFault on an instruction prefetch has occurred | RW | 0 | ||
| 7 | MMARVALID | Indicates validity of the MMFAR register | RW | 0 | ||
| 6 | RES0 | Reserved, RES0 | RO | 0 | ||
| 5 | MLSPERR | Records whether a MemManage fault occurred during FP lazy state preservation | RW | 0 | ||
| 4 | MSTKERR | Records whether a derived MemManage fault occurred during exception entry stacking | RW | 0 | ||
| 3 | MUNSTKERR | Records whether a derived MemManage fault occurred during exception return unstacking | RW | 0 | ||
| 2 | RES0_1 | Reserved, RES0 | RO | 0 | ||
| 1 | DACCVIOL | Records whether a data access violation has occurred | RW | 0 | ||
| 0 | IACCVIOL | Records whether an instruction related memory access violation has occurred | RW | 0 | ||
| Address Offset | 0x0000 0030 | ||
| Physical Address | 0xE000 ED2C | Instance | 0xE000 ED2C |
| Description | Shows the cause of any HardFaults | ||
| Type | |||
| Bits | Field Name | Description | Type | Reset | ||
| 31 | DEBUGEVT | Indicates when a Debug event has occurred | RW | 0 | ||
| 30 | FORCED | Indicates that a fault with configurable priority has been escalated to a HardFault exception, because it could not be made active, because of priority, or because it was disabled | RW | 0 | ||
| 29:2 | RES0 | Reserved, RES0 | RO | 0x000 0000 | ||
| 1 | VECTTBL | Indicates when a fault has occurred because of a vector table read error on exception processing | RW | 0 | ||
| 0 | RES0_1 | Reserved, RES0 | RO | 0 | ||
| Address Offset | 0x0000 0034 | ||
| Physical Address | 0xE000 ED30 | Instance | 0xE000 ED30 |
| Description | Shows which debug event occurred | ||
| Type | |||
| Bits | Field Name | Description | Type | Reset | ||
| 31:5 | RES0 | Reserved, RES0 | RO | 0b000 0000 0000 0000 0000 0000 0000 | ||
| 4 | EXTERNAL | Sticky flag indicating whether an External debug request debug event has occurred | RW | 0 | ||
| 3 | VCATCH | Sticky flag indicating whether a Vector catch debug event has occurred | RW | 0 | ||
| 2 | DWTTRAP | Sticky flag indicating whether a Watchpoint debug event has occurred | RW | 0 | ||
| 1 | BKPT | Sticky flag indicating whether a Breakpoint debug event has occurred | RW | 0 | ||
| 0 | HALTED | Sticky flag indicating that a Halt request debug event or Step debug event has occurred | RW | 0 | ||
| Address Offset | 0x0000 0038 | ||
| Physical Address | 0xE000 ED34 | Instance | 0xE000 ED34 |
| Description | Shows the address of the memory location that caused an MPU fault | ||
| Type | |||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | ADDRESS | This register is updated with the address of a location that produced a MemManage fault. The MMFSR shows the cause of the fault, and whether this field is valid. This field is valid only when MMFSR.MMARVALID is set, otherwise it is UNKNOWN | RW | 0x0000 0000 | ||
| Address Offset | 0x0000 003C | ||
| Physical Address | 0xE000 ED38 | Instance | 0xE000 ED38 |
| Description | Shows the address associated with a precise data access BusFault | ||
| Type | |||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | ADDRESS | This register is updated with the address of a location that produced a BusFault. The BFSR shows the reason for the fault. This field is valid only when BFSR.BFARVALID is set, otherwise it is UNKNOWN | RW | 0x0000 0000 | ||
| Address Offset | 0x0000 0040 | ||
| Physical Address | 0xE000 ED3C | Instance | 0xE000 ED3C |
| Description | This register is used to determine additional system fault information to software. Single-cycle high level on an auxiliary faults is latched as one. The bit can only be cleared by writing a one to the corresponding bit. Auxiliary fault inputs to the CPU are tied to 0. | ||
| Type | |||
| Bits | Field Name | Description | Type | Reset | ||
| 31:1 | RESERVED1 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 0000 0000 | ||
| 0 | IMPDEF | Implementation defined. The bits map directly onto the signal assignment to the auxiliary fault inputs. Tied to 0 | RW | 0 | ||
| Address Offset | 0x0000 0044 | ||
| Physical Address | 0xE000 ED40 | Instance | 0xE000 ED40 |
| Description | Gives top-level information about the instruction set supported by the PE | ||
| Type | |||
| Bits | Field Name | Description | Type | Reset | ||
| 31:8 | RES0 | Reserved, RES0 | RO | 0x00 0000 | ||
| 7:4 | State1 | T32 instruction set support | RO | 0x3 | ||
| 3:0 | State0 | A32 instruction set support | RO | 0x0 | ||
| Address Offset | 0x0000 0048 | ||
| Physical Address | 0xE000 ED44 | Instance | 0xE000 ED44 |
| Description | Gives information about the programmers' model and Extensions support | ||
| Type | |||
| Bits | Field Name | Description | Type | Reset | ||
| 31:12 | RES0 | Reserved, RES0 | RO | 0x0 0000 | ||
| 11:8 | MProgMod | Identifies support for the M-Profile programmers' model support | RO | 0x2 | ||
| 7:4 | Security | Identifies whether the Security Extension is implemented | RO | 0x1 | ||
| 3:0 | RES0_1 | Reserved, RES0 | RO | 0x0 | ||
| Address Offset | 0x0000 004C | ||
| Physical Address | 0xE000 ED48 | Instance | 0xE000 ED48 |
| Description | Provides top level information about the debug system | ||
| Type | |||
| Bits | Field Name | Description | Type | Reset | ||
| 31:24 | RES0 | Reserved, RES0 | RO | 0x00 | ||
| 23:20 | MProfDbg | Indicates the supported M-profile debug architecture | RO | 0x2 | ||
| 19:0 | RES0_1 | Reserved, RES0 | RO | 0x0 0000 | ||
| Address Offset | 0x0000 0050 | ||
| Physical Address | 0xE000 ED4C | Instance | 0xE000 ED4C |
| Description | Provides information about the IMPLEMENTATION DEFINED features of the PE | ||
| Type | |||
| Bits | Field Name | Description | Type | Reset | ||
| 31:16 | RES0 | Reserved, RES0 | RO | 0x0000 | ||
| 15:12 | IMPDEF3 | IMPLEMENTATION DEFINED meaning | RO | 0x0 | ||
| 11:8 | IMPDEF2 | IMPLEMENTATION DEFINED meaning | RO | 0x0 | ||
| 7:4 | IMPDEF1 | IMPLEMENTATION DEFINED meaning | RO | 0x0 | ||
| 3:0 | IMPDEF0 | IMPLEMENTATION DEFINED meaning | RO | 0x0 | ||
| Address Offset | 0x0000 0054 | ||
| Physical Address | 0xE000 ED50 | Instance | 0xE000 ED50 |
| Description | Provides information about the implemented memory model and memory management support | ||
| Type | |||
| Bits | Field Name | Description | Type | Reset | ||
| 31:24 | RES0 | Reserved, RES0 | RO | 0x00 | ||
| 23:20 | AuxReg | Indicates support for Auxiliary Control Registers | RO | 0x1 | ||
| 19:16 | TCM | Indicates support for tightly coupled memories (TCMs) | RO | 0x0 | ||
| 15:12 | ShareLvl | Indicates the number of shareability levels implemented | RO | 0x1 | ||
| 11:8 | OuterShr | Indicates the outermost shareability domain implemented | RO | 0xF | ||
| 7:4 | PMSA | Indicates support for the protected memory system architecture (PMSA) | RO | 0x4 | ||
| 3:0 | RES0_1 | Reserved, RES0 | RO | 0x0 | ||
| Address Offset | 0x0000 0058 | ||
| Physical Address | 0xE000 ED54 | Instance | 0xE000 ED54 |
| Description | Provides information about the implemented memory model and memory management support | ||
| Type | |||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | RES0 | Reserved, RES0 | RO | 0x0000 0000 | ||
| Address Offset | 0x0000 005C | ||
| Physical Address | 0xE000 ED58 | Instance | 0xE000 ED58 |
| Description | Provides information about the implemented memory model and memory management support | ||
| Type | |||
| Bits | Field Name | Description | Type | Reset | ||
| 31:28 | RES0 | Reserved, RES0 | RO | 0x0 | ||
| 27:24 | WFIStall | Indicates the support for Wait For Interrupt (WFI) stalling | RO | 0x1 | ||
| 23:0 | RES0_1 | Reserved, RES0 | RO | 0x00 0000 | ||
| Address Offset | 0x0000 0060 | ||
| Physical Address | 0xE000 ED5C | Instance | 0xE000 ED5C |
| Description | Provides information about the implemented memory model and memory management support | ||
| Type | |||
| Bits | Field Name | Description | Type | Reset | ||
| 31:12 | RES0 | Reserved, RES0 | RO | 0x0 0000 | ||
| 11:8 | BPMaint | Indicates the supported branch predictor maintenance | RO | 0x0 | ||
| 7:4 | CMaintSW | Indicates the supported cache maintenance operations by set/way | RO | 0x0 | ||
| 3:0 | CMaintVA | Indicates the supported cache maintenance operations by address | RO | 0x0 | ||
| Address Offset | 0x0000 0064 | ||
| Physical Address | 0xE000 ED60 | Instance | 0xE000 ED60 |
| Description | Provides information about the instruction set implemented by the PE | ||
| Type | |||
| Bits | Field Name | Description | Type | Reset | ||
| 31:28 | RES0 | Reserved, RES0 | RO | 0x0 | ||
| 27:24 | Divide | Indicates the supported Divide instructions | RO | 0x1 | ||
| 23:20 | Debug | Indicates the implemented Debug instructions | RO | 0x1 | ||
| 19:16 | Coproc | Indicates the supported Coprocessor instructions | RO | 0x4 | ||
| 15:12 | CmpBranch | Indicates the supported combined Compare and Branch instructions | RO | 0x1 | ||
| 11:8 | BitField | Indicates the supported bit field instructions | RO | 0x1 | ||
| 7:4 | BitCount | Indicates the supported bit count instructions | RO | 0x1 | ||
| 3:0 | RES0_1 | Reserved, RES0 | RO | 0x0 | ||
| Address Offset | 0x0000 0068 | ||
| Physical Address | 0xE000 ED64 | Instance | 0xE000 ED64 |
| Description | Provides information about the instruction set implemented by the PE | ||
| Type | |||
| Bits | Field Name | Description | Type | Reset | ||
| 31:28 | RES0 | Reserved, RES0 | RO | 0x0 | ||
| 27:24 | Interwork | Indicates the implemented Interworking instructions | RO | 0x2 | ||
| 23:20 | Immediate | Indicates the implemented for data-processing instructions with long immediates | RO | 0x2 | ||
| 19:16 | IfThen | Indicates the implemented If-Then instructions | RO | 0x1 | ||
| 15:12 | Extend | Indicates the implemented Extend instructions | RO | 0x2 | ||
| 11:0 | RES0_1 | Reserved, RES0 | RO | 0x000 | ||
| Address Offset | 0x0000 006C | ||
| Physical Address | 0xE000 ED68 | Instance | 0xE000 ED68 |
| Description | Provides information about the instruction set implemented by the PE | ||
| Type | |||
| Bits | Field Name | Description | Type | Reset | ||
| 31:28 | Reversal | Indicates the implemented Reversal instructions | RO | 0x2 | ||
| 27:24 | RES0 | Reserved, RES0 | RO | 0x0 | ||
| 23:20 | MultU | Indicates the implemented advanced unsigned Multiply instructions | RO | 0x2 | ||
| 19:16 | MultS | Indicates the implemented advanced signed Multiply instructions | RO | 0x3 | ||
| 15:12 | Mult | Indicates the implemented additional Multiply instructions | RO | 0x2 | ||
| 11:8 | MultiAccessInt | Indicates the support for interruptible multi-access instructions | RO | 0x2 | ||
| 7:4 | MemHint | Indicates the implemented Memory Hint instructions | RO | 0x3 | ||
| 3:0 | LoadStore | Indicates the implemented additional load/store instructions | RO | 0x2 | ||
| Address Offset | 0x0000 0070 | ||
| Physical Address | 0xE000 ED6C | Instance | 0xE000 ED6C |
| Description | Provides information about the instruction set implemented by the PE | ||
| Type | |||
| Bits | Field Name | Description | Type | Reset | ||
| 31:28 | RES0 | Reserved, RES0 | RO | 0x0 | ||
| 27:24 | TrueNOP | Indicates the implemented true NOP instructions | RO | 0x1 | ||
| 23:20 | T32Copy | Indicates the support for T32 non flag-setting MOV instructions | RO | 0x1 | ||
| 19:16 | TabBranch | Indicates the implemented Table Branch instructions | RO | 0x1 | ||
| 15:12 | SynchPrim | Used in conjunction with ID_ISAR4.SynchPrim_frac to indicate the implemented Synchronization Primitive instructions | RO | 0x1 | ||
| 11:8 | SVC | Indicates the implemented SVC instructions | RO | 0x1 | ||
| 7:4 | SIMD | Indicates the implemented SIMD instructions | RO | 0x3 | ||
| 3:0 | Saturate | Indicates the implemented saturating instructions | RO | 0x1 | ||
| Address Offset | 0x0000 0074 | ||
| Physical Address | 0xE000 ED70 | Instance | 0xE000 ED70 |
| Description | Provides information about the instruction set implemented by the PE | ||
| Type | |||
| Bits | Field Name | Description | Type | Reset | ||
| 31:28 | RES0 | Reserved, RES0 | RO | 0x0 | ||
| 27:24 | PSR_M | Indicates the implemented M profile instructions to modify the PSRs | RO | 0x1 | ||
| 23:20 | SyncPrim_frac | Used in conjunction with ID_ISAR3.SynchPrim to indicate the implemented Synchronization Primitive instructions | RO | 0x3 | ||
| 19:16 | Barrier | Indicates the implemented Barrier instructions | RO | 0x1 | ||
| 15:12 | RES0_1 | Reserved, RES0 | RO | 0x0 | ||
| 11:8 | Writeback | Indicates the support for writeback addressing modes | RO | 0x1 | ||
| 7:4 | WithShifts | Indicates the support for writeback addressing modes | RO | 0x3 | ||
| 3:0 | Unpriv | Indicates the implemented unprivileged instructions | RO | 0x2 | ||
| Address Offset | 0x0000 0078 | ||
| Physical Address | 0xE000 ED74 | Instance | 0xE000 ED74 |
| Description | Provides information about the instruction set implemented by the PE | ||
| Type | |||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | RES0 | Reserved, RES0 | RO | 0x0000 0000 | ||
| Address Offset | 0x0000 007C | ||
| Physical Address | 0xE000 ED78 | Instance | 0xE000 ED78 |
| Description | Identifies the type of caches implemented and the level of coherency and unification | ||
| Type | |||
| Bits | Field Name | Description | Type | Reset | ||||||||||||||||||||
| 31:30 | ICB | This field indicates the boundary between inner and outer domain
|
RO | 0b00 | ||||||||||||||||||||
| 29:27 | LoUU | This field indicates the Level of Unification Uniprocessor for the cache hierarchy |
RO | 0b000 | ||||||||||||||||||||
| 26:24 | LoC | This field indicates the Level of Coherence for the cache hierarchy | RO | 0b000 | ||||||||||||||||||||
| 23:21 | LoUIS | Enables Non-secure access to coprocessor CP0 | RO | 0b000 | ||||||||||||||||||||
| 20:18 | Ctype7 | Cache type field 7. Indicates the type of cache implemented at level 7.
|
RO | 0b000 | ||||||||||||||||||||
| 17:15 | Ctype6 | Cache type field 6. Indicates the type of cache implemented at level 6.
|
RO | 0b000 | ||||||||||||||||||||
| 14:12 | Ctype5 | Cache type field 5. Indicates the type of cache implemented at level 5.
|
RO | 0b000 | ||||||||||||||||||||
| 11:9 | Ctype4 | Cache type field 4. Indicates the type of cache implemented at level 4.
|
RO | 0b000 | ||||||||||||||||||||
| 8:6 | Ctype3 | Cache type field 3. Indicates the type of cache implemented at level 3.
|
RO | 0b000 | ||||||||||||||||||||
| 5:3 | Ctype2 | Cache type field 2. Indicates the type of cache implemented at level 2.
|
RO | 0b000 | ||||||||||||||||||||
| 2:0 | Ctype1 | Cache type field 1. Indicates the type of cache implemented at level 1.
|
RO | 0b000 | ||||||||||||||||||||
| Address Offset | 0x0000 0080 | ||
| Physical Address | 0xE000 ED7C | Instance | 0xE000 ED7C |
| Description | The CTR provides information about the architecture of the currently selected cache | ||
| Type | |||
| Bits | Field Name | Description | Type | Reset | ||
| 31 | RES1 | Reserved, RES1 | RO | 1 | ||
| 30:28 | RES0 | Reserved, RES0 | RO | 0b000 | ||
| 27:24 | CWG | Log2 of the number of words of the maximum size of memory that can be overwritten as a result of the eviction of a cache entry that has had a memory location in it modified | RO | 0x0 | ||
| 23:20 | ERG | Log2 of the number of words of the maximum size of the reservation granule that has been implemented for the Load-Exclusive and Store-Exclusive instructions | RO | 0x0 | ||
| 19:16 | DminLine | Log2 of the number of words in the smallest cache line of all the data caches and unified caches that are controlled by the PE | RO | 0x0 | ||
| 15:14 | RES1_1 | Reserved, RES1 | RO | 0b11 | ||
| 13:4 | RES0_1 | Reserved, RES0 | RO | 0b00 0000 0000 | ||
| 3:0 | IminLine | Log2 of the number of words in the smallest cache line of all the instruction caches that are controlled by the PE | RO | 0x0 | ||
| Address Offset | 0x0000 0084 | ||
| Physical Address | 0xE000 ED80 | Instance | 0xE000 ED80 |
| Description | Provides information about the architecture of the caches. CCSIDR is RES0 if CLIDR is zero. | ||
| Type | |||
| Bits | Field Name | Description | Type | Reset | |||||||||||
| 31 | WT | Indicates whether the currently selected cache level supports Write-Through
|
RO | 1 | |||||||||||
| 30 | WB | Indicates whether the currently selected cache level supports Write-Back
|
RO | 0 | |||||||||||
| 29 | RA | Indicates whether the currently selected cache level supports read-allocation
|
RO | 0 | |||||||||||
| 28 | WA | Indicates whether the currently selected cache level supports write-allocation
|
RO | 0 | |||||||||||
| 27:13 | NumSets | Indicates (Number of sets in the currently selected cache) - 1. Therefore, a value of 0 indicates that 1 is set in the cache. The number of sets does not have to be a power of 2 |
RO | 0b000 0000 0000 0110 | |||||||||||
| 12:3 | Associativity | Indicates (Associativity of cache) - 1. A value of 0 indicates an associativity of 1. The associativity does not have to be a power of 2 |
RO | 0b00 0000 0000 | |||||||||||
| 2:0 | LineSize | Indicates (Log2(Number of words per line in the currently selected cache)) - 2. | RO | 0b000 | |||||||||||
| Address Offset | 0x0000 0088 | ||
| Physical Address | 0xE000 ED84 | Instance | 0xE000 ED84 |
| Description | Selects the current Cache Size ID Register, CCSIDR, by specifying the required cache level and the cache type (either instruction or data cache) |
||
| Type | |||
| Bits | Field Name | Description | Type | Reset | ||||||||||||||||||||||||||
| 31:4 | Res0 | Reserved,Res0 | RO | 0x800 0C00 | ||||||||||||||||||||||||||
| 3:1 | Level | Selects which cache level is to be identified. Permitted values are from 0b000, indicating Level 1 cache, to 0b110 indicating Level 7 cache
|
RO | 0b000 | ||||||||||||||||||||||||||
| 0 | InD | Selects whether the instruction or the data cache is to be identified
|
RO | 0 | ||||||||||||||||||||||||||
| Address Offset | 0x0000 008C | ||
| Physical Address | 0xE000 ED88 | Instance | 0xE000 ED88 |
| Description | Specifies the access privileges for coprocessors and the FP Extension | ||
| Type | |||
| Bits | Field Name | Description | Type | Reset | ||
| 31:24 | RES0 | Reserved, RES0 | RO | 0x00 | ||
| 23:22 | CP11 | The value in this field is ignored. If the implementation does not include the FP Extension, this field is RAZ/WI. If the value of this bit is not programmed to the same value as the CP10 field, then the value is UNKNOWN | RW | 0b00 | ||
| 21:20 | CP10 | Defines the access rights for the floating-point functionality | RW | 0b00 | ||
| 19:16 | RES0_1 | Reserved, RES0 | RO | 0x0 | ||
| 15:14 | CP7 | Controls access privileges for coprocessor 7 | RW | 0b00 | ||
| 13:12 | CP6 | Controls access privileges for coprocessor 6 | RW | 0b00 | ||
| 11:10 | CP5 | Controls access privileges for coprocessor 5 | RW | 0b00 | ||
| 9:8 | CP4 | Controls access privileges for coprocessor 4 | RW | 0b00 | ||
| 7:6 | CP3 | Controls access privileges for coprocessor 3 | RW | 0b00 | ||
| 5:4 | CP2 | Controls access privileges for coprocessor 2 | RW | 0b00 | ||
| 3:2 | CP1 | Controls access privileges for coprocessor 1 | RW | 0b00 | ||
| 1:0 | CP0 | Controls access privileges for coprocessor 0 | RW | 0b00 | ||
| Address Offset | 0x0000 0090 | ||
| Physical Address | 0xE000 ED8C | Instance | 0xE000 ED8C |
| Description | Defines the Non-secure access permissions for both the FP Extension and coprocessors CP0 to CP7 | ||
| Type | |||
| Bits | Field Name | Description | Type | Reset | ||
| 31:12 | RES0 | Reserved, RES0 | RO | 0x0 0000 | ||
| 11 | CP11 | Enables Non-secure access to the Floating-point Extension | RW | 0 | ||
| 10 | CP10 | Enables Non-secure access to the Floating-point Extension | RW | 0 | ||
| 9:8 | RES0_1 | Reserved, RES0 | RO | 0b00 | ||
| 7 | CP7 | Enables Non-secure access to coprocessor CP7 | RW | 0 | ||
| 6 | CP6 | Enables Non-secure access to coprocessor CP6 | RW | 0 | ||
| 5 | CP5 | Enables Non-secure access to coprocessor CP5 | RW | 0 | ||
| 4 | CP4 | Enables Non-secure access to coprocessor CP4 | RW | 0 | ||
| 3 | CP3 | Enables Non-secure access to coprocessor CP3 | RW | 0 | ||
| 2 | CP2 | Enables Non-secure access to coprocessor CP2 | RW | 0 | ||
| 1 | CP1 | Enables Non-secure access to coprocessor CP1 | RW | 0 | ||
| 0 | CP0 | Enables Non-secure access to coprocessor CP0 | RW | 0 | ||
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