SAU

Instance: SAU
Component: SAU
Base address: 0xE000EDD0


TOP:SAU Register Summary

Register Name

Type

Register Width (Bits)

Register Reset

Address Offset

Physical Address

SAU_CTRL

32

0x0000 0000

0x0000 0000

0xE000 EDD0

SAU_TYPE

32

0x0000 0004

0x0000 0004

0xE000 EDD4

SAU_RNR

32

0x0000 0000

0x0000 0008

0xE000 EDD8

SAU_RBAR

32

0x0000 0000

0x0000 000C

0xE000 EDDC

SAU_RLAR

32

0x0000 0000

0x0000 0010

0xE000 EDE0

SFSR

32

0x0000 0000

0x0000 0014

0xE000 EDE4

SFAR

32

0x0000 0000

0x0000 0018

0xE000 EDE8

TOP:SAU Register Descriptions

TOP:SAU:SAU_CTRL

Address Offset 0x0000 0000
Physical Address 0xE000 EDD0 Instance 0xE000 EDD0
Description Allows enabling of the Security Attribution Unit
Type
Bits Field Name Description Type Reset
31:2 RES0 Reserved, RES0 RO 0b00 0000 0000 0000 0000 0000 0000 0000
1 ALLNS When SAU_CTRL.ENABLE is 0 this bit controls if the memory is marked as Non-secure or Secure RW 0
0 ENABLE Enables the SAU RW 0

TOP:SAU:SAU_TYPE

Address Offset 0x0000 0004
Physical Address 0xE000 EDD4 Instance 0xE000 EDD4
Description Indicates the number of regions implemented by the Security Attribution Unit
Type
Bits Field Name Description Type Reset
31:8 RES0 Reserved, RES0 RO 0x00 0000
7:0 SREGION The number of implemented SAU regions RO 0x04

TOP:SAU:SAU_RNR

Address Offset 0x0000 0008
Physical Address 0xE000 EDD8 Instance 0xE000 EDD8
Description Selects the region currently accessed by SAU_RBAR and SAU_RLAR
Type
Bits Field Name Description Type Reset
31:8 RES0 Reserved, RES0 RO 0x00 0000
7:0 REGION Indicates the SAU region accessed by SAU_RBAR and SAU_RLAR RW 0x00

TOP:SAU:SAU_RBAR

Address Offset 0x0000 000C
Physical Address 0xE000 EDDC Instance 0xE000 EDDC
Description Provides indirect read and write access to the base address of the currently selected SAU region
Type
Bits Field Name Description Type Reset
31:5 BADDR Holds bits [31:5] of the base address for the selected SAU region RW 0b000 0000 0000 0000 0000 0000 0000
4:0 RES0 Reserved, RES0 RO 0b0 0000

TOP:SAU:SAU_RLAR

Address Offset 0x0000 0010
Physical Address 0xE000 EDE0 Instance 0xE000 EDE0
Description Provides indirect read and write access to the limit address of the currently selected SAU region
Type
Bits Field Name Description Type Reset
31:5 LADDR Holds bits [31:5] of the limit address for the selected SAU region RW 0b000 0000 0000 0000 0000 0000 0000
4:2 RES0 Reserved, RES0 RO 0b000
1 NSC Controls whether Non-secure state is permitted to execute an SG instruction from this region RW 0
0 ENABLE SAU region enable RW 0

TOP:SAU:SFSR

Address Offset 0x0000 0014
Physical Address 0xE000 EDE4 Instance 0xE000 EDE4
Description Provides information about any security related faults
Type
Bits Field Name Description Type Reset
31:8 RES0 Reserved, RES0 RO 0x00 0000
7 LSERR Sticky flag indicating that an error occurred during lazy state activation or deactivation RW 0
6 SFARVALID This bit is set when the SFAR register contains a valid value. As with similar fields, such as BFSR.BFARVALID and MMFSR.MMARVALID, this bit can be cleared by other exceptions, such as BusFault RW 0
5 LSPERR Stick flag indicating that an SAU or IDAU violation occurred during the lazy preservation of floating-point state RW 0
4 INVTRAN Sticky flag indicating that an exception was raised due to a branch that was not flagged as being domain crossing causing a transition from Secure to Non-secure memory RW 0
3 AUVIOL Sticky flag indicating that an attempt was made to access parts of the address space that are marked as Secure with NS-Req for the transaction set to Non-secure. This bit is not set if the violation occurred during lazy state preservation. See LSPERR RW 0
2 INVER This can be caused by EXC_RETURN.DCRS being set to 0 when returning from an exception in the Non-secure state, or by EXC_RETURN.ES being set to 1 when returning from an exception in the Non-secure state RW 0
1 INVIS This bit is set if the integrity signature in an exception stack frame is found to be invalid during the unstacking operation RW 0
0 INVEP This bit is set if a function call from the Non-secure state or exception targets a non-SG instruction in the Secure state. This bit is also set if the target address is a SG instruction, but there is no matching SAU/IDAU region with the NSC flag set RW 0

TOP:SAU:SFAR

Address Offset 0x0000 0018
Physical Address 0xE000 EDE8 Instance 0xE000 EDE8
Description Shows the address of the memory location that caused a Security violation
Type
Bits Field Name Description Type Reset
31:0 ADDRESS The address of an access that caused a attribution unit violation. This field is only valid when SFSR.SFARVALID is set. This allows the actual flip flops associated with this register to be shared with other fault address registers. If an implementation chooses to share the storage in this way, care must be taken to not leak Secure address information to the Non-secure state. One way of achieving this is to share the SFAR register with the MMFAR_S register, which is not accessible to the Non-secure state RW 0x0000 0000