Instance: PMCTL
Component: PMCTL
Base address: 0x40000000
This component is the Power Management controller. Together with the System Controller, it controls system resets and the power states of the device.
Register Name |
Type |
Register Width (Bits) |
Register Reset |
Address Offset |
Physical Address |
RO |
32 |
0xD741 0020 |
0x0000 0000 |
0x4000 0000 |
|
RO |
32 |
0xF400 0000 |
0x0000 0004 |
0x4000 0004 |
|
WO |
32 |
0x0000 0000 |
0x0000 0008 |
0x4000 0008 |
|
RW |
32 |
0x0000 0000 |
0x0000 000C |
0x4000 000C |
|
RO |
32 |
0x0000 0001 |
0x0000 0010 |
0x4000 0010 |
|
RW |
32 |
0x0000 0000 |
0x0000 0014 |
0x4000 0014 |
|
WO |
32 |
0x0000 0000 |
0x0000 0020 |
0x4000 0020 |
|
WO |
32 |
0x0000 0000 |
0x0000 0024 |
0x4000 0024 |
|
RO |
32 |
0x0000 0000 |
0x0000 0028 |
0x4000 0028 |
|
RW |
32 |
0x0000 0000 |
0x0000 002C |
0x4000 002C |
|
RO |
32 |
0x0000 0000 |
0x0000 0030 |
0x4000 0030 |
|
RW |
32 |
0x0000 0000 |
0x0000 0034 |
0x4000 0034 |
|
RO |
32 |
0x0000 0000 |
0x0000 003C |
0x4000 003C |
|
WO |
32 |
0x0000 0000 |
0x0000 0040 |
0x4000 0040 |
|
WO |
32 |
0x0000 0000 |
0x0000 0044 |
0x4000 0044 |
|
RO |
32 |
0x0000 0000 |
0x0000 004C |
0x4000 004C |
|
RO |
32 |
0x0000 0000 |
0x0000 0050 |
0x4000 0050 |
|
RW |
32 |
0x0000 0000 |
0x0000 0054 |
0x4000 0054 |
|
RW |
32 |
0x0000 0000 |
0x0000 0058 |
0x4000 0058 |
|
RW |
32 |
0x0000 0000 |
0x0000 0064 |
0x4000 0064 |
|
RW |
32 |
0x0000 0001 |
0x0000 007C |
0x4000 007C |
|
RW |
32 |
0x0000 0001 |
0x0000 0080 |
0x4000 0080 |
|
RW |
32 |
0x0000 0001 |
0x0000 0084 |
0x4000 0084 |
|
RW |
32 |
0x0000 0000 |
0x0000 0088 |
0x4000 0088 |
|
RW |
32 |
0x0000 0000 |
0x0000 008C |
0x4000 008C |
|
RW |
32 |
0x0000 0001 |
0x0000 0090 |
0x4000 0090 |
|
RW |
32 |
0x0000 0000 |
0x0000 0094 |
0x4000 0094 |
|
RW |
32 |
0x0000 0001 |
0x0000 0098 |
0x4000 0098 |
|
RW |
32 |
0x0000 0001 |
0x0000 00A8 |
0x4000 00A8 |
|
RW |
32 |
0x0000 0000 |
0x0000 00AC |
0x4000 00AC |
|
RW |
32 |
0x0000 0011 |
0x0000 00B0 |
0x4000 00B0 |
|
RO |
32 |
0x0000 0000 |
0x0000 00B4 |
0x4000 00B4 |
Address Offset | 0x0000 0000 | ||
Physical Address | 0x4000 0000 | Instance | 0x4000 0000 |
Description | Description Register. This register provides IP module ID, revision information, instance index and standard MMR registers offset. |
||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:16 | MODID | Module identifier used to uniquely identify this IP. | RO | 0xD741 | ||
15:12 | STDIPOFF | Standard IP MMR block offset. Standard IP MMRs are the set of from aggregated IRQ registers till DTB. 0: Standard IP MMRs do not exist 0x1-0xF: Standard IP MMRs begin at offset of (64*STDIPOFF from the base IP address) |
RO | 0x0 | ||
11:8 | INSTIDX | IP Instance ID number. If multiple instances of IP exist in the device, this field can identify the instance number (0-15). | RO | 0x0 | ||
7:4 | MAJREV | Major revision of IP (0-15). | RO | 0x2 | ||
3:0 | MINREV | Minor revision of IP (0-15). | RO | 0x0 |
Address Offset | 0x0000 0004 | ||
Physical Address | 0x4000 0004 | Instance | 0x4000 0004 |
Description | Extended Description Register. This register shows ULL IP availability and memory size configuration. |
||
Type | RO |
Bits | Field Name | Description | Type | Reset | |||||||||||||||||
31:30 | FLASHSZ | System flash availability
|
RO | 0b11 | |||||||||||||||||
29:28 | SRAMSZ | System SRAM availability
|
RO | 0b11 | |||||||||||||||||
27 | RESERVED27 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0 | |||||||||||||||||
26 | LPCMP | LPCMP (low power comparator) IP status on device
|
RO | 1 | |||||||||||||||||
25:0 | RESERVED0 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 0000 0000 0000 0000 0000 |
Address Offset | 0x0000 0008 | ||
Physical Address | 0x4000 0008 | Instance | 0x4000 0008 |
Description | Shutdown Register. This register controls SHUTDOWN mode entry. |
||
Type | WO |
Bits | Field Name | Description | Type | Reset | ||||||||
31:16 | RESERVED16 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0000 | ||||||||
15:0 | KEY | Setting a valid key will trigger the device to enter SHUTDOWN mode.
|
WO | 0x0000 |
Address Offset | 0x0000 000C | ||
Physical Address | 0x4000 000C | Instance | 0x4000 000C |
Description | Sleep Control Register. This register controls I/O pad sleep mode. When I/O pad sleep mode is enabled all I/O pad outputs and I/O pad configurations are latched. Inputs are transparent if I/O pad is configured as input. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:1 | RESERVED1 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0b000 0000 0000 0000 0000 0000 0000 0000 | |||||||||||
0 | SLPN | The boot code will set this bit field and disable sleep mode, automatically unless waking up from a SHUTDOWN RSTSTA.SDDET is set. Application software must reconfigure the state for all IO's before setting this bit field upon waking up from a SHUTDOWN to avoid glitches on pins.
|
RW | 0 |
Address Offset | 0x0000 0010 | ||
Physical Address | 0x4000 0010 | Instance | 0x4000 0010 |
Description | Wakeup Status Register This register shows the device wakeup source. Used to distinguish between wakeup from STANDBY, SHUTDOWN and reset. |
||
Type | RO |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:2 | RESERVED2 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 0000 0000 0000 0000 0000 0000 | |||||||||||
1:0 | SRC | This field shows the device wakeup source.
|
RO | 0b01 |
Address Offset | 0x0000 0014 | ||
Physical Address | 0x4000 0014 | Instance | 0x4000 0014 |
Description | VDDR Control Register. This register contains VDDR regulator settings for the device. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:2 | RESERVED2 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 0000 0000 0000 0000 0000 0000 | |||||||||||
1 | STBY | Select between continuous or duty-cycled VDDR regulation in STANDBY mode.
|
RW | 0 | |||||||||||
0 | SELECT | Select between GLDO and DCDC as VDDR regulator (in ACTIVE, IDLE and STANDBY mode).
|
RW | 0 |
Address Offset | 0x0000 0020 | ||
Physical Address | 0x4000 0020 | Instance | 0x4000 0020 |
Description | Internal. Only to be used through TI provided API. | ||
Type | WO |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:3 | RESERVED3 | Internal. Only to be used through TI provided API. | RO | 0b0 0000 0000 0000 0000 0000 0000 0000 | |||||||||||
2 | FLAG2 | Internal. Only to be used through TI provided API.
|
WO | 0 | |||||||||||
1 | FLAG1 | Internal. Only to be used through TI provided API.
|
WO | 0 | |||||||||||
0 | FLAG0 | Internal. Only to be used through TI provided API.
|
WO | 0 |
Address Offset | 0x0000 0024 | ||
Physical Address | 0x4000 0024 | Instance | 0x4000 0024 |
Description | Internal. Only to be used through TI provided API. | ||
Type | WO |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:3 | RESERVED3 | Internal. Only to be used through TI provided API. | RO | 0b0 0000 0000 0000 0000 0000 0000 0000 | |||||||||||
2 | FLAG2 | Internal. Only to be used through TI provided API.
|
WO | 0 | |||||||||||
1 | FLAG1 | Internal. Only to be used through TI provided API.
|
WO | 0 | |||||||||||
0 | FLAG0 | Internal. Only to be used through TI provided API.
|
WO | 0 |
Address Offset | 0x0000 0028 | ||
Physical Address | 0x4000 0028 | Instance | 0x4000 0028 |
Description | Internal. Only to be used through TI provided API. | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:3 | RESERVED3 | Internal. Only to be used through TI provided API. | RO | 0b0 0000 0000 0000 0000 0000 0000 0000 | |||||||||||
2 | FLAG2 | Internal. Only to be used through TI provided API.
|
RO | 0 | |||||||||||
1 | FLAG1 | Internal. Only to be used through TI provided API.
|
RO | 0 | |||||||||||
0 | FLAG0 | Internal. Only to be used through TI provided API.
|
RO | 0 |
Address Offset | 0x0000 002C | ||
Physical Address | 0x4000 002C | Instance | 0x4000 002C |
Description | Reset Control Register. This register configures and controls system reset. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:4 | RESERVED4 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x000 0000 | |||||||||||
3 | VGMDLYN | VDD glitch monitor delay. This bit configures if exit out of STANDBY will be stalled until VGM has settled or not. When bypassed the CPU execution will potentially start before the VGM is ready.
|
RW | 0 | |||||||||||
2 | LFLOSS | LF clock loss reset enable. Trigger system reset when LF clock loss is detected, which reset the entire device and causes a reboot of the system. The system reset event is captured as RSTSTA.RESETSRC set to SYSRESET and RSTSTA.SYSSRC set to LFLOSSEV.
|
RW | 0 | |||||||||||
1 | TSDEN | TSD (Thermal Shutdown) enable. TSD will trigger an immediate system reset, which reset the entire device and causes a reboot of the system. The device will be in reset until released by the TSD IP. The system reset event is captured as RSTSTA.TSDEV flag set.
|
RW | 0 | |||||||||||
0 | SYSRST | Trigger system reset, which will reset the entire device and causes a reboot of the system. The system reset event is captured as RSTSTA.RESETSRC set to SYSRESET and RSTSTA.SYSSRC set to SYSRSTEV.
|
RW | 0 |
Address Offset | 0x0000 0030 | ||
Physical Address | 0x4000 0030 | Instance | 0x4000 0030 |
Description | Reset Status. This register contains the reset source and SHUTDOWN wakeup source for the system. Check WUSTA.SRC first to ensure that wakeup from STANDBY is not set. The capture feature is not rearmed until all of the possible reset sources have been released and the result has been copied to this register. During the copy and rearm process it is one 24MHz period in which an eventual new system reset will be reported as Power on reset regardless of the root cause. |
||
Type | RO |
Bits | Field Name | Description | Type | Reset | |||||||||||||||||||||||||||||||||||||||||
31:18 | RESERVED18 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 0000 0000 | |||||||||||||||||||||||||||||||||||||||||
17 | SDDET | Wakeup from SHUTDOWN flag. Note: This flag will be cleared when SLPCTL.SLPN is asserted.
|
RO | 0 | |||||||||||||||||||||||||||||||||||||||||
16 | IOWUSD | Wakeup from SHUTDOWN on an I/O event flag. Note: This flag will be cleared when SLPCTL.SLPN is asserted.
|
RO | 0 | |||||||||||||||||||||||||||||||||||||||||
15 | RTCSTA | RTC TIME reset status. This bit shows if the last system reset event cleared RTC TIME or not.
|
RO | 0 | |||||||||||||||||||||||||||||||||||||||||
14:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 | |||||||||||||||||||||||||||||||||||||||||
7:4 | SYSSRC | Shows which reset event that triggered SYSRESET in RESETSRC.
|
RO | 0x0 | |||||||||||||||||||||||||||||||||||||||||
3 | TSDEV | System reset triggered by TSD event
|
RO | 0 | |||||||||||||||||||||||||||||||||||||||||
2:0 | RESETSRC | Shows the root cause of the last system reset. More than one reported reset source can have been active during the last system reset, but only the root cause is reported. If reset cause is SYSRESET or PINRESET, the other reset flags must be read to determine actual root cause.
|
RO | 0b000 |
Address Offset | 0x0000 0034 | ||
Physical Address | 0x4000 0034 | Instance | 0x4000 0034 |
Description | Internal. Only to be used through TI provided API. | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:8 | RESERVED8 | Internal. Only to be used through TI provided API. | RO | 0x00 0000 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
7:0 | FLAG | Internal. Only to be used through TI provided API.
|
RW | 0x00 |
Address Offset | 0x0000 003C | ||
Physical Address | 0x4000 003C | Instance | 0x4000 003C |
Description | AON Register Status 1. This register contains the general purpose AON flags for SW, and is updated through AONRSET1.FLAG and AONRCLR1.FLAG. The register is only reset on a POR event. |
||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:21 | RESERVED21 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 | ||
20 | VDDIOPGIO | VDDIO power good. Controls the I/O pads on the VDDIO segment. |
RO | 0 | ||
19:18 | RESERVED18 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 | ||
17:0 | FLAG | State of the AON register flags | RO | 0b00 0000 0000 0000 0000 |
Address Offset | 0x0000 0040 | ||
Physical Address | 0x4000 0040 | Instance | 0x4000 0040 |
Description | AON Register Set 1. This register sets the AON flags that can be read through AONRSTA1.FLAG. |
||
Type | WO |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:21 | RESERVED21 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 | |||||||||||
20 | VDDIOPGIO | Write 1 to set AONRSTA1.VDDIOPGIO.
|
WO | 0 | |||||||||||
19:18 | RESERVED18 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | WO | 0b00 | |||||||||||
17:0 | FLAG | Write 1 to set AONRSTA1.FLAG
|
WO | 0b00 0000 0000 0000 0000 |
Address Offset | 0x0000 0044 | ||
Physical Address | 0x4000 0044 | Instance | 0x4000 0044 |
Description | AON register clear 1 Clear the AON flags that can be read through AONRSTA1.FLAG |
||
Type | WO |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:21 | RESERVED21 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 | |||||||||||
20 | VDDIOPGIO | Write 1 to clear AONRSTA1.VDDIOPGIO.
|
WO | 0 | |||||||||||
19:18 | RESERVED18 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | WO | 0b00 | |||||||||||
17:0 | FLAG | Write 1 to clear AONRSTA1.FLAG
|
WO | 0b00 0000 0000 0000 0000 |
Address Offset | 0x0000 004C | ||
Physical Address | 0x4000 004C | Instance | 0x4000 004C |
Description | Delta Time Register. This register contains the measured delta time during wakeup from STANDBY mode. |
||
Type | RO |
Bits | Field Name | Description | Type | Reset | |||||||||||||||||
31:30 | SLWP | Slow part. States which of HFXT ready or SW ready that completed first during wakeup from STANDBY mode.
|
RO | 0b00 | |||||||||||||||||
29:12 | RESERVED12 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 0000 0000 0000 | |||||||||||||||||
11:0 | TIME | Delta time. Measured time in us between SWSTMP.SWRDY and HFXT ready. This is a always a positive number, and SLWP is used to determine which event occurred first. Measurement is enabled when PREPUCTL.WUTIMEN is set. |
RO | 0x000 |
Address Offset | 0x0000 0050 | ||
Physical Address | 0x4000 0050 | Instance | 0x4000 0050 |
Description | WakeUp Time Register. This register contains the measured wakeup times from STANDBY mode. |
||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:24 | RESERVED24 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 | ||
23:16 | DIGWU | Digital wakeup time. Gives the time (in us) from HFSOC is running until CPU execution starts. Measurement is enabled when PREPUCTL.WUTIMEN is set. |
RO | 0x00 | ||
15:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 | ||
7:0 | HFXTWU | HFXT wakeup time. Gives the time (in us) from HFSOC is running until HFXT auto enable is triggered. Measurement is enabled when PREPUCTL.WUTIMEN is set. |
RO | 0x00 |
Address Offset | 0x0000 0054 | ||
Physical Address | 0x4000 0054 | Instance | 0x4000 0054 |
Description | Pre Power-Up Control Register. This register contains settings and control for pre-powerup, STANDBY and wakeup measurements. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||
31 | PREPUEN | Pre powerup Enable. When this bit is set, the device will start the wakeup process in advance of the RTC wakeup event. This to start HFXT settling earlier, so that HFXT can be ready when SW is ready. Note that HFXTCTL.AUTO must be enabled to turn on HFXT.
|
RW | 0 | |||||||||||
30 | WUTIMEN | Wakeup time measurement enable. When set will enable WUTIME.DIGWU, WUTIME.HFXTWU and DELTA.TIME time measurements.
|
RW | 0 | |||||||||||
29:16 | RESERVED16 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0b00 0000 0000 0000 | |||||||||||
15:8 | CONS | Conservative pre-wakeup time. When PREPUEN is set, the device will start the wakeup process in advance of the RTC wakeup event. This field will give the conservative time in advance of a RTC event. Conservative value is used if a temperature change has been detected since STANDBY mode was entered. The time unit for the value is 8us.
|
RW | 0x00 | |||||||||||
7:0 | NOM | Nominal pre-wakeup time. When PREPUEN is set, the device will start the wakeup process in advance of the RTC wakeup event. This field will give the nominal time in advance of a RTC event. Nominal value is used if no temperature change has been detected since STANDBY mode was entered. The time unit for the value is 8us.
|
RW | 0x00 |
Address Offset | 0x0000 0058 | ||
Physical Address | 0x4000 0058 | Instance | 0x4000 0058 |
Description | SW Time Stamp Register. This register is used to set the SW time stamp for the delta time measurement. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:1 | RESERVED1 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 0000 0000 | |||||||||||
0 | SWRDY | SW ready. Set by SW to indicate when SW is ready. Used to measure DELTA.TIME and DELTA.SLWP. This bit is auto-cleared by HW.
|
RW | 0 |
Address Offset | 0x0000 0064 | ||
Physical Address | 0x4000 0064 | Instance | 0x4000 0064 |
Description | Internal. Only to be used through TI provided API. | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:0 | RESERVED0 | Internal. Only to be used through TI provided API. | RO | 0x0000 0000 |
Address Offset | 0x0000 007C | ||
Physical Address | 0x4000 007C | Instance | 0x4000 007C |
Description | Internal. Only to be used through TI provided API. | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||
31 | LOCK | Internal. Only to be used through TI provided API.
|
RW | 0 | |||||||||||
30:1 | RESERVED1 | Internal. Only to be used through TI provided API. | RO | 0b00 0000 0000 0000 0000 0000 0000 0000 | |||||||||||
0 | VAL | Internal. Only to be used through TI provided API. | RW | 1 |
Address Offset | 0x0000 0080 | ||
Physical Address | 0x4000 0080 | Instance | 0x4000 0080 |
Description | Internal. Only to be used through TI provided API. | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||
31 | LOCK | Internal. Only to be used through TI provided API.
|
RW | 0 | |||||||||||
30:1 | RESERVED1 | Internal. Only to be used through TI provided API. | RO | 0b00 0000 0000 0000 0000 0000 0000 0000 | |||||||||||
0 | VAL | Internal. Only to be used through TI provided API. | RW | 1 |
Address Offset | 0x0000 0084 | ||
Physical Address | 0x4000 0084 | Instance | 0x4000 0084 |
Description | Internal. Only to be used through TI provided API. | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||
31 | LOCK | Internal. Only to be used through TI provided API.
|
RW | 0 | |||||||||||
30:1 | RESERVED1 | Internal. Only to be used through TI provided API. | RO | 0b00 0000 0000 0000 0000 0000 0000 0000 | |||||||||||
0 | VAL | Internal. Only to be used through TI provided API. | RW | 1 |
Address Offset | 0x0000 0088 | ||
Physical Address | 0x4000 0088 | Instance | 0x4000 0088 |
Description | Internal. Only to be used through TI provided API. | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||
31 | LOCK | Internal. Only to be used through TI provided API.
|
RW | 0 | |||||||||||
30:1 | RESERVED1 | Internal. Only to be used through TI provided API. | RO | 0b00 0000 0000 0000 0000 0000 0000 0000 | |||||||||||
0 | VAL | Internal. Only to be used through TI provided API. | RW | 0 |
Address Offset | 0x0000 008C | ||
Physical Address | 0x4000 008C | Instance | 0x4000 008C |
Description | Internal. Only to be used through TI provided API. | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||
31 | LOCK | Internal. Only to be used through TI provided API.
|
RW | 0 | |||||||||||
30:3 | RESERVED3 | Internal. Only to be used through TI provided API. | RO | 0x000 0000 | |||||||||||
2:0 | VAL | Internal. Only to be used through TI provided API. | RW | 0b000 |
Address Offset | 0x0000 0090 | ||
Physical Address | 0x4000 0090 | Instance | 0x4000 0090 |
Description | Internal. Only to be used through TI provided API. | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||
31 | LOCK | Internal. Only to be used through TI provided API.
|
RW | 0 | |||||||||||
30:2 | RESERVED2 | Internal. Only to be used through TI provided API. | RO | 0b0 0000 0000 0000 0000 0000 0000 0000 | |||||||||||
1:0 | VAL | Internal. Only to be used through TI provided API. | RW | 0b01 |
Address Offset | 0x0000 0094 | ||
Physical Address | 0x4000 0094 | Instance | 0x4000 0094 |
Description | Internal. Only to be used through TI provided API. | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||
31 | LOCK | Internal. Only to be used through TI provided API.
|
RW | 0 | |||||||||||
30:2 | RESERVED2 | Internal. Only to be used through TI provided API. | RO | 0b0 0000 0000 0000 0000 0000 0000 0000 | |||||||||||
1:0 | VAL | Internal. Only to be used through TI provided API. | RW | 0b00 |
Address Offset | 0x0000 0098 | ||
Physical Address | 0x4000 0098 | Instance | 0x4000 0098 |
Description | Internal. Only to be used through TI provided API. | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||
31 | LOCK | Internal. Only to be used through TI provided API.
|
RW | 0 | |||||||||||
30:3 | RESERVED3 | Internal. Only to be used through TI provided API. | RO | 0x000 0000 | |||||||||||
2:0 | VAL | Internal. Only to be used through TI provided API. | RW | 0b001 |
Address Offset | 0x0000 00A8 | ||
Physical Address | 0x4000 00A8 | Instance | 0x4000 00A8 |
Description | HFXT Control Register. This register controls features to turn on/off HFXT automatically. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:2 | RESERVED2 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 0000 0000 0000 0000 0000 0000 | |||||||||||
1 | LFCAL | LF Calibration Enable. Turn on/off HFXT periodically to perform LF oscillator calibration. LF oscillator period and measurement time is configured through LFCAL.
|
RW | 0 | |||||||||||
0 | AUTO | Turn on/off HFXT during STANDBY entry/exit.
|
RW | 1 |
Address Offset | 0x0000 00AC | ||
Physical Address | 0x4000 00AC | Instance | 0x4000 00AC |
Description | Low Frequency Calibration Register. This register contains the period and measurement time setting used for LF oscillator calibration. The LF calibartion feature is enabled through HFXTCTL.LFCAL. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||
31 | QUAL | CKM qualifier configuration. Used to qualify that LF calibration is completed before HFXT is request off.
|
RW | 0 | |||||||||||
30:24 | RESERVED24 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 | |||||||||||
23:16 | MEAS | LFCAL measurment time, given in number of 32kHz periods.
|
RW | 0x00 | |||||||||||
15:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 | |||||||||||
7:0 | PER | LFCAL period time, given in number of 256 * 32kHz periods.
|
RW | 0x00 |
Address Offset | 0x0000 00B0 | ||
Physical Address | 0x4000 00B0 | Instance | 0x4000 00B0 |
Description | Internal. Only to be used through TI provided API. | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:6 | RESERVED6 | Internal. Only to be used through TI provided API. | RO | 0b00 0000 0000 0000 0000 0000 0000 | ||
5:0 | TIMEOUT | Internal. Only to be used through TI provided API. | RW | 0b01 0001 |
Address Offset | 0x0000 00B4 | ||
Physical Address | 0x4000 00B4 | Instance | 0x4000 00B4 |
Description | VREF Status Register. This register contains VREF settling status. |
||
Type | RO |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:1 | RESERVED1 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 0000 0000 | |||||||||||
0 | GOOD | VREF settling / good status.
|
RO | 0 |
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