NVIC

Instance: NVIC
Component: NVIC
Base address: 0xE000E100


TOP:NVIC Register Summary

Register Name

Type

Register Width (Bits)

Register Reset

Address Offset

Physical Address

NVIC_ISER0

32

0x0000 0000

0x0000 0000

0xE000 E100

NVIC_ISER1

32

0x0000 0000

0x0000 0004

0xE000 E104

NVIC_ICER0

32

0x0000 0000

0x0000 0080

0xE000 E180

NVIC_ICER1

32

0x0000 0000

0x0000 0084

0xE000 E184

NVIC_ISPR0

32

0x0000 0000

0x0000 0100

0xE000 E200

NVIC_ISPR1

32

0x0000 0000

0x0000 0104

0xE000 E204

NVIC_ICPR0

32

0x0000 0000

0x0000 0180

0xE000 E280

NVIC_ICPR1

32

0x0000 0000

0x0000 0184

0xE000 E284

NVIC_IABR0

32

0x0000 0000

0x0000 0200

0xE000 E300

NVIC_IABR1

32

0x0000 0000

0x0000 0204

0xE000 E304

NVIC_ITNS0

32

0x0000 0000

0x0000 0280

0xE000 E380

NVIC_ITNS1

32

0x0000 0000

0x0000 0284

0xE000 E384

NVIC_IPR0

32

0x0000 0000

0x0000 0300

0xE000 E400

NVIC_IPR1

32

0x0000 0000

0x0000 0304

0xE000 E404

NVIC_IPR2

32

0x0000 0000

0x0000 0308

0xE000 E408

NVIC_IPR3

32

0x0000 0000

0x0000 030C

0xE000 E40C

NVIC_IPR4

32

0x0000 0000

0x0000 0310

0xE000 E410

NVIC_IPR5

32

0x0000 0000

0x0000 0314

0xE000 E414

NVIC_IPR6

32

0x0000 0000

0x0000 0318

0xE000 E418

NVIC_IPR7

32

0x0000 0000

0x0000 031C

0xE000 E41C

NVIC_IPR8

32

0x0000 0000

0x0000 0320

0xE000 E420

TOP:NVIC Register Descriptions

TOP:NVIC:NVIC_ISER0

Address Offset 0x0000 0000
Physical Address 0xE000 E100 Instance 0xE000 E100
Description Enables or reads the enabled state of each group of 32 interrupts
Type
Bits Field Name Description Type Reset
31:0 SETENA For SETENA[m] in NVIC_ISER*n, indicates whether interrupt 32*n + m is enabled RO 0x0000 0000

TOP:NVIC:NVIC_ISER1

Address Offset 0x0000 0004
Physical Address 0xE000 E104 Instance 0xE000 E104
Description Enables or reads the enabled state of each group of 32 interrupts
Type
Bits Field Name Description Type Reset
31:0 SETENA For SETENA[m] in NVIC_ISER*n, indicates whether interrupt 32*n + m is enabled RO 0x0000 0000

TOP:NVIC:NVIC_ICER0

Address Offset 0x0000 0080
Physical Address 0xE000 E180 Instance 0xE000 E180
Description Clears or reads the enabled state of each group of 32 interrupts
Type
Bits Field Name Description Type Reset
31:0 CLRENA For CLRENA[m] in NVIC_ICER*n, indicates whether interrupt 32*n + m is enabled RO 0x0000 0000

TOP:NVIC:NVIC_ICER1

Address Offset 0x0000 0084
Physical Address 0xE000 E184 Instance 0xE000 E184
Description Clears or reads the enabled state of each group of 32 interrupts
Type
Bits Field Name Description Type Reset
31:0 CLRENA For CLRENA[m] in NVIC_ICER*n, indicates whether interrupt 32*n + m is enabled RO 0x0000 0000

TOP:NVIC:NVIC_ISPR0

Address Offset 0x0000 0100
Physical Address 0xE000 E200 Instance 0xE000 E200
Description Enables or reads the pending state of each group of 32 interrupts
Type
Bits Field Name Description Type Reset
31:0 SETPEND For SETPEND[m] in NVIC_ISPR*n, indicates whether interrupt 32*n + m is pending RO 0x0000 0000

TOP:NVIC:NVIC_ISPR1

Address Offset 0x0000 0104
Physical Address 0xE000 E204 Instance 0xE000 E204
Description Enables or reads the pending state of each group of 32 interrupts
Type
Bits Field Name Description Type Reset
31:0 SETPEND For SETPEND[m] in NVIC_ISPR*n, indicates whether interrupt 32*n + m is pending RO 0x0000 0000

TOP:NVIC:NVIC_ICPR0

Address Offset 0x0000 0180
Physical Address 0xE000 E280 Instance 0xE000 E280
Description Clears or reads the pending state of each group of 32 interrupts
Type
Bits Field Name Description Type Reset
31:0 CLRPEND For CLRPEND[m] in NVIC_ICPR*n, indicates whether interrupt 32*n + m is pending RO 0x0000 0000

TOP:NVIC:NVIC_ICPR1

Address Offset 0x0000 0184
Physical Address 0xE000 E284 Instance 0xE000 E284
Description Clears or reads the pending state of each group of 32 interrupts
Type
Bits Field Name Description Type Reset
31:0 CLRPEND For CLRPEND[m] in NVIC_ICPR*n, indicates whether interrupt 32*n + m is pending RO 0x0000 0000

TOP:NVIC:NVIC_IABR0

Address Offset 0x0000 0200
Physical Address 0xE000 E300 Instance 0xE000 E300
Description For each group of 32 interrupts, shows the active state of each interrupt
Type
Bits Field Name Description Type Reset
31:0 ACTIVE For ACTIVE[m] in NVIC_IABR*n, indicates the active state for interrupt 32*n+m RO 0x0000 0000

TOP:NVIC:NVIC_IABR1

Address Offset 0x0000 0204
Physical Address 0xE000 E304 Instance 0xE000 E304
Description For each group of 32 interrupts, shows the active state of each interrupt
Type
Bits Field Name Description Type Reset
31:0 ACTIVE For ACTIVE[m] in NVIC_IABR*n, indicates the active state for interrupt 32*n+m RO 0x0000 0000

TOP:NVIC:NVIC_ITNS0

Address Offset 0x0000 0280
Physical Address 0xE000 E380 Instance 0xE000 E380
Description For each group of 32 interrupts, determines whether each interrupt targets Non-secure or Secure state
Type
Bits Field Name Description Type Reset
31:0 ITNS For ITNS[m] in NVIC_ITNS*n, `IAAMO the target Security state for interrupt 32*n+m RW 0x0000 0000

TOP:NVIC:NVIC_ITNS1

Address Offset 0x0000 0284
Physical Address 0xE000 E384 Instance 0xE000 E384
Description For each group of 32 interrupts, determines whether each interrupt targets Non-secure or Secure state
Type
Bits Field Name Description Type Reset
31:0 ITNS For ITNS[m] in NVIC_ITNS*n, `IAAMO the target Security state for interrupt 32*n+m RW 0x0000 0000

TOP:NVIC:NVIC_IPR0

Address Offset 0x0000 0300
Physical Address 0xE000 E400 Instance 0xE000 E400
Description Sets or reads interrupt priorities
Type
Bits Field Name Description Type Reset
31:27 RESERVED27 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000
26:24 PRI_N3 For register NVIC_IPR*n, `IAAMO the priority of interrupt number 4*n+2, or is RES0 if the PE does not implement this interrupt RO 0b000
23:19 RESERVED19 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000
18:16 PRI_N2 For register NVIC_IPR*n, `IAAMO the priority of interrupt number 4*n+2, or is RES0 if the PE does not implement this interrupt RO 0b000
15:11 RESERVED11 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000
10:8 PRI_N1 For register NVIC_IPR*n, `IAAMO the priority of interrupt number 4*n+1, or is RES0 if the PE does not implement this interrupt RO 0b000
7:3 RESERVED3 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000
2:0 PRI_N0 For register NVIC_IPR*n, `IAAMO the priority of interrupt number 4*n+0, or is RES0 if the PE does not implement this interrupt RO 0b000

TOP:NVIC:NVIC_IPR1

Address Offset 0x0000 0304
Physical Address 0xE000 E404 Instance 0xE000 E404
Description Sets or reads interrupt priorities
Type
Bits Field Name Description Type Reset
31:27 RESERVED27 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000
26:24 PRI_N3 For register NVIC_IPR*n, `IAAMO the priority of interrupt number 4*n+2, or is RES0 if the PE does not implement this interrupt RO 0b000
23:19 RESERVED19 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000
18:16 PRI_N2 For register NVIC_IPR*n, `IAAMO the priority of interrupt number 4*n+2, or is RES0 if the PE does not implement this interrupt RO 0b000
15:11 RESERVED11 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000
10:8 PRI_N1 For register NVIC_IPR*n, `IAAMO the priority of interrupt number 4*n+1, or is RES0 if the PE does not implement this interrupt RO 0b000
7:3 RESERVED3 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000
2:0 PRI_N0 For register NVIC_IPR*n, `IAAMO the priority of interrupt number 4*n+0, or is RES0 if the PE does not implement this interrupt RO 0b000

TOP:NVIC:NVIC_IPR2

Address Offset 0x0000 0308
Physical Address 0xE000 E408 Instance 0xE000 E408
Description Sets or reads interrupt priorities
Type
Bits Field Name Description Type Reset
31:27 RESERVED27 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000
26:24 PRI_N3 For register NVIC_IPR*n, `IAAMO the priority of interrupt number 4*n+2, or is RES0 if the PE does not implement this interrupt RO 0b000
23:19 RESERVED19 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000
18:16 PRI_N2 For register NVIC_IPR*n, `IAAMO the priority of interrupt number 4*n+2, or is RES0 if the PE does not implement this interrupt RO 0b000
15:11 RESERVED11 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000
10:8 PRI_N1 For register NVIC_IPR*n, `IAAMO the priority of interrupt number 4*n+1, or is RES0 if the PE does not implement this interrupt RO 0b000
7:3 RESERVED3 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000
2:0 PRI_N0 For register NVIC_IPR*n, `IAAMO the priority of interrupt number 4*n+0, or is RES0 if the PE does not implement this interrupt RO 0b000

TOP:NVIC:NVIC_IPR3

Address Offset 0x0000 030C
Physical Address 0xE000 E40C Instance 0xE000 E40C
Description Sets or reads interrupt priorities
Type
Bits Field Name Description Type Reset
31:27 RESERVED27 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000
26:24 PRI_N3 For register NVIC_IPR*n, `IAAMO the priority of interrupt number 4*n+2, or is RES0 if the PE does not implement this interrupt RO 0b000
23:19 RESERVED19 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000
18:16 PRI_N2 For register NVIC_IPR*n, `IAAMO the priority of interrupt number 4*n+2, or is RES0 if the PE does not implement this interrupt RO 0b000
15:11 RESERVED11 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000
10:8 PRI_N1 For register NVIC_IPR*n, `IAAMO the priority of interrupt number 4*n+1, or is RES0 if the PE does not implement this interrupt RO 0b000
7:3 RESERVED3 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000
2:0 PRI_N0 For register NVIC_IPR*n, `IAAMO the priority of interrupt number 4*n+0, or is RES0 if the PE does not implement this interrupt RO 0b000

TOP:NVIC:NVIC_IPR4

Address Offset 0x0000 0310
Physical Address 0xE000 E410 Instance 0xE000 E410
Description Sets or reads interrupt priorities
Type
Bits Field Name Description Type Reset
31:27 RESERVED27 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000
26:24 PRI_N3 For register NVIC_IPR*n, `IAAMO the priority of interrupt number 4*n+2, or is RES0 if the PE does not implement this interrupt RO 0b000
23:19 RESERVED19 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000
18:16 PRI_N2 For register NVIC_IPR*n, `IAAMO the priority of interrupt number 4*n+2, or is RES0 if the PE does not implement this interrupt RO 0b000
15:11 RESERVED11 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000
10:8 PRI_N1 For register NVIC_IPR*n, `IAAMO the priority of interrupt number 4*n+1, or is RES0 if the PE does not implement this interrupt RO 0b000
7:3 RESERVED3 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000
2:0 PRI_N0 For register NVIC_IPR*n, `IAAMO the priority of interrupt number 4*n+0, or is RES0 if the PE does not implement this interrupt RO 0b000

TOP:NVIC:NVIC_IPR5

Address Offset 0x0000 0314
Physical Address 0xE000 E414 Instance 0xE000 E414
Description Sets or reads interrupt priorities
Type
Bits Field Name Description Type Reset
31:27 RESERVED27 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000
26:24 PRI_N3 For register NVIC_IPR*n, `IAAMO the priority of interrupt number 4*n+2, or is RES0 if the PE does not implement this interrupt RO 0b000
23:19 RESERVED19 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000
18:16 PRI_N2 For register NVIC_IPR*n, `IAAMO the priority of interrupt number 4*n+2, or is RES0 if the PE does not implement this interrupt RO 0b000
15:11 RESERVED11 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000
10:8 PRI_N1 For register NVIC_IPR*n, `IAAMO the priority of interrupt number 4*n+1, or is RES0 if the PE does not implement this interrupt RO 0b000
7:3 RESERVED3 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000
2:0 PRI_N0 For register NVIC_IPR*n, `IAAMO the priority of interrupt number 4*n+0, or is RES0 if the PE does not implement this interrupt RO 0b000

TOP:NVIC:NVIC_IPR6

Address Offset 0x0000 0318
Physical Address 0xE000 E418 Instance 0xE000 E418
Description Sets or reads interrupt priorities
Type
Bits Field Name Description Type Reset
31:27 RESERVED27 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000
26:24 PRI_N3 For register NVIC_IPR*n, `IAAMO the priority of interrupt number 4*n+2, or is RES0 if the PE does not implement this interrupt RO 0b000
23:19 RESERVED19 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000
18:16 PRI_N2 For register NVIC_IPR*n, `IAAMO the priority of interrupt number 4*n+2, or is RES0 if the PE does not implement this interrupt RO 0b000
15:11 RESERVED11 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000
10:8 PRI_N1 For register NVIC_IPR*n, `IAAMO the priority of interrupt number 4*n+1, or is RES0 if the PE does not implement this interrupt RO 0b000
7:3 RESERVED3 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000
2:0 PRI_N0 For register NVIC_IPR*n, `IAAMO the priority of interrupt number 4*n+0, or is RES0 if the PE does not implement this interrupt RO 0b000

TOP:NVIC:NVIC_IPR7

Address Offset 0x0000 031C
Physical Address 0xE000 E41C Instance 0xE000 E41C
Description Sets or reads interrupt priorities
Type
Bits Field Name Description Type Reset
31:27 RESERVED27 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000
26:24 PRI_N3 For register NVIC_IPR*n, `IAAMO the priority of interrupt number 4*n+2, or is RES0 if the PE does not implement this interrupt RO 0b000
23:19 RESERVED19 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000
18:16 PRI_N2 For register NVIC_IPR*n, `IAAMO the priority of interrupt number 4*n+2, or is RES0 if the PE does not implement this interrupt RO 0b000
15:11 RESERVED11 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000
10:8 PRI_N1 For register NVIC_IPR*n, `IAAMO the priority of interrupt number 4*n+1, or is RES0 if the PE does not implement this interrupt RO 0b000
7:3 RESERVED3 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000
2:0 PRI_N0 For register NVIC_IPR*n, `IAAMO the priority of interrupt number 4*n+0, or is RES0 if the PE does not implement this interrupt RO 0b000

TOP:NVIC:NVIC_IPR8

Address Offset 0x0000 0320
Physical Address 0xE000 E420 Instance 0xE000 E420
Description Sets or reads interrupt priorities
Type
Bits Field Name Description Type Reset
31:19 RESERVED19 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000 0000 0000
18:16 PRI_N2 For register NVIC_IPR*n, `IAAMO the priority of interrupt number 4*n+2, or is RES0 if the PE does not implement this interrupt RO 0b000
15:11 RESERVED11 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000
10:8 PRI_N1 For register NVIC_IPR*n, `IAAMO the priority of interrupt number 4*n+1, or is RES0 if the PE does not implement this interrupt RO 0b000
7:3 RESERVED3 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000
2:0 PRI_N0 For register NVIC_IPR*n, `IAAMO the priority of interrupt number 4*n+0, or is RES0 if the PE does not implement this interrupt RO 0b000


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