Instance: MPU
Component: MPU
Base address: 0xE000ED90
|
Register Name |
Type |
Register Width (Bits) |
Register Reset |
Address Offset |
Physical Address |
|
32 |
0x0000 0800 |
0x0000 0000 |
0xE000 ED90 |
||
|
32 |
0x0000 0000 |
0x0000 0004 |
0xE000 ED94 |
||
|
32 |
0x0000 0000 |
0x0000 0008 |
0xE000 ED98 |
||
|
32 |
0x0000 0000 |
0x0000 000C |
0xE000 ED9C |
||
|
32 |
0x0000 0000 |
0x0000 0010 |
0xE000 EDA0 |
||
|
32 |
0x0000 0000 |
0x0000 0014 |
0xE000 EDA4 |
||
|
32 |
0x0000 0000 |
0x0000 0018 |
0xE000 EDA8 |
||
|
32 |
0x0000 0000 |
0x0000 001C |
0xE000 EDAC |
||
|
32 |
0x0000 0000 |
0x0000 0020 |
0xE000 EDB0 |
||
|
32 |
0x0000 0000 |
0x0000 0024 |
0xE000 EDB4 |
||
|
32 |
0x0000 0000 |
0x0000 0028 |
0xE000 EDB8 |
||
|
32 |
0x0000 0000 |
0x0000 0030 |
0xE000 EDC0 |
||
|
32 |
0x0000 0000 |
0x0000 0034 |
0xE000 EDC4 |
| Address Offset | 0x0000 0000 | ||
| Physical Address | 0xE000 ED90 | Instance | 0xE000 ED90 |
| Description | The MPU Type Register indicates how many regions the MPU `FTSSS supports | ||
| Type | |||
| Bits | Field Name | Description | Type | Reset | ||
| 31:16 | RES0 | Reserved, RES0 | RO | 0x0000 | ||
| 15:8 | DREGION | Number of regions supported by the MPU | RO | 0x08 | ||
| 7:1 | RES0_1 | Reserved, RES0 | RO | 0b000 0000 | ||
| 0 | SEPARATE | Indicates support for separate instructions and data address regions | RO | 0 | ||
| Address Offset | 0x0000 0004 | ||
| Physical Address | 0xE000 ED94 | Instance | 0xE000 ED94 |
| Description | Enables the MPU and, when the MPU is enabled, controls whether the default memory map is enabled as a background region for privileged accesses, and whether the MPU is enabled for HardFaults, NMIs, and exception handlers when FAULTMASK is set to 1 | ||
| Type | |||
| Bits | Field Name | Description | Type | Reset | ||
| 31:3 | RES0 | Reserved, RES0 | RO | 0b0 0000 0000 0000 0000 0000 0000 0000 | ||
| 2 | PRIVDEFENA | Controls whether the default memory map is enabled for privileged software | RW | 0 | ||
| 1 | HFNMIENA | Controls whether handlers executing with priority less than 0 access memory with the MPU enabled or disabled. This applies to HardFaults, NMIs, and exception handlers when FAULTMASK is set to 1 | RW | 0 | ||
| 0 | ENABLE | Enables the MPU | RW | 0 | ||
| Address Offset | 0x0000 0008 | ||
| Physical Address | 0xE000 ED98 | Instance | 0xE000 ED98 |
| Description | Selects the region currently accessed by MPU_RBAR and MPU_RLAR | ||
| Type | |||
| Bits | Field Name | Description | Type | Reset | ||
| 31:4 | RES0 | Reserved, RES0 | RO | 0x000 0000 | ||
| 3 | RES0_3 | Reserved, RES0 | RO | 0 | ||
| 2:0 | REGION | Indicates the memory region accessed by MPU_RBAR and MPU_RLAR | RW | 0b000 | ||
| Address Offset | 0x0000 000C | ||
| Physical Address | 0xE000 ED9C | Instance | 0xE000 ED9C |
| Description | Provides indirect read and write access to the base address of the currently selected MPU region `FTSSS | ||
| Type | |||
| Bits | Field Name | Description | Type | Reset | ||
| 31:5 | BASE | Contains bits [31:5] of the lower inclusive limit of the selected MPU memory region. This value is zero extended to provide the base address to be checked against | RW | 0b000 0000 0000 0000 0000 0000 0000 | ||
| 4:3 | SH | Defines the Shareability domain of this region for Normal memory | RW | 0b00 | ||
| 2:1 | AP | Defines the access permissions for this region | RW | 0b00 | ||
| 0 | XN | Defines whether code can be executed from this region | RW | 0 | ||
| Address Offset | 0x0000 0010 | ||
| Physical Address | 0xE000 EDA0 | Instance | 0xE000 EDA0 |
| Description | Provides indirect read and write access to the limit address of the currently selected MPU region `FTSSS | ||
| Type | |||
| Bits | Field Name | Description | Type | Reset | ||
| 31:5 | LIMIT | Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region. This value is postfixed with 0x1F to provide the limit address to be checked against | RW | 0b000 0000 0000 0000 0000 0000 0000 | ||
| 4 | RES0 | Reserved, RES0 | RO | 0 | ||
| 3:1 | AttrIndx | Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields | RW | 0b000 | ||
| 0 | EN | Region enable | RW | 0 | ||
| Address Offset | 0x0000 0014 | ||
| Physical Address | 0xE000 EDA4 | Instance | 0xE000 EDA4 |
| Description | Provides indirect read and write access to the base address of the MPU region selected by MPU_RNR[7:2]:(1[1:0]) `FTSSS | ||
| Type | |||
| Bits | Field Name | Description | Type | Reset | ||
| 31:5 | BASE | Contains bits [31:5] of the lower inclusive limit of the selected MPU memory region. This value is zero extended to provide the base address to be checked against | RW | 0b000 0000 0000 0000 0000 0000 0000 | ||
| 4:3 | SH | Defines the Shareability domain of this region for Normal memory | RW | 0b00 | ||
| 2:1 | AP | Defines the access permissions for this region | RW | 0b00 | ||
| 0 | XN | Defines whether code can be executed from this region | RW | 0 | ||
| Address Offset | 0x0000 0018 | ||
| Physical Address | 0xE000 EDA8 | Instance | 0xE000 EDA8 |
| Description | Provides indirect read and write access to the limit address of the currently selected MPU region selected by MPU_RNR[7:2]:(1[1:0]) `FTSSS | ||
| Type | |||
| Bits | Field Name | Description | Type | Reset | ||
| 31:5 | LIMIT | Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region. This value is postfixed with 0x1F to provide the limit address to be checked against | RW | 0b000 0000 0000 0000 0000 0000 0000 | ||
| 4 | RES0 | Reserved, RES0 | RO | 0 | ||
| 3:1 | AttrIndx | Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields | RW | 0b000 | ||
| 0 | EN | Region enable | RW | 0 | ||
| Address Offset | 0x0000 001C | ||
| Physical Address | 0xE000 EDAC | Instance | 0xE000 EDAC |
| Description | Provides indirect read and write access to the base address of the MPU region selected by MPU_RNR[7:2]:(2[1:0]) `FTSSS | ||
| Type | |||
| Bits | Field Name | Description | Type | Reset | ||
| 31:5 | BASE | Contains bits [31:5] of the lower inclusive limit of the selected MPU memory region. This value is zero extended to provide the base address to be checked against | RW | 0b000 0000 0000 0000 0000 0000 0000 | ||
| 4:3 | SH | Defines the Shareability domain of this region for Normal memory | RW | 0b00 | ||
| 2:1 | AP | Defines the access permissions for this region | RW | 0b00 | ||
| 0 | XN | Defines whether code can be executed from this region | RW | 0 | ||
| Address Offset | 0x0000 0020 | ||
| Physical Address | 0xE000 EDB0 | Instance | 0xE000 EDB0 |
| Description | Provides indirect read and write access to the limit address of the currently selected MPU region selected by MPU_RNR[7:2]:(2[1:0]) `FTSSS | ||
| Type | |||
| Bits | Field Name | Description | Type | Reset | ||
| 31:5 | LIMIT | Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region. This value is postfixed with 0x1F to provide the limit address to be checked against | RW | 0b000 0000 0000 0000 0000 0000 0000 | ||
| 4 | RES0 | Reserved, RES0 | RO | 0 | ||
| 3:1 | AttrIndx | Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields | RW | 0b000 | ||
| 0 | EN | Region enable | RW | 0 | ||
| Address Offset | 0x0000 0024 | ||
| Physical Address | 0xE000 EDB4 | Instance | 0xE000 EDB4 |
| Description | Provides indirect read and write access to the base address of the MPU region selected by MPU_RNR[7:2]:(3[1:0]) `FTSSS | ||
| Type | |||
| Bits | Field Name | Description | Type | Reset | ||
| 31:5 | BASE | Contains bits [31:5] of the lower inclusive limit of the selected MPU memory region. This value is zero extended to provide the base address to be checked against | RW | 0b000 0000 0000 0000 0000 0000 0000 | ||
| 4:3 | SH | Defines the Shareability domain of this region for Normal memory | RW | 0b00 | ||
| 2:1 | AP | Defines the access permissions for this region | RW | 0b00 | ||
| 0 | XN | Defines whether code can be executed from this region | RW | 0 | ||
| Address Offset | 0x0000 0028 | ||
| Physical Address | 0xE000 EDB8 | Instance | 0xE000 EDB8 |
| Description | Provides indirect read and write access to the limit address of the currently selected MPU region selected by MPU_RNR[7:2]:(3[1:0]) `FTSSS | ||
| Type | |||
| Bits | Field Name | Description | Type | Reset | ||
| 31:5 | LIMIT | Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region. This value is postfixed with 0x1F to provide the limit address to be checked against | RW | 0b000 0000 0000 0000 0000 0000 0000 | ||
| 4 | RES0 | Reserved, RES0 | RO | 0 | ||
| 3:1 | AttrIndx | Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields | RW | 0b000 | ||
| 0 | EN | Region enable | RW | 0 | ||
| Address Offset | 0x0000 0030 | ||
| Physical Address | 0xE000 EDC0 | Instance | 0xE000 EDC0 |
| Description | Along with MPU_MAIR1, provides the memory attribute encodings corresponding to the AttrIndex values | ||
| Type | |||
| Bits | Field Name | Description | Type | Reset | ||
| 31:24 | Attr3 | Memory attribute encoding for MPU regions with an AttrIndex of 3 | RW | 0x00 | ||
| 23:16 | Attr2 | Memory attribute encoding for MPU regions with an AttrIndex of 2 | RW | 0x00 | ||
| 15:8 | Attr1 | Memory attribute encoding for MPU regions with an AttrIndex of 1 | RW | 0x00 | ||
| 7:0 | Attr0 | Memory attribute encoding for MPU regions with an AttrIndex of 0 | RW | 0x00 | ||
| Address Offset | 0x0000 0034 | ||
| Physical Address | 0xE000 EDC4 | Instance | 0xE000 EDC4 |
| Description | Along with MPU_MAIR0, provides the memory attribute encodings corresponding to the AttrIndex values | ||
| Type | |||
| Bits | Field Name | Description | Type | Reset | ||
| 31:24 | Attr7 | Memory attribute encoding for MPU regions with an AttrIndex of 7 | RW | 0x00 | ||
| 23:16 | Attr6 | Memory attribute encoding for MPU regions with an AttrIndex of 6 | RW | 0x00 | ||
| 15:8 | Attr5 | Memory attribute encoding for MPU regions with an AttrIndex of 5 | RW | 0x00 | ||
| 7:0 | Attr4 | Memory attribute encoding for MPU regions with an AttrIndex of 4 | RW | 0x00 | ||
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