Instance: ICB
Component: ICB
Base address: 0xE000E000
|
Register Name |
Type |
Register Width (Bits) |
Register Reset |
Address Offset |
Physical Address |
|
32 |
0x0000 0000 |
0x0000 0004 |
0xE000 E004 |
||
|
32 |
0x0000 0000 |
0x0000 0008 |
0xE000 E008 |
| Address Offset | 0x0000 0004 | ||
| Physical Address | 0xE000 E004 | Instance | 0xE000 E004 |
| Description | Provides information about the interrupt controller | ||
| Type | |||
| Bits | Field Name | Description | Type | Reset | ||
| 31:4 | RES0 | Reserved, RES0 | RO | 0x000 0000 | ||
| 3:0 | INTLINESNUM | Indicates the number of the highest implemented register in each of the NVIC control register sets, or in the case of NVIC_IPR*n, 4×INTLINESNUM | RO | 0x0 | ||
| Address Offset | 0x0000 0008 | ||
| Physical Address | 0xE000 E008 | Instance | 0xE000 E008 |
| Description | Provides IMPLEMENTATION DEFINED configuration and control options | ||
| Type | |||
| Bits | Field Name | Description | Type | Reset | ||
| 31:30 | RES0 | Reserved, RES0 | RO | 0b00 | ||
| 29 | EXTEXCLALL | External Exclusives Allowed with no MPU | RW | 0 | ||
| 28:14 | RES0_1 | Reserved, RES0 | RO | 0b000 0000 0000 0000 | ||
| 13 | SBIST | Bit used internally by Software Test Library (STL) | RW | 0 | ||
| 12 | DISITMATBFLUSH | Disable ATB Flush | RW | 0 | ||
| 11 | RES0_2 | Reserved, RES0 | RO | 0 | ||
| 10 | FPEXCODIS | Disable FPU exception outputs | RW | 0 | ||
| 9 | DISOOFP | Disable out-of-order FP instruction completion | RW | 0 | ||
| 8:3 | RES0_3 | Reserved, RES0 | RO | 0b00 0000 | ||
| 2 | DISFOLD | Disable dual-issue. | RW | 0 | ||
| 1 | RES0_4 | Reserved, RES0 | RO | 0 | ||
| 0 | DISMCYCINT | Disable dual-issue. | RW | 0 | ||
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