Instance: HSMCRYPTO
Component: HSMCRYPTO
Base address: 0x400F0000
|
Register Name |
Type |
Register Width (Bits) |
Register Reset |
Address Offset |
Physical Address |
|
RO |
32 |
0x0000 0000 |
0x0000 0000 |
0x400F 0000 |
|
|
WO |
32 |
0x0000 0000 |
0x0000 0000 |
0x400F 0000 |
|
|
RO |
32 |
0x0000 0000 |
0x0000 0400 |
0x400F 0400 |
|
|
WO |
32 |
0x0000 0000 |
0x0000 0400 |
0x400F 0400 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 3E00 |
0x400F 3E00 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 3E04 |
0x400F 3E04 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 3E08 |
0x400F 3E08 |
|
|
RO |
32 |
0x0000 001F |
0x0000 3E0C |
0x400F 3E0C |
|
|
WO |
32 |
0x0000 0000 |
0x0000 3E0C |
0x400F 3E0C |
|
|
RO |
32 |
0x0000 0000 |
0x0000 3E10 |
0x400F 3E10 |
|
|
WO |
32 |
0x0000 0000 |
0x0000 3E10 |
0x400F 3E10 |
|
|
WO |
32 |
0x0000 0000 |
0x0000 3E14 |
0x400F 3E14 |
|
|
RO |
32 |
0x0000 0005 |
0x0000 3E18 |
0x400F 3E18 |
|
|
RO |
32 |
0x0140 36C9 |
0x0000 3E1C |
0x400F 3E1C |
|
|
RO |
32 |
0x0000 0000 |
0x0000 3F00 |
0x400F 3F00 |
|
|
WO |
32 |
0x0000 0000 |
0x0000 3F00 |
0x400F 3F00 |
|
|
RO |
32 |
0x0000 0000 |
0x0000 3F04 |
0x400F 3F04 |
|
|
WO |
32 |
0x0000 0000 |
0x0000 3F04 |
0x400F 3F04 |
|
|
RO |
32 |
0x0000 0000 |
0x0000 3F08 |
0x400F 3F08 |
|
|
RO |
32 |
0x0000 0000 |
0x0000 3F0C |
0x400F 3F0C |
|
|
RW |
32 |
0x0000 0202 |
0x0000 3F10 |
0x400F 3F10 |
|
|
RW |
32 |
0x0000 0100 |
0x0000 3FE0 |
0x400F 3FE0 |
|
|
RO |
32 |
0x0020 003C |
0x0000 3FF4 |
0x400F 3FF4 |
|
|
RO |
32 |
0x0390 0312 |
0x0000 3FF8 |
0x400F 3FF8 |
|
|
RO |
32 |
0x0400 7D82 |
0x0000 3FFC |
0x400F 3FFC |
| Address Offset | 0x0000 0000 | ||
| Physical Address | 0x400F 0000 | Instance | 0x400F 0000 |
| Description | Input Mailbox 1 | ||
| Type | RO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | MEM | RO | 0x0000 0000 | |||
| Address Offset | 0x0000 0000 | ||
| Physical Address | 0x400F 0000 | Instance | 0x400F 0000 |
| Description | Output Mailbox 1 | ||
| Type | WO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | MEM | WO | 0x0000 0000 | |||
| Address Offset | 0x0000 0400 | ||
| Physical Address | 0x400F 0400 | Instance | 0x400F 0400 |
| Description | Input Mailbox 2 | ||
| Type | RO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | MEM | RO | 0x0000 0000 | |||
| Address Offset | 0x0000 0400 | ||
| Physical Address | 0x400F 0400 | Instance | 0x400F 0400 |
| Description | Output Mailbox 2 | ||
| Type | WO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | MEM | WO | 0x0000 0000 | |||
| Address Offset | 0x0000 3E00 | ||
| Physical Address | 0x400F 3E00 | Instance | 0x400F 3E00 |
| Description | AIC Polarity Control Register | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:5 | RESERVED5 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 0000 | ||
| 4 | POLCTRL4 | Individual polarity (high level/rising edge or low level/falling edge) control bits per interrupt input: 0b = Low level/falling edge 1b = High level/rising edge. | RW | 0 | ||
| 3 | POLCTRL3 | Individual polarity (high level/rising edge or low level/falling edge) control bits per interrupt input: 0b = Low level/falling edge 1b = High level/rising edge. | RW | 0 | ||
| 2 | POLCTRL2 | Individual polarity (high level/rising edge or low level/falling edge) control bits per interrupt input: 0b = Low level/falling edge 1b = High level/rising edge. | RW | 0 | ||
| 1 | POLCTRL1 | Individual polarity (high level/rising edge or low level/falling edge) control bits per interrupt input: 0b = Low level/falling edge 1b = High level/rising edge. | RW | 0 | ||
| 0 | POLCTRL0 | Individual polarity (high level/rising edge or low level/falling edge) control bits per interrupt input: 0b = Low level/falling edge 1b = High level/rising edge. | RW | 0 | ||
| Address Offset | 0x0000 3E04 | ||
| Physical Address | 0x400F 3E04 | Instance | 0x400F 3E04 |
| Description | AIC Type Control Register | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:5 | RESERVED5 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 0000 | ||
| 4 | TYPCTRL4 | Signal type (level or edge) control bits for each interrupt input: 0b = level (the interrupt source level determines the raw status). 1b = edge (the interrupt source is connected to an edge detector and the edge detector output determines the raw status). | RW | 0 | ||
| 3 | TYPCTRL3 | Signal type (level or edge) control bits for each interrupt input: 0b = level (the interrupt source level determines the raw status). 1b = edge (the interrupt source is connected to an edge detector and the edge detector output determines the raw status). | RW | 0 | ||
| 2 | TYPCTRL2 | Signal type (level or edge) control bits for each interrupt input: 0b = level (the interrupt source level determines the raw status). 1b = edge (the interrupt source is connected to an edge detector and the edge detector output determines the raw status). | RW | 0 | ||
| 1 | TYPCTRL1 | Signal type (level or edge) control bits for each interrupt input: 0b = level (the interrupt source level determines the raw status). 1b = edge (the interrupt source is connected to an edge detector and the edge detector output determines the raw status). | RW | 0 | ||
| 0 | TYPCTRL | Signal type (level or edge) control bits for each interrupt input: 0b = level (the interrupt source level determines the raw status). 1b = edge (the interrupt source is connected to an edge detector and the edge detector output determines the raw status). | RW | 0 | ||
| Address Offset | 0x0000 3E08 | ||
| Physical Address | 0x400F 3E08 | Instance | 0x400F 3E08 |
| Description | AIC Enable Control Register | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:5 | RESERVED5 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 0000 | ||
| 4:0 | ENCTRL | Individual enable control bits per interrupt input: 0b = Disabled. 1b = Enabled | RW | 0b0 0000 | ||
| Address Offset | 0x0000 3E0C | ||
| Physical Address | 0x400F 3E0C | Instance | 0x400F 3E0C |
| Description | AIC Raw Source Status Register | ||
| Type | RO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:5 | RESERVED5 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 0000 | ||
| 4 | RAWSTAT4 | Individual interrupt status bit before masking with enable_ctrl_r[4] (programmable, reset to 'low level' mode): 0b = Inactive, 1b = Pending. | RO | 1 | ||
| 3 | RAWSTAT3 | Individual interrupt status bit before masking with enable_ctrl_r[3] (programmable, reset to 'low level' mode): 0b = Inactive, 1b = Pending. | RO | 1 | ||
| 2 | RAWSTAT2 | Individual interrupt status bit before masking with enable_ctrl_r[2] (programmable, reset to 'low level' mode): 0b = Inactive, 1b = Pending. | RO | 1 | ||
| 1 | RAWSTAT1 | Individual interrupt status bit before masking with enable_ctrl_r[1] (programmable, reset to 'low level' mode): 0b = Inactive, 1b = Pending. | RO | 1 | ||
| 0 | RAWSTAT0 | Individual interrupt status bit before masking with enable_ctrl_r[0] (programmable, reset to 'low level' mode): 0b = Inactive, 1b = Pending. | RO | 1 | ||
| Address Offset | 0x0000 3E0C | ||
| Physical Address | 0x400F 3E0C | Instance | 0x400F 3E0C |
| Description | AIC Enable Set Registers | ||
| Type | WO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:5 | RESERVED5 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 0000 | ||
| 4:0 | ENSET | Individual interrupt enable bits per interrupt input: 0b = No effect. 1b = Set the corresponding bit in the AICENABLECTRL register, enabling the interrupt. After writing a 1b, there is no need to write a 0b. | WO | 0b0 0000 | ||
| Address Offset | 0x0000 3E10 | ||
| Physical Address | 0x400F 3E10 | Instance | 0x400F 3E10 |
| Description | AIC Enabled Status Register | ||
| Type | RO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:5 | RESERVED5 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 0000 | ||
| 4:0 | ENSTAT | These bits reflect the status of the interrupts after polarity control and optional edge detection, gated with bits in AICENABLECTRL register: 0b = Inactive. 1b = Pending. | RO | 0b0 0000 | ||
| Address Offset | 0x0000 3E10 | ||
| Physical Address | 0x400F 3E10 | Instance | 0x400F 3E10 |
| Description | AIC Acknowledge Register | ||
| Type | WO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:5 | RESERVED5 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 0000 | ||
| 4 | ACK4 | Used to clear edge-detect interrupts: 0b = No effect. 1b = Acknowledge the interrupt signal, clears the edge detector and status bit when in edge detect mode (bit [4] of TYPE_CTRL == 1b). After writing a 1b, there is no need to write a 0b. | RW | 0 | ||
| 3 | ACK3 | Used to clear edge-detect interrupts: 0b = No effect. 1b = Acknowledge the interrupt signal, clears the edge detector and status bit when in edge detect mode (bit [3] of TYPE_CTRL == 1b). After writing a 1b, there is no need to write a 0b. | RW | 0 | ||
| 2 | ACK2 | Used to clear edge-detect interrupts: 0b = No effect. 1b = Acknowledge the interrupt signal, clears the edge detector and status bit when in edge detect mode (bit [2] of TYPE_CTRL == 1b). After writing a 1b, there is no need to write a 0b. | RW | 0 | ||
| 1 | ACK1 | Used to clear edge-detect interrupts: 0b = No effect. 1b = Acknowledge the interrupt signal, clears the edge detector and status bit when in edge detect mode (bit [1] of TYPE_CTRL == 1b). After writing a 1b, there is no need to write a 0b. | RW | 0 | ||
| 0 | ACK0 | Used to clear edge-detect interrupts: 0b = No effect. 1b = Acknowledge the interrupt signal, clears the edge detector and status bit when in edge detect mode (bit [0] of TYPE_CTRL == 1b). After writing a 1b, there is no need to write a 0b. | RW | 0 | ||
| Address Offset | 0x0000 3E14 | ||
| Physical Address | 0x400F 3E14 | Instance | 0x400F 3E14 |
| Description | AIC Enable Clear Register | ||
| Type | WO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:5 | RESERVED5 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 0000 | ||
| 4:0 | ENCLR | Individual interrupt disable bits per interrupt input: 0b = No effect. 1b = Clear the corresponding bit in the AICENABLECTRL register, disabling the interrupt. After writing a 1b, there is no need to write a 0b. | WO | 0b0 0000 | ||
| Address Offset | 0x0000 3E18 | ||
| Physical Address | 0x400F 3E18 | Instance | 0x400F 3E18 |
| Description | AIC Options Register | ||
| Type | RO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:9 | RESERVED9 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 | ||
| 8 | MINIREGMAP | Mini register map. | RO | 0 | ||
| 7 | EXTREGMAP | Extended register map. | RO | 0 | ||
| 6 | RESERVED6 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0 | ||
| 5:0 | INPUTS | The number of interrupt request inputs. | RO | 0b00 0101 | ||
| Address Offset | 0x0000 3E1C | ||
| Physical Address | 0x400F 3E1C | Instance | 0x400F 3E1C |
| Description | AIC Version Register | ||
| Type | RO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:28 | RESERVED28 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0 | ||
| 27:24 | MAJORVER | These bits encode the major version number for the AIC module. | RO | 0x1 | ||
| 23:20 | MINORVER | These bits encode the minor version number for the AIC module. | RO | 0x4 | ||
| 19:16 | PATCHLEVEL | These bits encode the hardware patch level for the AIC module, starting at value 0 on the first release. | RO | 0x0 | ||
| 15:8 | AICNUMBERCMPL | These bits simply contain the complement of bits [7:0], used by a driver to ascertain that this version register is indeed read. | RO | 0x36 | ||
| 7:0 | AICNUMBER | These bits encode the AIC number. | RO | 0xC9 | ||
| Address Offset | 0x0000 3F00 | ||
| Physical Address | 0x400F 3F00 | Instance | 0x400F 3F00 |
| Description | Mailbox Status Register | ||
| Type | RO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 0000 | ||
| 7 | MBX2AVAILABLE | (set)-Input Mailbox is linked to a Host or is filled, (Clear)- Input Mailbox is available for linking by this Host | RO | 0 | ||
| 6 | MBX2LINKED | (set)-This Host is linked to Mailbox, (Clear)-This Host is not linked to Mailbox | RO | 0 | ||
| 5 | MBX2OUTFULL | (set)-Output Mailbox contains an output token, (Clear)-Output Mailbox is empty | RO | 0 | ||
| 4 | MBX2INFULL | (set)-Input Mailbox contains a token that is handed over to Internal Controller, (Clear)-Input Mailbox is ready to rceive new token | RO | 0 | ||
| 3 | MBX1AVAILABLE | (set)-Input Mailbox is linked to a Host or is filled, (Clear)- Input Mailbox is available for linking by this Host | RO | 0 | ||
| 2 | MBX1LINKED | (set)-This Host is linked to Mailbox, (Clear)-This Host is not linked to Mailbox | RO | 0 | ||
| 1 | MBX1OUTFULL | (set)-Output Mailbox contains an output token, (Clear)-Output Mailbox is empty | RO | 0 | ||
| 0 | MBX1INFULL | (set)-Input Mailbox contains a token that is handed over to Internal Controller, (Clear)-Input Mailbox is ready to rceive new token | RO | 0 | ||
| Address Offset | 0x0000 3F00 | ||
| Physical Address | 0x400F 3F00 | Instance | 0x400F 3F00 |
| Description | Mailbox Control Register | ||
| Type | WO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 0000 | ||
| 7 | MBX2UNLINK | Set only - Writing a 1b here unlinks the MAilbox from this HOST and clears the mbx_linked bit in MBXSTAT | WO | 0 | ||
| 6 | MBX2LINK | Writing a 1b here links Mailbox to this Host - only if Mailbox not filled and not linked to another host | WO | 0 | ||
| 5 | MBX2OUTEMPTY | Set only - The Host for whom the token in Output Mailbox is meant can clear the mbx_out_full bit in MBXSTAT by writing 1b here. | WO | 0 | ||
| 4 | MBX2INFULL | Set only - The Host linked to mailbox can set the mbx_in_full bit in MBXSTAT by writing 1b here. | WO | 0 | ||
| 3 | MBX1UNLINK | Set only - Writing a 1b here unlinks the MAilbox from this HOST and clears the mbx_linked bit in MBXSTAT | WO | 0 | ||
| 2 | MBX1LINK | Writing a 1b here links Mailbox to this Host - only if Mailbox not filled and not linked to another host | WO | 0 | ||
| 1 | MBX1OUTEMPTY | Set only - The Host for whom the token in Output Mailbox is meant can clear the mbx_out_full bit in MBXSTAT by writing 1b here. | WO | 0 | ||
| 0 | MBX1INFULL | Set only - The Host linked to mailbox can set the mbx_in_full bit in MBXSTAT by writing 1b here. | WO | 0 | ||
| Address Offset | 0x0000 3F04 | ||
| Physical Address | 0x400F 3F04 | Instance | 0x400F 3F04 |
| Description | Raw (unmasked) Mailbox Status Register | ||
| Type | RO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:7 | RESERVED7 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 0000 | ||
| 6 | MBX2LINKED | (set)-This Host is linked to Mailbox mbx%d , (Clear)-This Host is not linked to Mailbox mbx%d | RO | 0 | ||
| 5 | MBX2OUTFULL | (set)-Output Mailbox contains an output token, (Clear)-Output Mailbox mbx%d is empty | RO | 0 | ||
| 4 | MBX2INFULL | (set)-Input Mailbox contains a token that is handed over to Internal Controller, (Clear)-Input Mailbox mbx%d is ready to rceive new token | RO | 0 | ||
| 3 | RESERVED3 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0 | ||
| 2 | MBX1LINKED | (set)-This Host is linked to Mailbox mbx%d , (Clear)-This Host is not linked to Mailbox mbx%d | RO | 0 | ||
| 1 | MBX1OUTFULL | (set)-Output Mailbox contains an output token, (Clear)-Output Mailbox mbx%d is empty | RO | 0 | ||
| 0 | MBX1INFULL | (set)-Input Mailbox contains a token that is handed over to Internal Controller, (Clear)-Input Mailbox mbx%d is ready to rceive new token | RO | 0 | ||
| Address Offset | 0x0000 3F04 | ||
| Physical Address | 0x400F 3F04 | Instance | 0x400F 3F04 |
| Description | Mailbox Reset Register | ||
| Type | WO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 0000 | ||
| 7 | MBX2UNLINK | Set only - Master Host can unlink mbx from it's current Host by writing 1b here. | WO | 0 | ||
| 6 | RESERVED6 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0 | ||
| 5 | MBX2OUTEMPTY | Set only - Master Host can clear mbx_out_full bit in MBXSTAT by writing 1b here. | WO | 0 | ||
| 4 | RESERVED4 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0 | ||
| 3 | MBX1UNLINK | Set only - Master Host can unlink mbx from it's current Host by writing 1b here. | WO | 0 | ||
| 2 | RESERVED2 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0 | ||
| 1 | MBX1OUTEMPTY | Set only - Master Host can clear mbx_out_full bit in MBXSTAT by writing 1b here. | WO | 0 | ||
| 0 | RESERVED0 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0 | ||
| Address Offset | 0x0000 3F08 | ||
| Physical Address | 0x400F 3F08 | Instance | 0x400F 3F08 |
| Description | Mailbox Status - linked Host IDs Register | ||
| Type | RO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 0000 | ||
| 7 | MBX2PROTACC | 0: Mailbox 2 can be accessed by the Host using protected or non-protected access. 1: Mailbox 2 is only accessible if the Host uses protected access. | RO | 0 | ||
| 6:4 | MBX2LINK_id | Bits[1:0]Host cpu_id of the Host linked to the Mailbox, bit[2] Set - Mailbox is only accessible if Host uses protected access, Clear - Mailbox accessed with protected of non-protected access | RO | 0b000 | ||
| 3 | MBX1PROTACC | 0: Mailbox 1 can be accessed by the Host using protected or non-protected access. 1: Mailbox 1 is only accessible if the Host uses protected access. | RO | 0 | ||
| 2:0 | MBX1LINK_id | Bits[1:0]Host cpu_id of the Host linked to the Mailbox, bit[2] Set - Mailbox is only accessible if Host uses protected access, Clear - Mailbox accessed with protected of non-protected access | RO | 0b000 | ||
| Address Offset | 0x0000 3F0C | ||
| Physical Address | 0x400F 3F0C | Instance | 0x400F 3F0C |
| Description | Mailbox Status - output Host IDs Register | ||
| Type | RO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 0000 | ||
| 7 | MBX2PROTACC | 0: Output mailbox 2 can be accessed by the Host using protected or non-protected access. 1: Output mailbox 2 is only accessible if the Host uses protected access. | RO | 0 | ||
| 6:4 | MBX2OUTID | Bit[1,0] Host cpu_id of the Host allowed to read a result from the Mailbox, bit[2] Set - Out Mailbox is only accessible if Host uses protected access, Clear - Output Mailbox accessed with protected of non-protected access | RO | 0b000 | ||
| 3 | MBX1PROTACC | 0: Output mailbox 1 can be accessed by the Host using protected or non-protected access. 1: Output mailbox 1 is only accessible if the Host uses protected access. | RO | 0 | ||
| 2:0 | MBX1OUTID | Bit[1,0] Host cpu_id of the Host allowed to read a result from the Mailbox, bit[2] Set - Out Mailbox is only accessible if Host uses protected access, Clear - Output Mailbox accessed with protected of non-protected access | RO | 0b000 | ||
| Address Offset | 0x0000 3F10 | ||
| Physical Address | 0x400F 3F10 | Instance | 0x400F 3F10 |
| Description | Host/Mailbox1-4 lockout control Register | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:16 | RESERVED16 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0000 | ||
| 15:8 | MBX2LOCKOUT | Bit map indicates which Hosts are blocked from accessing mailbox | RW | 0x02 | ||
| 7:0 | MBX1LOCKOUT | Bit map indicates which Hosts are blocked from accessing mailbox | RW | 0x02 | ||
| Address Offset | 0x0000 3FE0 | ||
| Physical Address | 0x400F 3FE0 | Instance | 0x400F 3FE0 |
| Description | Module Status Register | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31 | FATALERROR | Read-Only. Set if fatal error occured | RO | 0 | ||
| 30:24 | RESERVED24 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 | ||
| 23 | FWIMGACCEPTED | Read-Only. Set if firmware is to be executed | RO | 0 | ||
| 22 | FWIMGCHKDONE | Read-Only. Set if firmware checks complete | RO | 0 | ||
| 21:11 | RESERVED11 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 | ||
| 10 | CRC24ERROR | Read-Only. Set if CRC on ProgramROM is fails | RO | 0 | ||
| 9 | CRC24OK | Read-Only. Set if CRC on ProgramROM is passes | RO | 0 | ||
| 8 | CRC24BUSY | Read-Only. Set if CRC on ProgramROM is busy | RO | 1 | ||
| 7:2 | RESERVED2 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 | ||
| 1 | NONFIPSMODE | Read-Only. Set if VaultIP is in non-FIPS mode | RO | 0 | ||
| 0 | FIPSMODE | Read-Only. Set if VaultIP is in FIPS mode | RO | 0 | ||
| Address Offset | 0x0000 3FF4 | ||
| Physical Address | 0x400F 3FF4 | Instance | 0x400F 3FF4 |
| Description | Configured options(2) | ||
| Type | RO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:26 | RESERVED26 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 | ||
| 25 | ADDCE10 | Set - an additional crypto engine is available in hardware as custom engine10 | RO | 0 | ||
| 24 | ADDCE9 | Set - an additional crypto engine is available in hardware as custom engine9 | RO | 0 | ||
| 23 | ADDCE8 | Set - an additional crypto engine is available in hardware as custom engine8 | RO | 0 | ||
| 22 | ADDCE7 | Set - an additional crypto engine is available in hardware as custom engine7 | RO | 0 | ||
| 21 | ADDCE6 | Set - an additional crypto engine is available in hardware as custom engine6 | RO | 1 | ||
| 20 | ADDCE5 | Set - an additional crypto engine is available in hardware as custom engine5 | RO | 0 | ||
| 19 | ADDCE4 | Set - an additional crypto engine is available in hardware as custom engine4 | RO | 0 | ||
| 18 | ADDCE3 | Set - an additional crypto engine is available in hardware as custom engine3 | RO | 0 | ||
| 17 | ADDCE2 | Set - an additional crypto engine is available in hardware as custom engine2 | RO | 0 | ||
| 16 | ADDCE1 | Set - an additional crypto engine is available in hardware as custom engine1 | RO | 0 | ||
| 15:13 | RESERVED13 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 | ||
| 12 | BUSIFC | Bus interface type, for both Master and Slave: 0b = 32-bit AHB, 1b = 32-bit AXI | RO | 0 | ||
| 11:10 | RESERVED10 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 | ||
| 9 | PROGRAMRAM | 1b = downloadable RAM based firmware program memory. 0b = ROM only firmware program memory. | RO | 0 | ||
| 8 | CCPU | C capable local cpu available | RO | 0 | ||
| 7:6 | RESERVED6 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 | ||
| 5 | PKCP | PKCP Engine available | RO | 1 | ||
| 4 | CRC | CRC calculation available | RO | 1 | ||
| 3 | TRNG | Set - TRNG engine available | RO | 1 | ||
| 2 | SHA | Set - SHA1/SHA2 combination core available | RO | 1 | ||
| 1 | RESERVED1 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0 | ||
| 0 | DESAES | Set - (3)DES/AES combination crypto core available | RO | 0 | ||
| Address Offset | 0x0000 3FF8 | ||
| Physical Address | 0x400F 3FF8 | Instance | 0x400F 3FF8 |
| Description | Configured options(1) | ||
| Type | RO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:24 | HOSTIDSEC | Bits to indicate which of the 8 possible cpu_id codes on the bus interface are active Hosts with secure access | RO | 0x03 | ||
| 23 | MYIDSEC | Indicates the current protection bit values of the Host actually reading the register | RO | 1 | ||
| 22:20 | MYID | Slave & Master interface support protection bit (secure/non-secure) accesses | RO | 0b001 | ||
| 19 | RESERVED19 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0 | ||
| 18:16 | MASTERID | Value of the cpu_id that designates the Master Host | RO | 0b000 | ||
| 15:8 | HOSTID | Bits to indicate which of the 8 possible cpu_id codes on the bus interface are active | RO | 0x03 | ||
| 7:6 | RESERVED6 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 | ||
| 5:4 | MBXSIZE | Implemented size of Mailbox pairs - 00b-128bytes, 01b-256bytes, 10b-512bytes, 11b-1Kbyte | RO | 0b01 | ||
| 3:0 | MAILBOXES | Number of Input/Output Mailbox pairs | RO | 0x2 | ||
| Address Offset | 0x0000 3FFC | ||
| Physical Address | 0x400F 3FFC | Instance | 0x400F 3FFC |
| Description | Version register | ||
| Type | RO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:28 | RESERVED28 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0 | ||
| 27:24 | MAJORVER | Major Version release number for this module | RO | 0x4 | ||
| 23:20 | MINORVER | Minor Version release number for this module | RO | 0x0 | ||
| 19:16 | PATCHLEVEL | Hardware Patch Level for this module | RO | 0x0 | ||
| 15:8 | NUMBERCMPL | Bit by Bit compliment of IP Number | RO | 0x7D | ||
| 7:0 | NUMBER | IP number | RO | 0x82 | ||
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