Instance: HSM
Component: HSM
Base address: 0x40053000
This is top module of HSM for LOKI, a wrapper for RAMBUS RT-130
|
Register Name |
Type |
Register Width (Bits) |
Register Reset |
Address Offset |
Physical Address |
|
RO |
32 |
0x654F 0010 |
0x0000 0000 |
0x4005 3000 |
|
|
RW |
32 |
0x8000 0000 |
0x0000 0004 |
0x4005 3004 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0008 |
0x4005 3008 |
| Address Offset | 0x0000 0000 | ||
| Physical Address | 0x4005 3000 | Instance | 0x4005 3000 |
| Description | Description Register. This register provides IP module ID, revision information, instance index and standard MMR registers offset. |
||
| Type | RO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:16 | MODID | Module identification contains a unique peripheral identification number. | RO | 0x654F | ||
| 15:12 | STDIPOFF | Standard IP MMR block offset. Standard IP MMRs are the set of from aggregated IRQ registers till DTB. 0: Standard IP MMRs do not exist 0x1-0xF: Standard IP MMRs begin at offset of (64*STDIPOFF from the base IP address) |
RO | 0x0 | ||
| 11:8 | INSTIDX | IP Instance ID number. If multiple instances of IP exist in the device, this field can identify the instance number (0-15). | RO | 0x0 | ||
| 7:4 | MAJREV | Major revision of IP | RO | 0x1 | ||
| 3:0 | MINREV | Minor revision of IP | RO | 0x0 | ||
| Address Offset | 0x0000 0004 | ||
| Physical Address | 0x4005 3004 | Instance | 0x4005 3004 |
| Description | Control Register |
||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | |||||||||||
| 31 | CPUIDUNLK | CPUID Lock. Sets sticky '0' lock for CTL.CPUIDSEL
|
RW | 1 | |||||||||||
| 30 | CPUIDSEL | CPUID Select. Selects between ROMFW CPUID and Application CPUID
|
RW | 0 | |||||||||||
| 29:10 | RESERVED10 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0 0000 | |||||||||||
| 9 | FRST | Force Reset.Asserts reset. This bit is not self clearing
|
RW | 0 | |||||||||||
| 8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0 | |||||||||||
| 7 | REFMARK | Refresher Marker. Trigger writting refresh marker. This bit is auto cleared when programming is done
|
RW | 0 | |||||||||||
| 6 | DMAFWDIS | DMA Firewall Disable
|
RW | 0 | |||||||||||
| 5 | OTPBUSY | OTP Busy. OTP contoller is busy | RO | 0 | |||||||||||
| 4 | OTPEVTST | OTP Event Status.
|
RO | 0 | |||||||||||
| 3 | OTPEVTCLR | OTP Event Clear
|
WO | 0 | |||||||||||
| 2 | OTPEVTEN | OTP Event Enable
|
RW | 0 | |||||||||||
| 1 | PKABORT | PKA Abort. Writing 1 to this bit requests PKA Abort, writing 0 has no effect
|
WO | 0 | |||||||||||
| 1 | RESERVED1 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0 | |||||||||||
| 0 | SWRST | Soft Reset Request. Writing 1 to this bit requests soft reset, writing 0 has no effect. This bit autoclears once softreset is done
|
RW | 0 | |||||||||||
| Address Offset | 0x0000 0008 | ||
| Physical Address | 0x4005 3008 | Instance | 0x4005 3008 |
| Description | Characterization Controls for FRO |
||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | |||||||||||
| 31:13 | RESERVED13 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 | |||||||||||
| 12:8 | FROSEL | Selects FRO to characterize | RW | 0b0 0000 | |||||||||||
| 7:3 | RESERVED3 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 | |||||||||||
| 2 | DLYSEL | Selects delay in target FRO.This input should only be changed when CHARCTL.FROEN = 0
|
RW | 0 | |||||||||||
| 1 | FROEN | Enables selected FRO
|
RW | 0 | |||||||||||
| 0 | EN | Enables` characterization
|
RW | 0 | |||||||||||
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